1 /* 2 * Altera 10/100/1000 triple speed ethernet mac driver 3 * 4 * Copyright (C) 2008 Altera Corporation. 5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <config.h> 12 #include <common.h> 13 #include <malloc.h> 14 #include <net.h> 15 #include <command.h> 16 #include <asm/cache.h> 17 #include <asm/dma-mapping.h> 18 #include <miiphy.h> 19 #include "altera_tse.h" 20 21 /* sgdma debug - print descriptor */ 22 static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc) 23 { 24 debug("SGDMA DEBUG :\n"); 25 debug("desc->source : 0x%x \n", (unsigned int)desc->source); 26 debug("desc->destination : 0x%x \n", (unsigned int)desc->destination); 27 debug("desc->next : 0x%x \n", (unsigned int)desc->next); 28 debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad); 29 debug("desc->destination_pad : 0x%x \n", 30 (unsigned int)desc->destination_pad); 31 debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad); 32 debug("desc->bytes_to_transfer : 0x%x \n", 33 (unsigned int)desc->bytes_to_transfer); 34 debug("desc->actual_bytes_transferred : 0x%x \n", 35 (unsigned int)desc->actual_bytes_transferred); 36 debug("desc->descriptor_status : 0x%x \n", 37 (unsigned int)desc->descriptor_status); 38 debug("desc->descriptor_control : 0x%x \n", 39 (unsigned int)desc->descriptor_control); 40 } 41 42 /* This is a generic routine that the SGDMA mode-specific routines 43 * call to populate a descriptor. 44 * arg1 :pointer to first SGDMA descriptor. 45 * arg2 :pointer to next SGDMA descriptor. 46 * arg3 :Address to where data to be written. 47 * arg4 :Address from where data to be read. 48 * arg5 :no of byte to transaction. 49 * arg6 :variable indicating to generate start of packet or not 50 * arg7 :read fixed 51 * arg8 :write fixed 52 * arg9 :read burst 53 * arg10 :write burst 54 * arg11 :atlantic_channel number 55 */ 56 static void alt_sgdma_construct_descriptor_burst( 57 volatile struct alt_sgdma_descriptor *desc, 58 volatile struct alt_sgdma_descriptor *next, 59 unsigned int *read_addr, 60 unsigned int *write_addr, 61 unsigned short length_or_eop, 62 int generate_eop, 63 int read_fixed, 64 int write_fixed_or_sop, 65 int read_burst, 66 int write_burst, 67 unsigned char atlantic_channel) 68 { 69 /* 70 * Mark the "next" descriptor as "not" owned by hardware. This prevents 71 * The SGDMA controller from continuing to process the chain. This is 72 * done as a single IO write to bypass cache, without flushing 73 * the entire descriptor, since only the 8-bit descriptor status must 74 * be flushed. 75 */ 76 if (!next) 77 debug("Next descriptor not defined!!\n"); 78 79 next->descriptor_control = (next->descriptor_control & 80 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK); 81 82 desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFFFFFF); 83 desc->destination = 84 (unsigned int *)((unsigned int)write_addr & 0x1FFFFFFF); 85 desc->next = (unsigned int *)((unsigned int)next & 0x1FFFFFFF); 86 desc->source_pad = 0x0; 87 desc->destination_pad = 0x0; 88 desc->next_pad = 0x0; 89 desc->bytes_to_transfer = length_or_eop; 90 desc->actual_bytes_transferred = 0; 91 desc->descriptor_status = 0x0; 92 93 /* SGDMA burst not currently supported */ 94 desc->read_burst = 0; 95 desc->write_burst = 0; 96 97 /* 98 * Set the descriptor control block as follows: 99 * - Set "owned by hardware" bit 100 * - Optionally set "generate EOP" bit 101 * - Optionally set the "read from fixed address" bit 102 * - Optionally set the "write to fixed address bit (which serves 103 * serves as a "generate SOP" control bit in memory-to-stream mode). 104 * - Set the 4-bit atlantic channel, if specified 105 * 106 * Note this step is performed after all other descriptor information 107 * has been filled out so that, if the controller already happens to be 108 * pointing at this descriptor, it will not run (via the "owned by 109 * hardware" bit) until all other descriptor has been set up. 110 */ 111 112 desc->descriptor_control = 113 ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) | 114 (generate_eop ? 115 ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0x0) | 116 (read_fixed ? 117 ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0x0) | 118 (write_fixed_or_sop ? 119 ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0x0) | 120 (atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0) 121 ); 122 } 123 124 static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev, 125 volatile struct alt_sgdma_descriptor *desc) 126 { 127 unsigned int status; 128 int counter = 0; 129 130 /* Wait for any pending transfers to complete */ 131 alt_sgdma_print_desc(desc); 132 status = dev->status; 133 134 counter = 0; 135 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { 136 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 137 break; 138 } 139 140 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 141 debug("Timeout waiting sgdma in do sync!\n"); 142 143 /* 144 * Clear any (previous) status register information 145 * that might occlude our error checking later. 146 */ 147 dev->status = 0xFF; 148 149 /* Point the controller at the descriptor */ 150 dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; 151 debug("next desc in sgdma 0x%x\n", 152 (unsigned int)dev->next_descriptor_pointer); 153 154 /* 155 * Set up SGDMA controller to: 156 * - Disable interrupt generation 157 * - Run once a valid descriptor is written to controller 158 * - Stop on an error with any particular descriptor 159 */ 160 dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | 161 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); 162 163 /* Wait for the descriptor (chain) to complete */ 164 status = dev->status; 165 debug("wait for sgdma...."); 166 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) 167 ; 168 debug("done\n"); 169 170 /* Clear Run */ 171 dev->control = (dev->control & (~ALT_SGDMA_CONTROL_RUN_MSK)); 172 173 /* Get & clear status register contents */ 174 status = dev->status; 175 dev->status = 0xFF; 176 177 /* we really should check if the transfer completes properly */ 178 debug("tx sgdma status = 0x%x", status); 179 return 0; 180 } 181 182 static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev, 183 volatile struct alt_sgdma_descriptor *desc) 184 { 185 unsigned int status; 186 int counter = 0; 187 188 /* Wait for any pending transfers to complete */ 189 alt_sgdma_print_desc(desc); 190 status = dev->status; 191 192 counter = 0; 193 while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { 194 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 195 break; 196 } 197 198 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 199 debug("Timeout waiting sgdma in do async!\n"); 200 201 /* 202 * Clear the RUN bit in the control register. This is needed 203 * to restart the SGDMA engine later on. 204 */ 205 dev->control = 0; 206 207 /* 208 * Clear any (previous) status register information 209 * that might occlude our error checking later. 210 */ 211 dev->status = 0xFF; 212 213 /* Point the controller at the descriptor */ 214 dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; 215 216 /* 217 * Set up SGDMA controller to: 218 * - Disable interrupt generation 219 * - Run once a valid descriptor is written to controller 220 * - Stop on an error with any particular descriptor 221 */ 222 dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | 223 ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); 224 225 /* we really should check if the transfer completes properly */ 226 return 0; 227 } 228 229 /* u-boot interface */ 230 static int tse_adjust_link(struct altera_tse_priv *priv) 231 { 232 unsigned int refvar; 233 234 refvar = priv->mac_dev->command_config.image; 235 236 if (!(priv->duplexity)) 237 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; 238 else 239 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; 240 241 switch (priv->speed) { 242 case 1000: 243 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; 244 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; 245 break; 246 case 100: 247 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; 248 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; 249 break; 250 case 10: 251 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; 252 refvar |= ALTERA_TSE_CMD_ENA_10_MSK; 253 break; 254 } 255 priv->mac_dev->command_config.image = refvar; 256 257 return 0; 258 } 259 260 static int tse_eth_send(struct eth_device *dev, 261 volatile void *packet, int length) 262 { 263 struct altera_tse_priv *priv = dev->priv; 264 volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; 265 volatile struct alt_sgdma_descriptor *tx_desc = 266 (volatile struct alt_sgdma_descriptor *)priv->tx_desc; 267 268 volatile struct alt_sgdma_descriptor *tx_desc_cur = 269 (volatile struct alt_sgdma_descriptor *)&tx_desc[0]; 270 271 flush_dcache((unsigned long)packet, length); 272 alt_sgdma_construct_descriptor_burst( 273 (volatile struct alt_sgdma_descriptor *)&tx_desc[0], 274 (volatile struct alt_sgdma_descriptor *)&tx_desc[1], 275 (unsigned int *)packet, /* read addr */ 276 (unsigned int *)0, 277 length, /* length or EOP ,will change for each tx */ 278 0x1, /* gen eop */ 279 0x0, /* read fixed */ 280 0x1, /* write fixed or sop */ 281 0x0, /* read burst */ 282 0x0, /* write burst */ 283 0x0 /* channel */ 284 ); 285 debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet, length); 286 287 /* send the packet */ 288 debug("sending packet\n"); 289 alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur); 290 debug("sent %d bytes\n", tx_desc_cur->actual_bytes_transferred); 291 return tx_desc_cur->actual_bytes_transferred; 292 } 293 294 static int tse_eth_rx(struct eth_device *dev) 295 { 296 int packet_length = 0; 297 struct altera_tse_priv *priv = dev->priv; 298 volatile struct alt_sgdma_descriptor *rx_desc = 299 (volatile struct alt_sgdma_descriptor *)priv->rx_desc; 300 volatile struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0]; 301 302 if (rx_desc_cur->descriptor_status & 303 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { 304 debug("got packet\n"); 305 packet_length = rx_desc->actual_bytes_transferred; 306 NetReceive(NetRxPackets[0], packet_length); 307 308 /* start descriptor again */ 309 flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); 310 alt_sgdma_construct_descriptor_burst( 311 (volatile struct alt_sgdma_descriptor *)&rx_desc[0], 312 (volatile struct alt_sgdma_descriptor *)&rx_desc[1], 313 (unsigned int)0x0, /* read addr */ 314 (unsigned int *)NetRxPackets[0], 315 0x0, /* length or EOP */ 316 0x0, /* gen eop */ 317 0x0, /* read fixed */ 318 0x0, /* write fixed or sop */ 319 0x0, /* read burst */ 320 0x0, /* write burst */ 321 0x0 /* channel */ 322 ); 323 324 /* setup the sgdma */ 325 alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]); 326 327 return packet_length; 328 } 329 330 return -1; 331 } 332 333 static void tse_eth_halt(struct eth_device *dev) 334 { 335 /* don't do anything! */ 336 /* this gets called after each uboot */ 337 /* network command. don't need to reset the thing all of the time */ 338 } 339 340 static void tse_eth_reset(struct eth_device *dev) 341 { 342 /* stop sgdmas, disable tse receive */ 343 struct altera_tse_priv *priv = dev->priv; 344 volatile struct alt_tse_mac *mac_dev = priv->mac_dev; 345 volatile struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; 346 volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; 347 int counter; 348 volatile struct alt_sgdma_descriptor *rx_desc = 349 (volatile struct alt_sgdma_descriptor *)&priv->rx_desc[0]; 350 351 /* clear rx desc & wait for sgdma to complete */ 352 rx_desc->descriptor_control = 0; 353 rx_sgdma->control = 0; 354 counter = 0; 355 while (rx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { 356 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 357 break; 358 } 359 360 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { 361 debug("Timeout waiting for rx sgdma!\n"); 362 rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; 363 rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; 364 } 365 366 counter = 0; 367 tx_sgdma->control = 0; 368 while (tx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { 369 if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) 370 break; 371 } 372 373 if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { 374 debug("Timeout waiting for tx sgdma!\n"); 375 tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; 376 tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; 377 } 378 /* reset the mac */ 379 mac_dev->command_config.bits.transmit_enable = 1; 380 mac_dev->command_config.bits.receive_enable = 1; 381 mac_dev->command_config.bits.software_reset = 1; 382 383 counter = 0; 384 while (mac_dev->command_config.bits.software_reset) { 385 if (counter++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR) 386 break; 387 } 388 389 if (counter >= ALT_TSE_SW_RESET_WATCHDOG_CNTR) 390 debug("TSEMAC SW reset bit never cleared!\n"); 391 } 392 393 static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum) 394 { 395 volatile struct alt_tse_mac *mac_dev; 396 unsigned int *mdio_regs; 397 unsigned int data; 398 u16 value; 399 400 mac_dev = priv->mac_dev; 401 402 /* set mdio address */ 403 mac_dev->mdio_phy1_addr = priv->phyaddr; 404 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; 405 406 /* get the data */ 407 data = mdio_regs[regnum]; 408 409 value = data & 0xffff; 410 411 return value; 412 } 413 414 static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum, 415 unsigned int value) 416 { 417 volatile struct alt_tse_mac *mac_dev; 418 unsigned int *mdio_regs; 419 unsigned int data; 420 421 mac_dev = priv->mac_dev; 422 423 /* set mdio address */ 424 mac_dev->mdio_phy1_addr = priv->phyaddr; 425 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; 426 427 /* get the data */ 428 data = (unsigned int)value; 429 430 mdio_regs[regnum] = data; 431 432 return 0; 433 } 434 435 /* MDIO access to phy */ 436 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) 437 static int altera_tse_miiphy_write(const char *devname, unsigned char addr, 438 unsigned char reg, unsigned short value) 439 { 440 struct eth_device *dev; 441 struct altera_tse_priv *priv; 442 dev = eth_get_dev_by_name(devname); 443 priv = dev->priv; 444 445 tse_mdio_write(priv, (uint) reg, (uint) value); 446 447 return 0; 448 } 449 450 static int altera_tse_miiphy_read(const char *devname, unsigned char addr, 451 unsigned char reg, unsigned short *value) 452 { 453 struct eth_device *dev; 454 struct altera_tse_priv *priv; 455 volatile struct alt_tse_mac *mac_dev; 456 unsigned int *mdio_regs; 457 458 dev = eth_get_dev_by_name(devname); 459 priv = dev->priv; 460 461 mac_dev = priv->mac_dev; 462 mac_dev->mdio_phy1_addr = (int)addr; 463 mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; 464 465 *value = 0xffff & mdio_regs[reg]; 466 467 return 0; 468 469 } 470 #endif 471 472 /* 473 * Also copied from tsec.c 474 */ 475 /* Parse the status register for link, and then do 476 * auto-negotiation 477 */ 478 static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv) 479 { 480 /* 481 * Wait if the link is up, and autonegotiation is in progress 482 * (ie - we're capable and it's not done) 483 */ 484 mii_reg = tse_mdio_read(priv, MIIM_STATUS); 485 486 if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & BMSR_ANEGCAPABLE) 487 && !(mii_reg & BMSR_ANEGCOMPLETE)) { 488 int i = 0; 489 490 puts("Waiting for PHY auto negotiation to complete"); 491 while (!(mii_reg & BMSR_ANEGCOMPLETE)) { 492 /* 493 * Timeout reached ? 494 */ 495 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 496 puts(" TIMEOUT !\n"); 497 priv->link = 0; 498 return 0; 499 } 500 501 if ((i++ % 1000) == 0) 502 putc('.'); 503 udelay(1000); /* 1 ms */ 504 mii_reg = tse_mdio_read(priv, MIIM_STATUS); 505 } 506 puts(" done\n"); 507 priv->link = 1; 508 udelay(500000); /* another 500 ms (results in faster booting) */ 509 } else { 510 if (mii_reg & MIIM_STATUS_LINK) { 511 debug("Link is up\n"); 512 priv->link = 1; 513 } else { 514 debug("Link is down\n"); 515 priv->link = 0; 516 } 517 } 518 519 return 0; 520 } 521 522 /* Parse the 88E1011's status register for speed and duplex 523 * information 524 */ 525 static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv) 526 { 527 uint speed; 528 529 mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); 530 531 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && 532 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 533 int i = 0; 534 535 puts("Waiting for PHY realtime link"); 536 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { 537 /* Timeout reached ? */ 538 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 539 puts(" TIMEOUT !\n"); 540 priv->link = 0; 541 break; 542 } 543 544 if ((i++ == 1000) == 0) { 545 i = 0; 546 puts("."); 547 } 548 udelay(1000); /* 1 ms */ 549 mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); 550 } 551 puts(" done\n"); 552 udelay(500000); /* another 500 ms (results in faster booting) */ 553 } else { 554 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) 555 priv->link = 1; 556 else 557 priv->link = 0; 558 } 559 560 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) 561 priv->duplexity = 1; 562 else 563 priv->duplexity = 0; 564 565 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); 566 567 switch (speed) { 568 case MIIM_88E1011_PHYSTAT_GBIT: 569 priv->speed = 1000; 570 debug("PHY Speed is 1000Mbit\n"); 571 break; 572 case MIIM_88E1011_PHYSTAT_100: 573 debug("PHY Speed is 100Mbit\n"); 574 priv->speed = 100; 575 break; 576 default: 577 debug("PHY Speed is 10Mbit\n"); 578 priv->speed = 10; 579 } 580 581 return 0; 582 } 583 584 static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv) 585 { 586 uint mii_data = tse_mdio_read(priv, mii_reg); 587 mii_data &= 0xfff0; 588 if ((priv->flags >= 1) && (priv->flags <= 4)) 589 mii_data |= 0xb; 590 else if (priv->flags == 5) 591 mii_data |= 0x4; 592 593 return mii_data; 594 } 595 596 static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv) 597 { 598 uint mii_data = tse_mdio_read(priv, mii_reg); 599 mii_data &= ~0x82; 600 if ((priv->flags >= 1) && (priv->flags <= 4)) 601 mii_data |= 0x82; 602 603 return mii_data; 604 } 605 606 /* 607 * Returns which value to write to the control register. 608 * For 10/100, the value is slightly different 609 */ 610 static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv) 611 { 612 return MIIM_CONTROL_INIT; 613 } 614 615 /* 616 * PHY & MDIO code 617 * Need to add SGMII stuff 618 * 619 */ 620 621 static struct phy_info phy_info_M88E1111S = { 622 0x01410cc, 623 "Marvell 88E1111S", 624 4, 625 (struct phy_cmd[]){ /* config */ 626 /* Reset and configure the PHY */ 627 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 628 {MIIM_88E1111_PHY_EXT_SR, 0x848f, 629 &mii_m88e1111s_setmode_sr}, 630 /* Delay RGMII TX and RX */ 631 {MIIM_88E1111_PHY_EXT_CR, 0x0cd2, 632 &mii_m88e1111s_setmode_cr}, 633 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, 634 {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, 635 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, 636 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, 637 {miim_end,} 638 }, 639 (struct phy_cmd[]){ /* startup */ 640 /* Status is read once to clear old link state */ 641 {MIIM_STATUS, miim_read, NULL}, 642 /* Auto-negotiate */ 643 {MIIM_STATUS, miim_read, &mii_parse_sr}, 644 /* Read the status */ 645 {MIIM_88E1011_PHY_STATUS, miim_read, 646 &mii_parse_88E1011_psr}, 647 {miim_end,} 648 }, 649 (struct phy_cmd[]){ /* shutdown */ 650 {miim_end,} 651 }, 652 }; 653 654 /* a generic flavor. */ 655 static struct phy_info phy_info_generic = { 656 0, 657 "Unknown/Generic PHY", 658 32, 659 (struct phy_cmd[]){ /* config */ 660 {MII_BMCR, BMCR_RESET, NULL}, 661 {MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART, NULL}, 662 {miim_end,} 663 }, 664 (struct phy_cmd[]){ /* startup */ 665 {MII_BMSR, miim_read, NULL}, 666 {MII_BMSR, miim_read, &mii_parse_sr}, 667 {miim_end,} 668 }, 669 (struct phy_cmd[]){ /* shutdown */ 670 {miim_end,} 671 } 672 }; 673 674 static struct phy_info *phy_info[] = { 675 &phy_info_M88E1111S, 676 NULL 677 }; 678 679 /* Grab the identifier of the device's PHY, and search through 680 * all of the known PHYs to see if one matches. If so, return 681 * it, if not, return NULL 682 */ 683 static struct phy_info *get_phy_info(struct eth_device *dev) 684 { 685 struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; 686 uint phy_reg, phy_ID; 687 int i; 688 struct phy_info *theInfo = NULL; 689 690 /* Grab the bits from PHYIR1, and put them in the upper half */ 691 phy_reg = tse_mdio_read(priv, MIIM_PHYIR1); 692 phy_ID = (phy_reg & 0xffff) << 16; 693 694 /* Grab the bits from PHYIR2, and put them in the lower half */ 695 phy_reg = tse_mdio_read(priv, MIIM_PHYIR2); 696 phy_ID |= (phy_reg & 0xffff); 697 698 /* loop through all the known PHY types, and find one that */ 699 /* matches the ID we read from the PHY. */ 700 for (i = 0; phy_info[i]; i++) { 701 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { 702 theInfo = phy_info[i]; 703 break; 704 } 705 } 706 707 if (theInfo == NULL) { 708 theInfo = &phy_info_generic; 709 debug("%s: No support for PHY id %x; assuming generic\n", 710 dev->name, phy_ID); 711 } else 712 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); 713 714 return theInfo; 715 } 716 717 /* Execute the given series of commands on the given device's 718 * PHY, running functions as necessary 719 */ 720 static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd) 721 { 722 int i; 723 uint result; 724 725 for (i = 0; cmd->mii_reg != miim_end; i++) { 726 if (cmd->mii_data == miim_read) { 727 result = tse_mdio_read(priv, cmd->mii_reg); 728 729 if (cmd->funct != NULL) 730 (*(cmd->funct)) (result, priv); 731 732 } else { 733 if (cmd->funct != NULL) 734 result = (*(cmd->funct)) (cmd->mii_reg, priv); 735 else 736 result = cmd->mii_data; 737 738 tse_mdio_write(priv, cmd->mii_reg, result); 739 740 } 741 cmd++; 742 } 743 } 744 745 /* Phy init code */ 746 static int init_phy(struct eth_device *dev) 747 { 748 struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; 749 struct phy_info *curphy; 750 751 /* Get the cmd structure corresponding to the attached 752 * PHY */ 753 curphy = get_phy_info(dev); 754 755 if (curphy == NULL) { 756 priv->phyinfo = NULL; 757 debug("%s: No PHY found\n", dev->name); 758 759 return 0; 760 } else 761 debug("%s found\n", curphy->name); 762 priv->phyinfo = curphy; 763 764 phy_run_commands(priv, priv->phyinfo->config); 765 766 return 1; 767 } 768 769 static int tse_set_mac_address(struct eth_device *dev) 770 { 771 struct altera_tse_priv *priv = dev->priv; 772 volatile struct alt_tse_mac *mac_dev = priv->mac_dev; 773 774 debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n", 775 dev->enetaddr[5], dev->enetaddr[4], 776 dev->enetaddr[3], dev->enetaddr[2], 777 dev->enetaddr[1], dev->enetaddr[0]); 778 mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 | 779 (dev->enetaddr[2]) << 16 | 780 (dev->enetaddr[1]) << 8 | (dev->enetaddr[0])); 781 782 mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 | 783 (dev->enetaddr[4])) & 0xFFFF); 784 785 /* Set the MAC address */ 786 mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0; 787 mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1; 788 789 /* Set the MAC address */ 790 mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0; 791 mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1; 792 793 /* Set the MAC address */ 794 mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0; 795 mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1; 796 797 /* Set the MAC address */ 798 mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0; 799 mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1; 800 return 0; 801 } 802 803 static int tse_eth_init(struct eth_device *dev, bd_t * bd) 804 { 805 int dat; 806 struct altera_tse_priv *priv = dev->priv; 807 volatile struct alt_tse_mac *mac_dev = priv->mac_dev; 808 volatile struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; 809 volatile struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 810 volatile struct alt_sgdma_descriptor *rx_desc_cur = 811 (volatile struct alt_sgdma_descriptor *)&rx_desc[0]; 812 813 /* stop controller */ 814 debug("Reseting TSE & SGDMAs\n"); 815 tse_eth_reset(dev); 816 817 /* start the phy */ 818 debug("Configuring PHY\n"); 819 phy_run_commands(priv, priv->phyinfo->startup); 820 821 /* need to create sgdma */ 822 debug("Configuring tx desc\n"); 823 alt_sgdma_construct_descriptor_burst( 824 (volatile struct alt_sgdma_descriptor *)&tx_desc[0], 825 (volatile struct alt_sgdma_descriptor *)&tx_desc[1], 826 (unsigned int *)NULL, /* read addr */ 827 (unsigned int *)0, 828 0, /* length or EOP ,will change for each tx */ 829 0x1, /* gen eop */ 830 0x0, /* read fixed */ 831 0x1, /* write fixed or sop */ 832 0x0, /* read burst */ 833 0x0, /* write burst */ 834 0x0 /* channel */ 835 ); 836 debug("Configuring rx desc\n"); 837 flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); 838 alt_sgdma_construct_descriptor_burst( 839 (volatile struct alt_sgdma_descriptor *)&rx_desc[0], 840 (volatile struct alt_sgdma_descriptor *)&rx_desc[1], 841 (unsigned int)0x0, /* read addr */ 842 (unsigned int *)NetRxPackets[0], 843 0x0, /* length or EOP */ 844 0x0, /* gen eop */ 845 0x0, /* read fixed */ 846 0x0, /* write fixed or sop */ 847 0x0, /* read burst */ 848 0x0, /* write burst */ 849 0x0 /* channel */ 850 ); 851 /* start rx async transfer */ 852 debug("Starting rx sgdma\n"); 853 alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur); 854 855 /* start TSE */ 856 debug("Configuring TSE Mac\n"); 857 /* Initialize MAC registers */ 858 mac_dev->max_frame_length = PKTSIZE_ALIGN; 859 mac_dev->rx_almost_empty_threshold = 8; 860 mac_dev->rx_almost_full_threshold = 8; 861 mac_dev->tx_almost_empty_threshold = 8; 862 mac_dev->tx_almost_full_threshold = 3; 863 mac_dev->tx_sel_empty_threshold = 864 CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16; 865 mac_dev->tx_sel_full_threshold = 0; 866 mac_dev->rx_sel_empty_threshold = 867 CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16; 868 mac_dev->rx_sel_full_threshold = 0; 869 870 /* NO Shift */ 871 mac_dev->rx_cmd_stat.bits.rx_shift16 = 0; 872 mac_dev->tx_cmd_stat.bits.tx_shift16 = 0; 873 874 /* enable MAC */ 875 dat = 0; 876 dat = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; 877 878 mac_dev->command_config.image = dat; 879 880 /* configure the TSE core */ 881 /* -- output clocks, */ 882 /* -- and later config stuff for SGMII */ 883 if (priv->link) { 884 debug("Adjusting TSE to link speed\n"); 885 tse_adjust_link(priv); 886 } 887 888 return priv->link ? 0 : -1; 889 } 890 891 /* TSE init code */ 892 int altera_tse_initialize(u8 dev_num, int mac_base, 893 int sgdma_rx_base, int sgdma_tx_base, 894 u32 sgdma_desc_base, u32 sgdma_desc_size) 895 { 896 struct altera_tse_priv *priv; 897 struct eth_device *dev; 898 struct alt_sgdma_descriptor *rx_desc; 899 struct alt_sgdma_descriptor *tx_desc; 900 unsigned long dma_handle; 901 902 dev = (struct eth_device *)malloc(sizeof *dev); 903 904 if (NULL == dev) 905 return 0; 906 907 memset(dev, 0, sizeof *dev); 908 909 priv = malloc(sizeof(*priv)); 910 911 if (!priv) { 912 free(dev); 913 return 0; 914 } 915 if (sgdma_desc_size) { 916 if (sgdma_desc_size < (sizeof(*tx_desc) * (3 + PKTBUFSRX))) { 917 printf("ALTERA_TSE-%hu: " 918 "descriptor memory is too small\n", dev_num); 919 free(priv); 920 free(dev); 921 return 0; 922 } 923 tx_desc = (struct alt_sgdma_descriptor *)sgdma_desc_base; 924 } else { 925 tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), 926 &dma_handle); 927 } 928 929 rx_desc = tx_desc + 2; 930 debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc); 931 debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc); 932 933 if (!tx_desc) { 934 free(priv); 935 free(dev); 936 return 0; 937 } 938 memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1)); 939 memset(tx_desc, 0, (sizeof *tx_desc) * 2); 940 941 /* initialize tse priv */ 942 priv->mac_dev = (volatile struct alt_tse_mac *)mac_base; 943 priv->sgdma_rx = (volatile struct alt_sgdma_registers *)sgdma_rx_base; 944 priv->sgdma_tx = (volatile struct alt_sgdma_registers *)sgdma_tx_base; 945 priv->phyaddr = CONFIG_SYS_ALTERA_TSE_PHY_ADDR; 946 priv->flags = CONFIG_SYS_ALTERA_TSE_FLAGS; 947 priv->rx_desc = rx_desc; 948 priv->tx_desc = tx_desc; 949 950 /* init eth structure */ 951 dev->priv = priv; 952 dev->init = tse_eth_init; 953 dev->halt = tse_eth_halt; 954 dev->send = tse_eth_send; 955 dev->recv = tse_eth_rx; 956 dev->write_hwaddr = tse_set_mac_address; 957 sprintf(dev->name, "%s-%hu", "ALTERA_TSE", dev_num); 958 959 eth_register(dev); 960 961 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) 962 miiphy_register(dev->name, altera_tse_miiphy_read, 963 altera_tse_miiphy_write); 964 #endif 965 966 init_phy(dev); 967 968 return 1; 969 } 970