1 /* 2 * Altera 10/100/1000 triple speed ethernet mac driver 3 * 4 * Copyright (C) 2008 Altera Corporation. 5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <fdt_support.h> 15 #include <memalign.h> 16 #include <miiphy.h> 17 #include <net.h> 18 #include <asm/cache.h> 19 #include <asm/dma-mapping.h> 20 #include <asm/io.h> 21 #include "altera_tse.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 static inline void alt_sgdma_construct_descriptor( 26 struct alt_sgdma_descriptor *desc, 27 struct alt_sgdma_descriptor *next, 28 void *read_addr, 29 void *write_addr, 30 u16 length_or_eop, 31 int generate_eop, 32 int read_fixed, 33 int write_fixed_or_sop) 34 { 35 u8 val; 36 37 /* 38 * Mark the "next" descriptor as "not" owned by hardware. This prevents 39 * The SGDMA controller from continuing to process the chain. 40 */ 41 next->descriptor_control = next->descriptor_control & 42 ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; 43 44 memset(desc, 0, sizeof(struct alt_sgdma_descriptor)); 45 desc->source = virt_to_phys(read_addr); 46 desc->destination = virt_to_phys(write_addr); 47 desc->next = virt_to_phys(next); 48 desc->bytes_to_transfer = length_or_eop; 49 50 /* 51 * Set the descriptor control block as follows: 52 * - Set "owned by hardware" bit 53 * - Optionally set "generate EOP" bit 54 * - Optionally set the "read from fixed address" bit 55 * - Optionally set the "write to fixed address bit (which serves 56 * serves as a "generate SOP" control bit in memory-to-stream mode). 57 * - Set the 4-bit atlantic channel, if specified 58 * 59 * Note this step is performed after all other descriptor information 60 * has been filled out so that, if the controller already happens to be 61 * pointing at this descriptor, it will not run (via the "owned by 62 * hardware" bit) until all other descriptor has been set up. 63 */ 64 val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK; 65 if (generate_eop) 66 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK; 67 if (read_fixed) 68 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK; 69 if (write_fixed_or_sop) 70 val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK; 71 desc->descriptor_control = val; 72 } 73 74 static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs) 75 { 76 int status; 77 ulong ctime; 78 79 /* Wait for the descriptor (chain) to complete */ 80 ctime = get_timer(0); 81 while (1) { 82 status = readl(®s->status); 83 if (!(status & ALT_SGDMA_STATUS_BUSY_MSK)) 84 break; 85 if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) { 86 status = -ETIMEDOUT; 87 debug("sgdma timeout\n"); 88 break; 89 } 90 } 91 92 /* Clear Run */ 93 writel(0, ®s->control); 94 /* Clear status */ 95 writel(0xff, ®s->status); 96 97 return status; 98 } 99 100 static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs, 101 struct alt_sgdma_descriptor *desc) 102 { 103 u32 val; 104 105 /* Point the controller at the descriptor */ 106 writel(virt_to_phys(desc), ®s->next_descriptor_pointer); 107 108 /* 109 * Set up SGDMA controller to: 110 * - Disable interrupt generation 111 * - Run once a valid descriptor is written to controller 112 * - Stop on an error with any particular descriptor 113 */ 114 val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK; 115 writel(val, ®s->control); 116 117 return 0; 118 } 119 120 static void tse_adjust_link(struct altera_tse_priv *priv, 121 struct phy_device *phydev) 122 { 123 struct alt_tse_mac *mac_dev = priv->mac_dev; 124 u32 refvar; 125 126 if (!phydev->link) { 127 debug("%s: No link.\n", phydev->dev->name); 128 return; 129 } 130 131 refvar = readl(&mac_dev->command_config); 132 133 if (phydev->duplex) 134 refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; 135 else 136 refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; 137 138 switch (phydev->speed) { 139 case 1000: 140 refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; 141 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; 142 break; 143 case 100: 144 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; 145 refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; 146 break; 147 case 10: 148 refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; 149 refvar |= ALTERA_TSE_CMD_ENA_10_MSK; 150 break; 151 } 152 writel(refvar, &mac_dev->command_config); 153 } 154 155 static int altera_tse_send(struct udevice *dev, void *packet, int length) 156 { 157 struct altera_tse_priv *priv = dev_get_priv(dev); 158 struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; 159 unsigned long tx_buf = (unsigned long)packet; 160 161 flush_dcache_range(tx_buf, tx_buf + length); 162 alt_sgdma_construct_descriptor( 163 tx_desc, 164 tx_desc + 1, 165 packet, /* read addr */ 166 NULL, /* write addr */ 167 length, /* length or EOP ,will change for each tx */ 168 1, /* gen eop */ 169 0, /* read fixed */ 170 1 /* write fixed or sop */ 171 ); 172 173 /* send the packet */ 174 alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc); 175 alt_sgdma_wait_transfer(priv->sgdma_tx); 176 debug("sent %d bytes\n", tx_desc->actual_bytes_transferred); 177 178 return tx_desc->actual_bytes_transferred; 179 } 180 181 static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp) 182 { 183 struct altera_tse_priv *priv = dev_get_priv(dev); 184 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 185 int packet_length; 186 187 if (rx_desc->descriptor_status & 188 ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { 189 packet_length = rx_desc->actual_bytes_transferred; 190 debug("recv %d bytes\n", packet_length); 191 *packetp = priv->rx_buf; 192 193 return packet_length; 194 } 195 196 return -EAGAIN; 197 } 198 199 static int altera_tse_free_pkt(struct udevice *dev, uchar *packet, 200 int length) 201 { 202 struct altera_tse_priv *priv = dev_get_priv(dev); 203 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 204 unsigned long rx_buf = (unsigned long)priv->rx_buf; 205 206 alt_sgdma_wait_transfer(priv->sgdma_rx); 207 invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN); 208 alt_sgdma_construct_descriptor( 209 rx_desc, 210 rx_desc + 1, 211 NULL, /* read addr */ 212 priv->rx_buf, /* write addr */ 213 0, /* length or EOP */ 214 0, /* gen eop */ 215 0, /* read fixed */ 216 0 /* write fixed or sop */ 217 ); 218 219 /* setup the sgdma */ 220 alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc); 221 debug("recv setup\n"); 222 223 return 0; 224 } 225 226 static void altera_tse_stop_mac(struct altera_tse_priv *priv) 227 { 228 struct alt_tse_mac *mac_dev = priv->mac_dev; 229 u32 status; 230 ulong ctime; 231 232 /* reset the mac */ 233 writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config); 234 ctime = get_timer(0); 235 while (1) { 236 status = readl(&mac_dev->command_config); 237 if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK)) 238 break; 239 if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) { 240 debug("Reset mac timeout\n"); 241 break; 242 } 243 } 244 } 245 246 static void altera_tse_stop(struct udevice *dev) 247 { 248 struct altera_tse_priv *priv = dev_get_priv(dev); 249 struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; 250 struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; 251 struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; 252 int ret; 253 254 /* clear rx desc & wait for sgdma to complete */ 255 rx_desc->descriptor_control = 0; 256 writel(0, &rx_sgdma->control); 257 ret = alt_sgdma_wait_transfer(rx_sgdma); 258 if (ret == -ETIMEDOUT) 259 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, 260 &rx_sgdma->control); 261 262 writel(0, &tx_sgdma->control); 263 ret = alt_sgdma_wait_transfer(tx_sgdma); 264 if (ret == -ETIMEDOUT) 265 writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, 266 &tx_sgdma->control); 267 268 altera_tse_stop_mac(priv); 269 } 270 271 static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 272 { 273 struct altera_tse_priv *priv = bus->priv; 274 struct alt_tse_mac *mac_dev = priv->mac_dev; 275 u32 value; 276 277 /* set mdio address */ 278 writel(addr, &mac_dev->mdio_phy1_addr); 279 /* get the data */ 280 value = readl(&mac_dev->mdio_phy1[reg]); 281 282 return value & 0xffff; 283 } 284 285 static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 286 u16 val) 287 { 288 struct altera_tse_priv *priv = bus->priv; 289 struct alt_tse_mac *mac_dev = priv->mac_dev; 290 291 /* set mdio address */ 292 writel(addr, &mac_dev->mdio_phy1_addr); 293 /* set the data */ 294 writel(val, &mac_dev->mdio_phy1[reg]); 295 296 return 0; 297 } 298 299 static int tse_mdio_init(const char *name, struct altera_tse_priv *priv) 300 { 301 struct mii_dev *bus = mdio_alloc(); 302 303 if (!bus) { 304 printf("Failed to allocate MDIO bus\n"); 305 return -ENOMEM; 306 } 307 308 bus->read = tse_mdio_read; 309 bus->write = tse_mdio_write; 310 snprintf(bus->name, sizeof(bus->name), name); 311 312 bus->priv = (void *)priv; 313 314 return mdio_register(bus); 315 } 316 317 static int tse_phy_init(struct altera_tse_priv *priv, void *dev) 318 { 319 struct phy_device *phydev; 320 unsigned int mask = 0xffffffff; 321 322 if (priv->phyaddr) 323 mask = 1 << priv->phyaddr; 324 325 phydev = phy_find_by_mask(priv->bus, mask, priv->interface); 326 if (!phydev) 327 return -ENODEV; 328 329 phy_connect_dev(phydev, dev); 330 331 phydev->supported &= PHY_GBIT_FEATURES; 332 phydev->advertising = phydev->supported; 333 334 priv->phydev = phydev; 335 phy_config(phydev); 336 337 return 0; 338 } 339 340 static int altera_tse_write_hwaddr(struct udevice *dev) 341 { 342 struct altera_tse_priv *priv = dev_get_priv(dev); 343 struct alt_tse_mac *mac_dev = priv->mac_dev; 344 struct eth_pdata *pdata = dev_get_platdata(dev); 345 u8 *hwaddr = pdata->enetaddr; 346 u32 mac_lo, mac_hi; 347 348 mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) | 349 (hwaddr[1] << 8) | hwaddr[0]; 350 mac_hi = (hwaddr[5] << 8) | hwaddr[4]; 351 debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo); 352 353 writel(mac_lo, &mac_dev->mac_addr_0); 354 writel(mac_hi, &mac_dev->mac_addr_1); 355 writel(mac_lo, &mac_dev->supp_mac_addr_0_0); 356 writel(mac_hi, &mac_dev->supp_mac_addr_0_1); 357 writel(mac_lo, &mac_dev->supp_mac_addr_1_0); 358 writel(mac_hi, &mac_dev->supp_mac_addr_1_1); 359 writel(mac_lo, &mac_dev->supp_mac_addr_2_0); 360 writel(mac_hi, &mac_dev->supp_mac_addr_2_1); 361 writel(mac_lo, &mac_dev->supp_mac_addr_3_0); 362 writel(mac_hi, &mac_dev->supp_mac_addr_3_1); 363 364 return 0; 365 } 366 367 static int altera_tse_start(struct udevice *dev) 368 { 369 struct altera_tse_priv *priv = dev_get_priv(dev); 370 struct alt_tse_mac *mac_dev = priv->mac_dev; 371 u32 val; 372 int ret; 373 374 /* need to create sgdma */ 375 debug("Configuring rx desc\n"); 376 altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN); 377 /* start TSE */ 378 debug("Configuring TSE Mac\n"); 379 /* Initialize MAC registers */ 380 writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length); 381 writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold); 382 writel(0, &mac_dev->rx_sel_full_threshold); 383 writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold); 384 writel(0, &mac_dev->tx_sel_full_threshold); 385 writel(8, &mac_dev->rx_almost_empty_threshold); 386 writel(8, &mac_dev->rx_almost_full_threshold); 387 writel(8, &mac_dev->tx_almost_empty_threshold); 388 writel(3, &mac_dev->tx_almost_full_threshold); 389 390 /* NO Shift */ 391 writel(0, &mac_dev->rx_cmd_stat); 392 writel(0, &mac_dev->tx_cmd_stat); 393 394 /* enable MAC */ 395 val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; 396 writel(val, &mac_dev->command_config); 397 398 /* Start up the PHY */ 399 ret = phy_startup(priv->phydev); 400 if (ret) { 401 debug("Could not initialize PHY %s\n", 402 priv->phydev->dev->name); 403 return ret; 404 } 405 406 tse_adjust_link(priv, priv->phydev); 407 408 if (!priv->phydev->link) 409 return -EIO; 410 411 return 0; 412 } 413 414 static int altera_tse_probe(struct udevice *dev) 415 { 416 struct eth_pdata *pdata = dev_get_platdata(dev); 417 struct altera_tse_priv *priv = dev_get_priv(dev); 418 void *blob = (void *)gd->fdt_blob; 419 int node = dev->of_offset; 420 const char *list, *end; 421 const fdt32_t *cell; 422 void *base, *desc_mem = NULL; 423 unsigned long addr, size; 424 int parent, addrc, sizec; 425 int len, idx; 426 int ret; 427 428 /* 429 * decode regs. there are multiple reg tuples, and they need to 430 * match with reg-names. 431 */ 432 parent = fdt_parent_offset(blob, node); 433 of_bus_default_count_cells(blob, parent, &addrc, &sizec); 434 list = fdt_getprop(blob, node, "reg-names", &len); 435 if (!list) 436 return -ENOENT; 437 end = list + len; 438 cell = fdt_getprop(blob, node, "reg", &len); 439 if (!cell) 440 return -ENOENT; 441 idx = 0; 442 while (list < end) { 443 addr = fdt_translate_address((void *)blob, 444 node, cell + idx); 445 size = fdt_addr_to_cpu(cell[idx + addrc]); 446 base = ioremap(addr, size); 447 len = strlen(list); 448 if (strcmp(list, "control_port") == 0) 449 priv->mac_dev = base; 450 else if (strcmp(list, "rx_csr") == 0) 451 priv->sgdma_rx = base; 452 else if (strcmp(list, "tx_csr") == 0) 453 priv->sgdma_tx = base; 454 else if (strcmp(list, "s1") == 0) 455 desc_mem = base; 456 idx += addrc + sizec; 457 list += (len + 1); 458 } 459 /* decode fifo depth */ 460 priv->rx_fifo_depth = fdtdec_get_int(blob, node, 461 "rx-fifo-depth", 0); 462 priv->tx_fifo_depth = fdtdec_get_int(blob, node, 463 "tx-fifo-depth", 0); 464 /* decode phy */ 465 addr = fdtdec_get_int(blob, node, 466 "phy-handle", 0); 467 addr = fdt_node_offset_by_phandle(blob, addr); 468 priv->phyaddr = fdtdec_get_int(blob, addr, 469 "reg", 0); 470 /* init desc */ 471 len = sizeof(struct alt_sgdma_descriptor) * 4; 472 if (!desc_mem) { 473 desc_mem = dma_alloc_coherent(len, &addr); 474 if (!desc_mem) 475 return -ENOMEM; 476 } 477 memset(desc_mem, 0, len); 478 priv->tx_desc = desc_mem; 479 priv->rx_desc = priv->tx_desc + 2; 480 /* allocate recv packet buffer */ 481 priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN); 482 if (!priv->rx_buf) 483 return -ENOMEM; 484 485 /* stop controller */ 486 debug("Reset TSE & SGDMAs\n"); 487 altera_tse_stop(dev); 488 489 /* start the phy */ 490 priv->interface = pdata->phy_interface; 491 tse_mdio_init(dev->name, priv); 492 priv->bus = miiphy_get_dev_by_name(dev->name); 493 494 ret = tse_phy_init(priv, dev); 495 496 return ret; 497 } 498 499 static int altera_tse_ofdata_to_platdata(struct udevice *dev) 500 { 501 struct eth_pdata *pdata = dev_get_platdata(dev); 502 const char *phy_mode; 503 504 pdata->phy_interface = -1; 505 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 506 if (phy_mode) 507 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 508 if (pdata->phy_interface == -1) { 509 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 510 return -EINVAL; 511 } 512 513 return 0; 514 } 515 516 static const struct eth_ops altera_tse_ops = { 517 .start = altera_tse_start, 518 .send = altera_tse_send, 519 .recv = altera_tse_recv, 520 .free_pkt = altera_tse_free_pkt, 521 .stop = altera_tse_stop, 522 .write_hwaddr = altera_tse_write_hwaddr, 523 }; 524 525 static const struct udevice_id altera_tse_ids[] = { 526 { .compatible = "altr,tse-1.0", }, 527 { } 528 }; 529 530 U_BOOT_DRIVER(altera_tse) = { 531 .name = "altera_tse", 532 .id = UCLASS_ETH, 533 .of_match = altera_tse_ids, 534 .ops = &altera_tse_ops, 535 .ofdata_to_platdata = altera_tse_ofdata_to_platdata, 536 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 537 .priv_auto_alloc_size = sizeof(struct altera_tse_priv), 538 .probe = altera_tse_probe, 539 }; 540