1c960b13eSThomas Chou /*
2c960b13eSThomas Chou * Altera 10/100/1000 triple speed ethernet mac driver
3c960b13eSThomas Chou *
4c960b13eSThomas Chou * Copyright (C) 2008 Altera Corporation.
5c960b13eSThomas Chou * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
6c960b13eSThomas Chou *
7c960b13eSThomas Chou * This program is free software; you can redistribute it and/or modify
8c960b13eSThomas Chou * it under the terms of the GNU General Public License version 2 as
9c960b13eSThomas Chou * published by the Free Software Foundation.
10c960b13eSThomas Chou */
11c960b13eSThomas Chou #include <common.h>
1296fa1e43SThomas Chou #include <dm.h>
1396fa1e43SThomas Chou #include <errno.h>
1496fa1e43SThomas Chou #include <fdt_support.h>
1596fa1e43SThomas Chou #include <memalign.h>
1696fa1e43SThomas Chou #include <miiphy.h>
17c960b13eSThomas Chou #include <net.h>
18c960b13eSThomas Chou #include <asm/cache.h>
19c960b13eSThomas Chou #include <asm/dma-mapping.h>
2096fa1e43SThomas Chou #include <asm/io.h>
21c960b13eSThomas Chou #include "altera_tse.h"
22c960b13eSThomas Chou
2396fa1e43SThomas Chou DECLARE_GLOBAL_DATA_PTR;
24c960b13eSThomas Chou
alt_sgdma_construct_descriptor(struct alt_sgdma_descriptor * desc,struct alt_sgdma_descriptor * next,void * read_addr,void * write_addr,u16 length_or_eop,int generate_eop,int read_fixed,int write_fixed_or_sop)2596fa1e43SThomas Chou static inline void alt_sgdma_construct_descriptor(
2696fa1e43SThomas Chou struct alt_sgdma_descriptor *desc,
2796fa1e43SThomas Chou struct alt_sgdma_descriptor *next,
2896fa1e43SThomas Chou void *read_addr,
2996fa1e43SThomas Chou void *write_addr,
302cd0a52eSThomas Chou u16 length_or_eop,
31c960b13eSThomas Chou int generate_eop,
32c960b13eSThomas Chou int read_fixed,
3396fa1e43SThomas Chou int write_fixed_or_sop)
34c960b13eSThomas Chou {
352cd0a52eSThomas Chou u8 val;
3696fa1e43SThomas Chou
37c960b13eSThomas Chou /*
38c960b13eSThomas Chou * Mark the "next" descriptor as "not" owned by hardware. This prevents
3996fa1e43SThomas Chou * The SGDMA controller from continuing to process the chain.
40c960b13eSThomas Chou */
4196fa1e43SThomas Chou next->descriptor_control = next->descriptor_control &
4296fa1e43SThomas Chou ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
43c960b13eSThomas Chou
4496fa1e43SThomas Chou memset(desc, 0, sizeof(struct alt_sgdma_descriptor));
4596fa1e43SThomas Chou desc->source = virt_to_phys(read_addr);
4696fa1e43SThomas Chou desc->destination = virt_to_phys(write_addr);
4796fa1e43SThomas Chou desc->next = virt_to_phys(next);
48c960b13eSThomas Chou desc->bytes_to_transfer = length_or_eop;
49c960b13eSThomas Chou
50c960b13eSThomas Chou /*
51c960b13eSThomas Chou * Set the descriptor control block as follows:
52c960b13eSThomas Chou * - Set "owned by hardware" bit
53c960b13eSThomas Chou * - Optionally set "generate EOP" bit
54c960b13eSThomas Chou * - Optionally set the "read from fixed address" bit
55c960b13eSThomas Chou * - Optionally set the "write to fixed address bit (which serves
56c960b13eSThomas Chou * serves as a "generate SOP" control bit in memory-to-stream mode).
57c960b13eSThomas Chou * - Set the 4-bit atlantic channel, if specified
58c960b13eSThomas Chou *
59c960b13eSThomas Chou * Note this step is performed after all other descriptor information
60c960b13eSThomas Chou * has been filled out so that, if the controller already happens to be
61c960b13eSThomas Chou * pointing at this descriptor, it will not run (via the "owned by
62c960b13eSThomas Chou * hardware" bit) until all other descriptor has been set up.
63c960b13eSThomas Chou */
6496fa1e43SThomas Chou val = ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK;
6596fa1e43SThomas Chou if (generate_eop)
6696fa1e43SThomas Chou val |= ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK;
6796fa1e43SThomas Chou if (read_fixed)
6896fa1e43SThomas Chou val |= ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK;
6996fa1e43SThomas Chou if (write_fixed_or_sop)
7096fa1e43SThomas Chou val |= ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK;
7196fa1e43SThomas Chou desc->descriptor_control = val;
72c960b13eSThomas Chou }
73c960b13eSThomas Chou
alt_sgdma_wait_transfer(struct alt_sgdma_registers * regs)7496fa1e43SThomas Chou static int alt_sgdma_wait_transfer(struct alt_sgdma_registers *regs)
75c960b13eSThomas Chou {
7696fa1e43SThomas Chou int status;
7796fa1e43SThomas Chou ulong ctime;
78c960b13eSThomas Chou
79c960b13eSThomas Chou /* Wait for the descriptor (chain) to complete */
8096fa1e43SThomas Chou ctime = get_timer(0);
8196fa1e43SThomas Chou while (1) {
8296fa1e43SThomas Chou status = readl(®s->status);
8396fa1e43SThomas Chou if (!(status & ALT_SGDMA_STATUS_BUSY_MSK))
8496fa1e43SThomas Chou break;
8596fa1e43SThomas Chou if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
8696fa1e43SThomas Chou status = -ETIMEDOUT;
8796fa1e43SThomas Chou debug("sgdma timeout\n");
88c960b13eSThomas Chou break;
89c960b13eSThomas Chou }
9096fa1e43SThomas Chou }
91c960b13eSThomas Chou
9296fa1e43SThomas Chou /* Clear Run */
9396fa1e43SThomas Chou writel(0, ®s->control);
9496fa1e43SThomas Chou /* Clear status */
9596fa1e43SThomas Chou writel(0xff, ®s->status);
96c960b13eSThomas Chou
9796fa1e43SThomas Chou return status;
9896fa1e43SThomas Chou }
99337aff53SJoachim Foerster
alt_sgdma_start_transfer(struct alt_sgdma_registers * regs,struct alt_sgdma_descriptor * desc)10096fa1e43SThomas Chou static int alt_sgdma_start_transfer(struct alt_sgdma_registers *regs,
10196fa1e43SThomas Chou struct alt_sgdma_descriptor *desc)
10296fa1e43SThomas Chou {
1032cd0a52eSThomas Chou u32 val;
104c960b13eSThomas Chou
105c960b13eSThomas Chou /* Point the controller at the descriptor */
10696fa1e43SThomas Chou writel(virt_to_phys(desc), ®s->next_descriptor_pointer);
107c960b13eSThomas Chou
108c960b13eSThomas Chou /*
109c960b13eSThomas Chou * Set up SGDMA controller to:
110c960b13eSThomas Chou * - Disable interrupt generation
111c960b13eSThomas Chou * - Run once a valid descriptor is written to controller
112c960b13eSThomas Chou * - Stop on an error with any particular descriptor
113c960b13eSThomas Chou */
11496fa1e43SThomas Chou val = ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK;
11596fa1e43SThomas Chou writel(val, ®s->control);
116c960b13eSThomas Chou
117c960b13eSThomas Chou return 0;
118c960b13eSThomas Chou }
119c960b13eSThomas Chou
tse_adjust_link(struct altera_tse_priv * priv,struct phy_device * phydev)12096fa1e43SThomas Chou static void tse_adjust_link(struct altera_tse_priv *priv,
12196fa1e43SThomas Chou struct phy_device *phydev)
122c960b13eSThomas Chou {
12396fa1e43SThomas Chou struct alt_tse_mac *mac_dev = priv->mac_dev;
1242cd0a52eSThomas Chou u32 refvar;
125c960b13eSThomas Chou
12696fa1e43SThomas Chou if (!phydev->link) {
12796fa1e43SThomas Chou debug("%s: No link.\n", phydev->dev->name);
12896fa1e43SThomas Chou return;
12996fa1e43SThomas Chou }
130c960b13eSThomas Chou
13196fa1e43SThomas Chou refvar = readl(&mac_dev->command_config);
13296fa1e43SThomas Chou
13396fa1e43SThomas Chou if (phydev->duplex)
134c960b13eSThomas Chou refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
135c960b13eSThomas Chou else
136c960b13eSThomas Chou refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
137c960b13eSThomas Chou
13896fa1e43SThomas Chou switch (phydev->speed) {
139c960b13eSThomas Chou case 1000:
140c960b13eSThomas Chou refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
141c960b13eSThomas Chou refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
142c960b13eSThomas Chou break;
143c960b13eSThomas Chou case 100:
144c960b13eSThomas Chou refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
145c960b13eSThomas Chou refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
146c960b13eSThomas Chou break;
147c960b13eSThomas Chou case 10:
148c960b13eSThomas Chou refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
149c960b13eSThomas Chou refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
150c960b13eSThomas Chou break;
151c960b13eSThomas Chou }
15296fa1e43SThomas Chou writel(refvar, &mac_dev->command_config);
153c960b13eSThomas Chou }
154c960b13eSThomas Chou
altera_tse_send_sgdma(struct udevice * dev,void * packet,int length)15538fa4acaSThomas Chou static int altera_tse_send_sgdma(struct udevice *dev, void *packet, int length)
156c960b13eSThomas Chou {
15796fa1e43SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
15896fa1e43SThomas Chou struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
159c960b13eSThomas Chou
16096fa1e43SThomas Chou alt_sgdma_construct_descriptor(
16196fa1e43SThomas Chou tx_desc,
16296fa1e43SThomas Chou tx_desc + 1,
16396fa1e43SThomas Chou packet, /* read addr */
16496fa1e43SThomas Chou NULL, /* write addr */
165c960b13eSThomas Chou length, /* length or EOP ,will change for each tx */
16696fa1e43SThomas Chou 1, /* gen eop */
16796fa1e43SThomas Chou 0, /* read fixed */
16896fa1e43SThomas Chou 1 /* write fixed or sop */
169c960b13eSThomas Chou );
170c960b13eSThomas Chou
171c960b13eSThomas Chou /* send the packet */
17296fa1e43SThomas Chou alt_sgdma_start_transfer(priv->sgdma_tx, tx_desc);
17396fa1e43SThomas Chou alt_sgdma_wait_transfer(priv->sgdma_tx);
17496fa1e43SThomas Chou debug("sent %d bytes\n", tx_desc->actual_bytes_transferred);
17596fa1e43SThomas Chou
17696fa1e43SThomas Chou return tx_desc->actual_bytes_transferred;
177c960b13eSThomas Chou }
178c960b13eSThomas Chou
altera_tse_recv_sgdma(struct udevice * dev,int flags,uchar ** packetp)17938fa4acaSThomas Chou static int altera_tse_recv_sgdma(struct udevice *dev, int flags,
18038fa4acaSThomas Chou uchar **packetp)
181c960b13eSThomas Chou {
18296fa1e43SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
18396fa1e43SThomas Chou struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
18496fa1e43SThomas Chou int packet_length;
185c960b13eSThomas Chou
18696fa1e43SThomas Chou if (rx_desc->descriptor_status &
187c960b13eSThomas Chou ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
188577662f0SThomas Chou alt_sgdma_wait_transfer(priv->sgdma_rx);
189c960b13eSThomas Chou packet_length = rx_desc->actual_bytes_transferred;
19096fa1e43SThomas Chou debug("recv %d bytes\n", packet_length);
19196fa1e43SThomas Chou *packetp = priv->rx_buf;
19270d52f9aSJoachim Foerster
19370d52f9aSJoachim Foerster return packet_length;
194c960b13eSThomas Chou }
195c960b13eSThomas Chou
19696fa1e43SThomas Chou return -EAGAIN;
197c960b13eSThomas Chou }
198c960b13eSThomas Chou
altera_tse_free_pkt_sgdma(struct udevice * dev,uchar * packet,int length)19938fa4acaSThomas Chou static int altera_tse_free_pkt_sgdma(struct udevice *dev, uchar *packet,
20096fa1e43SThomas Chou int length)
201c960b13eSThomas Chou {
20296fa1e43SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
20396fa1e43SThomas Chou struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
20496fa1e43SThomas Chou
20596fa1e43SThomas Chou alt_sgdma_construct_descriptor(
20696fa1e43SThomas Chou rx_desc,
20796fa1e43SThomas Chou rx_desc + 1,
20896fa1e43SThomas Chou NULL, /* read addr */
20996fa1e43SThomas Chou priv->rx_buf, /* write addr */
21096fa1e43SThomas Chou 0, /* length or EOP */
21196fa1e43SThomas Chou 0, /* gen eop */
21296fa1e43SThomas Chou 0, /* read fixed */
21396fa1e43SThomas Chou 0 /* write fixed or sop */
21496fa1e43SThomas Chou );
21596fa1e43SThomas Chou
21696fa1e43SThomas Chou /* setup the sgdma */
21796fa1e43SThomas Chou alt_sgdma_start_transfer(priv->sgdma_rx, rx_desc);
21896fa1e43SThomas Chou debug("recv setup\n");
21996fa1e43SThomas Chou
22096fa1e43SThomas Chou return 0;
221c960b13eSThomas Chou }
222c960b13eSThomas Chou
altera_tse_stop_mac(struct altera_tse_priv * priv)223acd71c32SThomas Chou static void altera_tse_stop_mac(struct altera_tse_priv *priv)
224acd71c32SThomas Chou {
225acd71c32SThomas Chou struct alt_tse_mac *mac_dev = priv->mac_dev;
226acd71c32SThomas Chou u32 status;
227acd71c32SThomas Chou ulong ctime;
228acd71c32SThomas Chou
229acd71c32SThomas Chou /* reset the mac */
230acd71c32SThomas Chou writel(ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
231acd71c32SThomas Chou ctime = get_timer(0);
232acd71c32SThomas Chou while (1) {
233acd71c32SThomas Chou status = readl(&mac_dev->command_config);
234acd71c32SThomas Chou if (!(status & ALTERA_TSE_CMD_SW_RESET_MSK))
235acd71c32SThomas Chou break;
236acd71c32SThomas Chou if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
237acd71c32SThomas Chou debug("Reset mac timeout\n");
238acd71c32SThomas Chou break;
239acd71c32SThomas Chou }
240acd71c32SThomas Chou }
241acd71c32SThomas Chou }
242acd71c32SThomas Chou
altera_tse_stop_sgdma(struct udevice * dev)24338fa4acaSThomas Chou static void altera_tse_stop_sgdma(struct udevice *dev)
244c960b13eSThomas Chou {
24596fa1e43SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
24696fa1e43SThomas Chou struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
24796fa1e43SThomas Chou struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
24896fa1e43SThomas Chou struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
24996fa1e43SThomas Chou int ret;
250c960b13eSThomas Chou
251c960b13eSThomas Chou /* clear rx desc & wait for sgdma to complete */
252c960b13eSThomas Chou rx_desc->descriptor_control = 0;
25396fa1e43SThomas Chou writel(0, &rx_sgdma->control);
25496fa1e43SThomas Chou ret = alt_sgdma_wait_transfer(rx_sgdma);
25596fa1e43SThomas Chou if (ret == -ETIMEDOUT)
25696fa1e43SThomas Chou writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
25796fa1e43SThomas Chou &rx_sgdma->control);
258c960b13eSThomas Chou
25996fa1e43SThomas Chou writel(0, &tx_sgdma->control);
26096fa1e43SThomas Chou ret = alt_sgdma_wait_transfer(tx_sgdma);
26196fa1e43SThomas Chou if (ret == -ETIMEDOUT)
26296fa1e43SThomas Chou writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK,
26396fa1e43SThomas Chou &tx_sgdma->control);
264c960b13eSThomas Chou }
265c960b13eSThomas Chou
msgdma_reset(struct msgdma_csr * csr)266e3e87260SThomas Chou static void msgdma_reset(struct msgdma_csr *csr)
267e3e87260SThomas Chou {
268e3e87260SThomas Chou u32 status;
269e3e87260SThomas Chou ulong ctime;
270e3e87260SThomas Chou
271e3e87260SThomas Chou /* Reset mSGDMA */
272e3e87260SThomas Chou writel(MSGDMA_CSR_STAT_MASK, &csr->status);
273e3e87260SThomas Chou writel(MSGDMA_CSR_CTL_RESET, &csr->control);
274e3e87260SThomas Chou ctime = get_timer(0);
275e3e87260SThomas Chou while (1) {
276e3e87260SThomas Chou status = readl(&csr->status);
277e3e87260SThomas Chou if (!(status & MSGDMA_CSR_STAT_RESETTING))
278e3e87260SThomas Chou break;
279e3e87260SThomas Chou if (get_timer(ctime) > ALT_TSE_SW_RESET_TIMEOUT) {
280e3e87260SThomas Chou debug("Reset msgdma timeout\n");
281e3e87260SThomas Chou break;
282e3e87260SThomas Chou }
283e3e87260SThomas Chou }
284e3e87260SThomas Chou /* Clear status */
285e3e87260SThomas Chou writel(MSGDMA_CSR_STAT_MASK, &csr->status);
286e3e87260SThomas Chou }
287e3e87260SThomas Chou
msgdma_wait(struct msgdma_csr * csr)288e3e87260SThomas Chou static u32 msgdma_wait(struct msgdma_csr *csr)
289e3e87260SThomas Chou {
290e3e87260SThomas Chou u32 status;
291e3e87260SThomas Chou ulong ctime;
292e3e87260SThomas Chou
293e3e87260SThomas Chou /* Wait for the descriptor to complete */
294e3e87260SThomas Chou ctime = get_timer(0);
295e3e87260SThomas Chou while (1) {
296e3e87260SThomas Chou status = readl(&csr->status);
297e3e87260SThomas Chou if (!(status & MSGDMA_CSR_STAT_BUSY))
298e3e87260SThomas Chou break;
299e3e87260SThomas Chou if (get_timer(ctime) > ALT_TSE_SGDMA_BUSY_TIMEOUT) {
300e3e87260SThomas Chou debug("sgdma timeout\n");
301e3e87260SThomas Chou break;
302e3e87260SThomas Chou }
303e3e87260SThomas Chou }
304e3e87260SThomas Chou /* Clear status */
305e3e87260SThomas Chou writel(MSGDMA_CSR_STAT_MASK, &csr->status);
306e3e87260SThomas Chou
307e3e87260SThomas Chou return status;
308e3e87260SThomas Chou }
309e3e87260SThomas Chou
altera_tse_send_msgdma(struct udevice * dev,void * packet,int length)310e3e87260SThomas Chou static int altera_tse_send_msgdma(struct udevice *dev, void *packet,
311e3e87260SThomas Chou int length)
312e3e87260SThomas Chou {
313e3e87260SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
314e3e87260SThomas Chou struct msgdma_extended_desc *desc = priv->tx_desc;
315e3e87260SThomas Chou u32 tx_buf = virt_to_phys(packet);
316e3e87260SThomas Chou u32 status;
317e3e87260SThomas Chou
318e3e87260SThomas Chou writel(tx_buf, &desc->read_addr_lo);
319e3e87260SThomas Chou writel(0, &desc->read_addr_hi);
320e3e87260SThomas Chou writel(0, &desc->write_addr_lo);
321e3e87260SThomas Chou writel(0, &desc->write_addr_hi);
322e3e87260SThomas Chou writel(length, &desc->len);
323e3e87260SThomas Chou writel(0, &desc->burst_seq_num);
324e3e87260SThomas Chou writel(MSGDMA_DESC_TX_STRIDE, &desc->stride);
325e3e87260SThomas Chou writel(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control);
326e3e87260SThomas Chou status = msgdma_wait(priv->sgdma_tx);
327e3e87260SThomas Chou debug("sent %d bytes, status %08x\n", length, status);
328e3e87260SThomas Chou
329e3e87260SThomas Chou return 0;
330e3e87260SThomas Chou }
331e3e87260SThomas Chou
altera_tse_recv_msgdma(struct udevice * dev,int flags,uchar ** packetp)332e3e87260SThomas Chou static int altera_tse_recv_msgdma(struct udevice *dev, int flags,
333e3e87260SThomas Chou uchar **packetp)
334e3e87260SThomas Chou {
335e3e87260SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
336e3e87260SThomas Chou struct msgdma_csr *csr = priv->sgdma_rx;
337e3e87260SThomas Chou struct msgdma_response *resp = priv->rx_resp;
338e3e87260SThomas Chou u32 level, length, status;
339e3e87260SThomas Chou
340e3e87260SThomas Chou level = readl(&csr->resp_fill_level);
341e3e87260SThomas Chou if (level & 0xffff) {
342e3e87260SThomas Chou length = readl(&resp->bytes_transferred);
343e3e87260SThomas Chou status = readl(&resp->status);
344e3e87260SThomas Chou debug("recv %d bytes, status %08x\n", length, status);
345e3e87260SThomas Chou *packetp = priv->rx_buf;
346e3e87260SThomas Chou
347e3e87260SThomas Chou return length;
348e3e87260SThomas Chou }
349e3e87260SThomas Chou
350e3e87260SThomas Chou return -EAGAIN;
351e3e87260SThomas Chou }
352e3e87260SThomas Chou
altera_tse_free_pkt_msgdma(struct udevice * dev,uchar * packet,int length)353e3e87260SThomas Chou static int altera_tse_free_pkt_msgdma(struct udevice *dev, uchar *packet,
354e3e87260SThomas Chou int length)
355e3e87260SThomas Chou {
356e3e87260SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
357e3e87260SThomas Chou struct msgdma_extended_desc *desc = priv->rx_desc;
358e3e87260SThomas Chou u32 rx_buf = virt_to_phys(priv->rx_buf);
359e3e87260SThomas Chou
360e3e87260SThomas Chou writel(0, &desc->read_addr_lo);
361e3e87260SThomas Chou writel(0, &desc->read_addr_hi);
362e3e87260SThomas Chou writel(rx_buf, &desc->write_addr_lo);
363e3e87260SThomas Chou writel(0, &desc->write_addr_hi);
364e3e87260SThomas Chou writel(PKTSIZE_ALIGN, &desc->len);
365e3e87260SThomas Chou writel(0, &desc->burst_seq_num);
366e3e87260SThomas Chou writel(MSGDMA_DESC_RX_STRIDE, &desc->stride);
367e3e87260SThomas Chou writel(MSGDMA_DESC_CTL_RX_SINGLE, &desc->control);
368e3e87260SThomas Chou debug("recv setup\n");
369e3e87260SThomas Chou
370e3e87260SThomas Chou return 0;
371e3e87260SThomas Chou }
372e3e87260SThomas Chou
altera_tse_stop_msgdma(struct udevice * dev)373e3e87260SThomas Chou static void altera_tse_stop_msgdma(struct udevice *dev)
374e3e87260SThomas Chou {
375e3e87260SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
376e3e87260SThomas Chou
377e3e87260SThomas Chou msgdma_reset(priv->sgdma_rx);
378e3e87260SThomas Chou msgdma_reset(priv->sgdma_tx);
379e3e87260SThomas Chou }
380e3e87260SThomas Chou
tse_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)38196fa1e43SThomas Chou static int tse_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
382c960b13eSThomas Chou {
38396fa1e43SThomas Chou struct altera_tse_priv *priv = bus->priv;
38496fa1e43SThomas Chou struct alt_tse_mac *mac_dev = priv->mac_dev;
3852cd0a52eSThomas Chou u32 value;
386c960b13eSThomas Chou
387c960b13eSThomas Chou /* set mdio address */
38896fa1e43SThomas Chou writel(addr, &mac_dev->mdio_phy1_addr);
389c960b13eSThomas Chou /* get the data */
39096fa1e43SThomas Chou value = readl(&mac_dev->mdio_phy1[reg]);
391c960b13eSThomas Chou
39296fa1e43SThomas Chou return value & 0xffff;
393c960b13eSThomas Chou }
394c960b13eSThomas Chou
tse_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)39596fa1e43SThomas Chou static int tse_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
39696fa1e43SThomas Chou u16 val)
397c960b13eSThomas Chou {
39896fa1e43SThomas Chou struct altera_tse_priv *priv = bus->priv;
39996fa1e43SThomas Chou struct alt_tse_mac *mac_dev = priv->mac_dev;
400c960b13eSThomas Chou
401c960b13eSThomas Chou /* set mdio address */
40296fa1e43SThomas Chou writel(addr, &mac_dev->mdio_phy1_addr);
40396fa1e43SThomas Chou /* set the data */
40496fa1e43SThomas Chou writel(val, &mac_dev->mdio_phy1[reg]);
405c960b13eSThomas Chou
406c960b13eSThomas Chou return 0;
407c960b13eSThomas Chou }
408c960b13eSThomas Chou
tse_mdio_init(const char * name,struct altera_tse_priv * priv)40996fa1e43SThomas Chou static int tse_mdio_init(const char *name, struct altera_tse_priv *priv)
410c960b13eSThomas Chou {
41196fa1e43SThomas Chou struct mii_dev *bus = mdio_alloc();
412c960b13eSThomas Chou
41396fa1e43SThomas Chou if (!bus) {
41496fa1e43SThomas Chou printf("Failed to allocate MDIO bus\n");
41596fa1e43SThomas Chou return -ENOMEM;
41696fa1e43SThomas Chou }
41796fa1e43SThomas Chou
41896fa1e43SThomas Chou bus->read = tse_mdio_read;
41996fa1e43SThomas Chou bus->write = tse_mdio_write;
420192bc694SBen Whitten snprintf(bus->name, sizeof(bus->name), "%s", name);
42196fa1e43SThomas Chou
42296fa1e43SThomas Chou bus->priv = (void *)priv;
42396fa1e43SThomas Chou
42496fa1e43SThomas Chou return mdio_register(bus);
42596fa1e43SThomas Chou }
42696fa1e43SThomas Chou
tse_phy_init(struct altera_tse_priv * priv,void * dev)42796fa1e43SThomas Chou static int tse_phy_init(struct altera_tse_priv *priv, void *dev)
42896fa1e43SThomas Chou {
42996fa1e43SThomas Chou struct phy_device *phydev;
43096fa1e43SThomas Chou unsigned int mask = 0xffffffff;
43196fa1e43SThomas Chou
43296fa1e43SThomas Chou if (priv->phyaddr)
43396fa1e43SThomas Chou mask = 1 << priv->phyaddr;
43496fa1e43SThomas Chou
43596fa1e43SThomas Chou phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
43696fa1e43SThomas Chou if (!phydev)
43796fa1e43SThomas Chou return -ENODEV;
43896fa1e43SThomas Chou
43996fa1e43SThomas Chou phy_connect_dev(phydev, dev);
44096fa1e43SThomas Chou
44196fa1e43SThomas Chou phydev->supported &= PHY_GBIT_FEATURES;
44296fa1e43SThomas Chou phydev->advertising = phydev->supported;
44396fa1e43SThomas Chou
44496fa1e43SThomas Chou priv->phydev = phydev;
44596fa1e43SThomas Chou phy_config(phydev);
446c960b13eSThomas Chou
447c960b13eSThomas Chou return 0;
448c960b13eSThomas Chou }
449c960b13eSThomas Chou
altera_tse_write_hwaddr(struct udevice * dev)45096fa1e43SThomas Chou static int altera_tse_write_hwaddr(struct udevice *dev)
451c960b13eSThomas Chou {
45296fa1e43SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
45396fa1e43SThomas Chou struct alt_tse_mac *mac_dev = priv->mac_dev;
45496fa1e43SThomas Chou struct eth_pdata *pdata = dev_get_platdata(dev);
45596fa1e43SThomas Chou u8 *hwaddr = pdata->enetaddr;
4562cd0a52eSThomas Chou u32 mac_lo, mac_hi;
457c960b13eSThomas Chou
45896fa1e43SThomas Chou mac_lo = (hwaddr[3] << 24) | (hwaddr[2] << 16) |
45996fa1e43SThomas Chou (hwaddr[1] << 8) | hwaddr[0];
46096fa1e43SThomas Chou mac_hi = (hwaddr[5] << 8) | hwaddr[4];
46196fa1e43SThomas Chou debug("Set MAC address to 0x%04x%08x\n", mac_hi, mac_lo);
462c960b13eSThomas Chou
46396fa1e43SThomas Chou writel(mac_lo, &mac_dev->mac_addr_0);
46496fa1e43SThomas Chou writel(mac_hi, &mac_dev->mac_addr_1);
46596fa1e43SThomas Chou writel(mac_lo, &mac_dev->supp_mac_addr_0_0);
46696fa1e43SThomas Chou writel(mac_hi, &mac_dev->supp_mac_addr_0_1);
46796fa1e43SThomas Chou writel(mac_lo, &mac_dev->supp_mac_addr_1_0);
46896fa1e43SThomas Chou writel(mac_hi, &mac_dev->supp_mac_addr_1_1);
46996fa1e43SThomas Chou writel(mac_lo, &mac_dev->supp_mac_addr_2_0);
47096fa1e43SThomas Chou writel(mac_hi, &mac_dev->supp_mac_addr_2_1);
47196fa1e43SThomas Chou writel(mac_lo, &mac_dev->supp_mac_addr_3_0);
47296fa1e43SThomas Chou writel(mac_hi, &mac_dev->supp_mac_addr_3_1);
473c960b13eSThomas Chou
474c960b13eSThomas Chou return 0;
475c960b13eSThomas Chou }
476c960b13eSThomas Chou
altera_tse_send(struct udevice * dev,void * packet,int length)47738fa4acaSThomas Chou static int altera_tse_send(struct udevice *dev, void *packet, int length)
47838fa4acaSThomas Chou {
47938fa4acaSThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
48038fa4acaSThomas Chou unsigned long tx_buf = (unsigned long)packet;
48138fa4acaSThomas Chou
48238fa4acaSThomas Chou flush_dcache_range(tx_buf, tx_buf + length);
48338fa4acaSThomas Chou
48438fa4acaSThomas Chou return priv->ops->send(dev, packet, length);
48538fa4acaSThomas Chou }
48638fa4acaSThomas Chou
altera_tse_recv(struct udevice * dev,int flags,uchar ** packetp)48738fa4acaSThomas Chou static int altera_tse_recv(struct udevice *dev, int flags, uchar **packetp)
48838fa4acaSThomas Chou {
48938fa4acaSThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
49038fa4acaSThomas Chou
49138fa4acaSThomas Chou return priv->ops->recv(dev, flags, packetp);
49238fa4acaSThomas Chou }
49338fa4acaSThomas Chou
altera_tse_free_pkt(struct udevice * dev,uchar * packet,int length)49438fa4acaSThomas Chou static int altera_tse_free_pkt(struct udevice *dev, uchar *packet,
49538fa4acaSThomas Chou int length)
49638fa4acaSThomas Chou {
49738fa4acaSThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
49838fa4acaSThomas Chou unsigned long rx_buf = (unsigned long)priv->rx_buf;
49938fa4acaSThomas Chou
50038fa4acaSThomas Chou invalidate_dcache_range(rx_buf, rx_buf + PKTSIZE_ALIGN);
50138fa4acaSThomas Chou
50238fa4acaSThomas Chou return priv->ops->free_pkt(dev, packet, length);
50338fa4acaSThomas Chou }
50438fa4acaSThomas Chou
altera_tse_stop(struct udevice * dev)50538fa4acaSThomas Chou static void altera_tse_stop(struct udevice *dev)
50638fa4acaSThomas Chou {
50738fa4acaSThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
50838fa4acaSThomas Chou
50938fa4acaSThomas Chou priv->ops->stop(dev);
51038fa4acaSThomas Chou altera_tse_stop_mac(priv);
51138fa4acaSThomas Chou }
51238fa4acaSThomas Chou
altera_tse_start(struct udevice * dev)51396fa1e43SThomas Chou static int altera_tse_start(struct udevice *dev)
514c960b13eSThomas Chou {
51596fa1e43SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
51696fa1e43SThomas Chou struct alt_tse_mac *mac_dev = priv->mac_dev;
5172cd0a52eSThomas Chou u32 val;
51896fa1e43SThomas Chou int ret;
519c960b13eSThomas Chou
520c960b13eSThomas Chou /* need to create sgdma */
521c960b13eSThomas Chou debug("Configuring rx desc\n");
52296fa1e43SThomas Chou altera_tse_free_pkt(dev, priv->rx_buf, PKTSIZE_ALIGN);
523c960b13eSThomas Chou /* start TSE */
524c960b13eSThomas Chou debug("Configuring TSE Mac\n");
525c960b13eSThomas Chou /* Initialize MAC registers */
52696fa1e43SThomas Chou writel(PKTSIZE_ALIGN, &mac_dev->max_frame_length);
52796fa1e43SThomas Chou writel(priv->rx_fifo_depth - 16, &mac_dev->rx_sel_empty_threshold);
52896fa1e43SThomas Chou writel(0, &mac_dev->rx_sel_full_threshold);
52996fa1e43SThomas Chou writel(priv->tx_fifo_depth - 16, &mac_dev->tx_sel_empty_threshold);
53096fa1e43SThomas Chou writel(0, &mac_dev->tx_sel_full_threshold);
53196fa1e43SThomas Chou writel(8, &mac_dev->rx_almost_empty_threshold);
53296fa1e43SThomas Chou writel(8, &mac_dev->rx_almost_full_threshold);
53396fa1e43SThomas Chou writel(8, &mac_dev->tx_almost_empty_threshold);
53496fa1e43SThomas Chou writel(3, &mac_dev->tx_almost_full_threshold);
535c960b13eSThomas Chou
536c960b13eSThomas Chou /* NO Shift */
53796fa1e43SThomas Chou writel(0, &mac_dev->rx_cmd_stat);
53896fa1e43SThomas Chou writel(0, &mac_dev->tx_cmd_stat);
539c960b13eSThomas Chou
540c960b13eSThomas Chou /* enable MAC */
54196fa1e43SThomas Chou val = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
54296fa1e43SThomas Chou writel(val, &mac_dev->command_config);
543c960b13eSThomas Chou
54496fa1e43SThomas Chou /* Start up the PHY */
54596fa1e43SThomas Chou ret = phy_startup(priv->phydev);
54696fa1e43SThomas Chou if (ret) {
54796fa1e43SThomas Chou debug("Could not initialize PHY %s\n",
54896fa1e43SThomas Chou priv->phydev->dev->name);
54996fa1e43SThomas Chou return ret;
550c960b13eSThomas Chou }
551c960b13eSThomas Chou
55296fa1e43SThomas Chou tse_adjust_link(priv, priv->phydev);
55396fa1e43SThomas Chou
55496fa1e43SThomas Chou if (!priv->phydev->link)
55596fa1e43SThomas Chou return -EIO;
55696fa1e43SThomas Chou
55796fa1e43SThomas Chou return 0;
558c960b13eSThomas Chou }
559c960b13eSThomas Chou
56038fa4acaSThomas Chou static const struct tse_ops tse_sgdma_ops = {
56138fa4acaSThomas Chou .send = altera_tse_send_sgdma,
56238fa4acaSThomas Chou .recv = altera_tse_recv_sgdma,
56338fa4acaSThomas Chou .free_pkt = altera_tse_free_pkt_sgdma,
56438fa4acaSThomas Chou .stop = altera_tse_stop_sgdma,
56538fa4acaSThomas Chou };
56638fa4acaSThomas Chou
567e3e87260SThomas Chou static const struct tse_ops tse_msgdma_ops = {
568e3e87260SThomas Chou .send = altera_tse_send_msgdma,
569e3e87260SThomas Chou .recv = altera_tse_recv_msgdma,
570e3e87260SThomas Chou .free_pkt = altera_tse_free_pkt_msgdma,
571e3e87260SThomas Chou .stop = altera_tse_stop_msgdma,
572e3e87260SThomas Chou };
573e3e87260SThomas Chou
altera_tse_probe(struct udevice * dev)57496fa1e43SThomas Chou static int altera_tse_probe(struct udevice *dev)
575c960b13eSThomas Chou {
57696fa1e43SThomas Chou struct eth_pdata *pdata = dev_get_platdata(dev);
57796fa1e43SThomas Chou struct altera_tse_priv *priv = dev_get_priv(dev);
57875199d6fSThomas Chou void *blob = (void *)gd->fdt_blob;
579e160f7d4SSimon Glass int node = dev_of_offset(dev);
58096fa1e43SThomas Chou const char *list, *end;
58196fa1e43SThomas Chou const fdt32_t *cell;
58296fa1e43SThomas Chou void *base, *desc_mem = NULL;
58396fa1e43SThomas Chou unsigned long addr, size;
58475199d6fSThomas Chou int parent, addrc, sizec;
58596fa1e43SThomas Chou int len, idx;
58696fa1e43SThomas Chou int ret;
587c960b13eSThomas Chou
58838fa4acaSThomas Chou priv->dma_type = dev_get_driver_data(dev);
58938fa4acaSThomas Chou if (priv->dma_type == ALT_SGDMA)
59038fa4acaSThomas Chou priv->ops = &tse_sgdma_ops;
591e3e87260SThomas Chou else
592e3e87260SThomas Chou priv->ops = &tse_msgdma_ops;
59396fa1e43SThomas Chou /*
59475199d6fSThomas Chou * decode regs. there are multiple reg tuples, and they need to
59575199d6fSThomas Chou * match with reg-names.
59696fa1e43SThomas Chou */
59775199d6fSThomas Chou parent = fdt_parent_offset(blob, node);
598*eed36609SSimon Glass fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
59996fa1e43SThomas Chou list = fdt_getprop(blob, node, "reg-names", &len);
60096fa1e43SThomas Chou if (!list)
60196fa1e43SThomas Chou return -ENOENT;
60296fa1e43SThomas Chou end = list + len;
60396fa1e43SThomas Chou cell = fdt_getprop(blob, node, "reg", &len);
60496fa1e43SThomas Chou if (!cell)
60596fa1e43SThomas Chou return -ENOENT;
60696fa1e43SThomas Chou idx = 0;
60796fa1e43SThomas Chou while (list < end) {
60896fa1e43SThomas Chou addr = fdt_translate_address((void *)blob,
60996fa1e43SThomas Chou node, cell + idx);
61075199d6fSThomas Chou size = fdt_addr_to_cpu(cell[idx + addrc]);
611e2b259f7SThomas Chou base = map_physmem(addr, size, MAP_NOCACHE);
61296fa1e43SThomas Chou len = strlen(list);
61396fa1e43SThomas Chou if (strcmp(list, "control_port") == 0)
61496fa1e43SThomas Chou priv->mac_dev = base;
61596fa1e43SThomas Chou else if (strcmp(list, "rx_csr") == 0)
61696fa1e43SThomas Chou priv->sgdma_rx = base;
617e3e87260SThomas Chou else if (strcmp(list, "rx_desc") == 0)
618e3e87260SThomas Chou priv->rx_desc = base;
619e3e87260SThomas Chou else if (strcmp(list, "rx_resp") == 0)
620e3e87260SThomas Chou priv->rx_resp = base;
62196fa1e43SThomas Chou else if (strcmp(list, "tx_csr") == 0)
62296fa1e43SThomas Chou priv->sgdma_tx = base;
623e3e87260SThomas Chou else if (strcmp(list, "tx_desc") == 0)
624e3e87260SThomas Chou priv->tx_desc = base;
62596fa1e43SThomas Chou else if (strcmp(list, "s1") == 0)
62696fa1e43SThomas Chou desc_mem = base;
62775199d6fSThomas Chou idx += addrc + sizec;
62896fa1e43SThomas Chou list += (len + 1);
62996fa1e43SThomas Chou }
63096fa1e43SThomas Chou /* decode fifo depth */
63196fa1e43SThomas Chou priv->rx_fifo_depth = fdtdec_get_int(blob, node,
63296fa1e43SThomas Chou "rx-fifo-depth", 0);
63396fa1e43SThomas Chou priv->tx_fifo_depth = fdtdec_get_int(blob, node,
63496fa1e43SThomas Chou "tx-fifo-depth", 0);
63596fa1e43SThomas Chou /* decode phy */
63696fa1e43SThomas Chou addr = fdtdec_get_int(blob, node,
63796fa1e43SThomas Chou "phy-handle", 0);
63896fa1e43SThomas Chou addr = fdt_node_offset_by_phandle(blob, addr);
63996fa1e43SThomas Chou priv->phyaddr = fdtdec_get_int(blob, addr,
64096fa1e43SThomas Chou "reg", 0);
64196fa1e43SThomas Chou /* init desc */
64238fa4acaSThomas Chou if (priv->dma_type == ALT_SGDMA) {
64396fa1e43SThomas Chou len = sizeof(struct alt_sgdma_descriptor) * 4;
64496fa1e43SThomas Chou if (!desc_mem) {
64596fa1e43SThomas Chou desc_mem = dma_alloc_coherent(len, &addr);
64696fa1e43SThomas Chou if (!desc_mem)
64796fa1e43SThomas Chou return -ENOMEM;
64896fa1e43SThomas Chou }
64996fa1e43SThomas Chou memset(desc_mem, 0, len);
65096fa1e43SThomas Chou priv->tx_desc = desc_mem;
65138fa4acaSThomas Chou priv->rx_desc = priv->tx_desc +
65238fa4acaSThomas Chou 2 * sizeof(struct alt_sgdma_descriptor);
65338fa4acaSThomas Chou }
65496fa1e43SThomas Chou /* allocate recv packet buffer */
65596fa1e43SThomas Chou priv->rx_buf = malloc_cache_aligned(PKTSIZE_ALIGN);
65696fa1e43SThomas Chou if (!priv->rx_buf)
65796fa1e43SThomas Chou return -ENOMEM;
658c960b13eSThomas Chou
65996fa1e43SThomas Chou /* stop controller */
66096fa1e43SThomas Chou debug("Reset TSE & SGDMAs\n");
66196fa1e43SThomas Chou altera_tse_stop(dev);
662c960b13eSThomas Chou
66396fa1e43SThomas Chou /* start the phy */
66496fa1e43SThomas Chou priv->interface = pdata->phy_interface;
66596fa1e43SThomas Chou tse_mdio_init(dev->name, priv);
66696fa1e43SThomas Chou priv->bus = miiphy_get_dev_by_name(dev->name);
667c960b13eSThomas Chou
66896fa1e43SThomas Chou ret = tse_phy_init(priv, dev);
669c960b13eSThomas Chou
67096fa1e43SThomas Chou return ret;
67196fa1e43SThomas Chou }
67296fa1e43SThomas Chou
altera_tse_ofdata_to_platdata(struct udevice * dev)67396fa1e43SThomas Chou static int altera_tse_ofdata_to_platdata(struct udevice *dev)
67496fa1e43SThomas Chou {
67596fa1e43SThomas Chou struct eth_pdata *pdata = dev_get_platdata(dev);
67696fa1e43SThomas Chou const char *phy_mode;
67796fa1e43SThomas Chou
67896fa1e43SThomas Chou pdata->phy_interface = -1;
679e160f7d4SSimon Glass phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
680e160f7d4SSimon Glass NULL);
68196fa1e43SThomas Chou if (phy_mode)
68296fa1e43SThomas Chou pdata->phy_interface = phy_get_interface_by_name(phy_mode);
68396fa1e43SThomas Chou if (pdata->phy_interface == -1) {
68496fa1e43SThomas Chou debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
68596fa1e43SThomas Chou return -EINVAL;
68696fa1e43SThomas Chou }
68796fa1e43SThomas Chou
688c960b13eSThomas Chou return 0;
689c960b13eSThomas Chou }
690b962ac79SJoachim Foerster
69196fa1e43SThomas Chou static const struct eth_ops altera_tse_ops = {
69296fa1e43SThomas Chou .start = altera_tse_start,
69396fa1e43SThomas Chou .send = altera_tse_send,
69496fa1e43SThomas Chou .recv = altera_tse_recv,
69596fa1e43SThomas Chou .free_pkt = altera_tse_free_pkt,
69696fa1e43SThomas Chou .stop = altera_tse_stop,
69796fa1e43SThomas Chou .write_hwaddr = altera_tse_write_hwaddr,
69896fa1e43SThomas Chou };
699c960b13eSThomas Chou
70096fa1e43SThomas Chou static const struct udevice_id altera_tse_ids[] = {
701e3e87260SThomas Chou { .compatible = "altr,tse-msgdma-1.0", .data = ALT_MSGDMA },
70238fa4acaSThomas Chou { .compatible = "altr,tse-1.0", .data = ALT_SGDMA },
70396fa1e43SThomas Chou {}
70496fa1e43SThomas Chou };
705c960b13eSThomas Chou
70696fa1e43SThomas Chou U_BOOT_DRIVER(altera_tse) = {
70796fa1e43SThomas Chou .name = "altera_tse",
70896fa1e43SThomas Chou .id = UCLASS_ETH,
70996fa1e43SThomas Chou .of_match = altera_tse_ids,
71096fa1e43SThomas Chou .ops = &altera_tse_ops,
71196fa1e43SThomas Chou .ofdata_to_platdata = altera_tse_ofdata_to_platdata,
71296fa1e43SThomas Chou .platdata_auto_alloc_size = sizeof(struct eth_pdata),
71396fa1e43SThomas Chou .priv_auto_alloc_size = sizeof(struct altera_tse_priv),
71496fa1e43SThomas Chou .probe = altera_tse_probe,
71596fa1e43SThomas Chou };
716