1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Atheros AR71xx / AR9xxx GMAC driver 4 * 5 * Copyright (C) 2016 Marek Vasut <marex@denx.de> 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <miiphy.h> 12 #include <malloc.h> 13 #include <linux/compiler.h> 14 #include <linux/err.h> 15 #include <linux/mii.h> 16 #include <wait_bit.h> 17 #include <asm/io.h> 18 19 #include <mach/ath79.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 enum ag7xxx_model { 24 AG7XXX_MODEL_AG933X, 25 AG7XXX_MODEL_AG934X, 26 }; 27 28 /* MAC Configuration 1 */ 29 #define AG7XXX_ETH_CFG1 0x00 30 #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31) 31 #define AG7XXX_ETH_CFG1_RX_RST BIT(19) 32 #define AG7XXX_ETH_CFG1_TX_RST BIT(18) 33 #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8) 34 #define AG7XXX_ETH_CFG1_RX_EN BIT(2) 35 #define AG7XXX_ETH_CFG1_TX_EN BIT(0) 36 37 /* MAC Configuration 2 */ 38 #define AG7XXX_ETH_CFG2 0x04 39 #define AG7XXX_ETH_CFG2_IF_1000 BIT(9) 40 #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8) 41 #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8) 42 #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5) 43 #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4) 44 #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2) 45 #define AG7XXX_ETH_CFG2_FDX BIT(0) 46 47 /* MII Configuration */ 48 #define AG7XXX_ETH_MII_MGMT_CFG 0x20 49 #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31) 50 51 /* MII Command */ 52 #define AG7XXX_ETH_MII_MGMT_CMD 0x24 53 #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1 54 55 /* MII Address */ 56 #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28 57 #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8 58 59 /* MII Control */ 60 #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c 61 62 /* MII Status */ 63 #define AG7XXX_ETH_MII_MGMT_STATUS 0x30 64 65 /* MII Indicators */ 66 #define AG7XXX_ETH_MII_MGMT_IND 0x34 67 #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2) 68 #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0) 69 70 /* STA Address 1 & 2 */ 71 #define AG7XXX_ETH_ADDR1 0x40 72 #define AG7XXX_ETH_ADDR2 0x44 73 74 /* ETH Configuration 0 - 5 */ 75 #define AG7XXX_ETH_FIFO_CFG_0 0x48 76 #define AG7XXX_ETH_FIFO_CFG_1 0x4c 77 #define AG7XXX_ETH_FIFO_CFG_2 0x50 78 #define AG7XXX_ETH_FIFO_CFG_3 0x54 79 #define AG7XXX_ETH_FIFO_CFG_4 0x58 80 #define AG7XXX_ETH_FIFO_CFG_5 0x5c 81 82 /* DMA Transfer Control for Queue 0 */ 83 #define AG7XXX_ETH_DMA_TX_CTRL 0x180 84 #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0) 85 86 /* Descriptor Address for Queue 0 Tx */ 87 #define AG7XXX_ETH_DMA_TX_DESC 0x184 88 89 /* DMA Tx Status */ 90 #define AG7XXX_ETH_DMA_TX_STATUS 0x188 91 92 /* Rx Control */ 93 #define AG7XXX_ETH_DMA_RX_CTRL 0x18c 94 #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0) 95 96 /* Pointer to Rx Descriptor */ 97 #define AG7XXX_ETH_DMA_RX_DESC 0x190 98 99 /* Rx Status */ 100 #define AG7XXX_ETH_DMA_RX_STATUS 0x194 101 102 /* Custom register at 0x18070000 */ 103 #define AG7XXX_GMAC_ETH_CFG 0x00 104 #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) 105 #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7) 106 #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6) 107 #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5) 108 #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4) 109 #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3) 110 #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2) 111 #define AG7XXX_ETH_CFG_MII_GE0 BIT(1) 112 #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0) 113 114 #define CONFIG_TX_DESCR_NUM 8 115 #define CONFIG_RX_DESCR_NUM 8 116 #define CONFIG_ETH_BUFSIZE 2048 117 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) 118 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) 119 120 /* DMA descriptor. */ 121 struct ag7xxx_dma_desc { 122 u32 data_addr; 123 #define AG7XXX_DMADESC_IS_EMPTY BIT(31) 124 #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16 125 #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0 126 #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff 127 u32 config; 128 u32 next_desc; 129 u32 _pad[5]; 130 }; 131 132 struct ar7xxx_eth_priv { 133 struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; 134 struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; 135 char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); 136 char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); 137 138 void __iomem *regs; 139 void __iomem *phyregs; 140 141 struct eth_device *dev; 142 struct phy_device *phydev; 143 struct mii_dev *bus; 144 145 u32 interface; 146 u32 tx_currdescnum; 147 u32 rx_currdescnum; 148 enum ag7xxx_model model; 149 }; 150 151 /* 152 * Switch and MDIO access 153 */ 154 static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val) 155 { 156 struct ar7xxx_eth_priv *priv = bus->priv; 157 void __iomem *regs = priv->phyregs; 158 int ret; 159 160 writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD); 161 writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg, 162 regs + AG7XXX_ETH_MII_MGMT_ADDRESS); 163 writel(AG7XXX_ETH_MII_MGMT_CMD_READ, 164 regs + AG7XXX_ETH_MII_MGMT_CMD); 165 166 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND, 167 AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0); 168 if (ret) 169 return ret; 170 171 *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff; 172 writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD); 173 174 return 0; 175 } 176 177 static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val) 178 { 179 struct ar7xxx_eth_priv *priv = bus->priv; 180 void __iomem *regs = priv->phyregs; 181 int ret; 182 183 writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg, 184 regs + AG7XXX_ETH_MII_MGMT_ADDRESS); 185 writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL); 186 187 ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND, 188 AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0); 189 190 return ret; 191 } 192 193 static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val) 194 { 195 struct ar7xxx_eth_priv *priv = bus->priv; 196 u32 phy_addr; 197 u32 reg_addr; 198 u32 phy_temp; 199 u32 reg_temp; 200 u16 rv = 0; 201 int ret; 202 203 if (priv->model == AG7XXX_MODEL_AG933X) { 204 phy_addr = 0x1f; 205 reg_addr = 0x10; 206 } else if (priv->model == AG7XXX_MODEL_AG934X) { 207 phy_addr = 0x18; 208 reg_addr = 0x00; 209 } else 210 return -EINVAL; 211 212 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); 213 if (ret) 214 return ret; 215 216 phy_temp = ((reg >> 6) & 0x7) | 0x10; 217 reg_temp = (reg >> 1) & 0x1e; 218 *val = 0; 219 220 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv); 221 if (ret < 0) 222 return ret; 223 *val |= rv; 224 225 ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv); 226 if (ret < 0) 227 return ret; 228 *val |= (rv << 16); 229 230 return 0; 231 } 232 233 static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val) 234 { 235 struct ar7xxx_eth_priv *priv = bus->priv; 236 u32 phy_addr; 237 u32 reg_addr; 238 u32 phy_temp; 239 u32 reg_temp; 240 int ret; 241 242 if (priv->model == AG7XXX_MODEL_AG933X) { 243 phy_addr = 0x1f; 244 reg_addr = 0x10; 245 } else if (priv->model == AG7XXX_MODEL_AG934X) { 246 phy_addr = 0x18; 247 reg_addr = 0x00; 248 } else 249 return -EINVAL; 250 251 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); 252 if (ret) 253 return ret; 254 255 phy_temp = ((reg >> 6) & 0x7) | 0x10; 256 reg_temp = (reg >> 1) & 0x1e; 257 258 /* 259 * The switch on AR933x has some special register behavior, which 260 * expects particular write order of their nibbles: 261 * 0x40 ..... MSB first, LSB second 262 * 0x50 ..... MSB first, LSB second 263 * 0x98 ..... LSB first, MSB second 264 * others ... don't care 265 */ 266 if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) { 267 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); 268 if (ret < 0) 269 return ret; 270 271 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); 272 if (ret < 0) 273 return ret; 274 } else { 275 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16); 276 if (ret < 0) 277 return ret; 278 279 ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff); 280 if (ret < 0) 281 return ret; 282 } 283 284 return 0; 285 } 286 287 static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val) 288 { 289 u32 data; 290 unsigned long start; 291 int ret; 292 /* No idea if this is long enough or too long */ 293 int timeout_ms = 1000; 294 295 /* Dummy read followed by PHY read/write command. */ 296 ret = ag7xxx_switch_reg_read(bus, 0x98, &data); 297 if (ret < 0) 298 return ret; 299 data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31); 300 ret = ag7xxx_switch_reg_write(bus, 0x98, data); 301 if (ret < 0) 302 return ret; 303 304 start = get_timer(0); 305 306 /* Wait for operation to finish */ 307 do { 308 ret = ag7xxx_switch_reg_read(bus, 0x98, &data); 309 if (ret < 0) 310 return ret; 311 312 if (get_timer(start) > timeout_ms) 313 return -ETIMEDOUT; 314 } while (data & BIT(31)); 315 316 return data & 0xffff; 317 } 318 319 static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 320 { 321 return ag7xxx_mdio_rw(bus, addr, reg, BIT(27)); 322 } 323 324 static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 325 u16 val) 326 { 327 int ret; 328 329 ret = ag7xxx_mdio_rw(bus, addr, reg, val); 330 if (ret < 0) 331 return ret; 332 return 0; 333 } 334 335 /* 336 * DMA ring handlers 337 */ 338 static void ag7xxx_dma_clean_tx(struct udevice *dev) 339 { 340 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 341 struct ag7xxx_dma_desc *curr, *next; 342 u32 start, end; 343 int i; 344 345 for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) { 346 curr = &priv->tx_mac_descrtable[i]; 347 next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM]; 348 349 curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]); 350 curr->config = AG7XXX_DMADESC_IS_EMPTY; 351 curr->next_desc = virt_to_phys(next); 352 } 353 354 priv->tx_currdescnum = 0; 355 356 /* Cache: Flush descriptors, don't care about buffers. */ 357 start = (u32)(&priv->tx_mac_descrtable[0]); 358 end = start + sizeof(priv->tx_mac_descrtable); 359 flush_dcache_range(start, end); 360 } 361 362 static void ag7xxx_dma_clean_rx(struct udevice *dev) 363 { 364 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 365 struct ag7xxx_dma_desc *curr, *next; 366 u32 start, end; 367 int i; 368 369 for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) { 370 curr = &priv->rx_mac_descrtable[i]; 371 next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM]; 372 373 curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]); 374 curr->config = AG7XXX_DMADESC_IS_EMPTY; 375 curr->next_desc = virt_to_phys(next); 376 } 377 378 priv->rx_currdescnum = 0; 379 380 /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */ 381 start = (u32)(&priv->rx_mac_descrtable[0]); 382 end = start + sizeof(priv->rx_mac_descrtable); 383 flush_dcache_range(start, end); 384 invalidate_dcache_range(start, end); 385 386 start = (u32)&priv->rxbuffs; 387 end = start + sizeof(priv->rxbuffs); 388 invalidate_dcache_range(start, end); 389 } 390 391 /* 392 * Ethernet I/O 393 */ 394 static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length) 395 { 396 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 397 struct ag7xxx_dma_desc *curr; 398 u32 start, end; 399 400 curr = &priv->tx_mac_descrtable[priv->tx_currdescnum]; 401 402 /* Cache: Invalidate descriptor. */ 403 start = (u32)curr; 404 end = start + sizeof(*curr); 405 invalidate_dcache_range(start, end); 406 407 if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) { 408 printf("ag7xxx: Out of TX DMA descriptors!\n"); 409 return -EPERM; 410 } 411 412 /* Copy the packet into the data buffer. */ 413 memcpy(phys_to_virt(curr->data_addr), packet, length); 414 curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK; 415 416 /* Cache: Flush descriptor, Flush buffer. */ 417 start = (u32)curr; 418 end = start + sizeof(*curr); 419 flush_dcache_range(start, end); 420 start = (u32)phys_to_virt(curr->data_addr); 421 end = start + length; 422 flush_dcache_range(start, end); 423 424 /* Load the DMA descriptor and start TX DMA. */ 425 writel(AG7XXX_ETH_DMA_TX_CTRL_TXE, 426 priv->regs + AG7XXX_ETH_DMA_TX_CTRL); 427 428 /* Switch to next TX descriptor. */ 429 priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM; 430 431 return 0; 432 } 433 434 static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp) 435 { 436 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 437 struct ag7xxx_dma_desc *curr; 438 u32 start, end, length; 439 440 curr = &priv->rx_mac_descrtable[priv->rx_currdescnum]; 441 442 /* Cache: Invalidate descriptor. */ 443 start = (u32)curr; 444 end = start + sizeof(*curr); 445 invalidate_dcache_range(start, end); 446 447 /* No packets received. */ 448 if (curr->config & AG7XXX_DMADESC_IS_EMPTY) 449 return -EAGAIN; 450 451 length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK; 452 453 /* Cache: Invalidate buffer. */ 454 start = (u32)phys_to_virt(curr->data_addr); 455 end = start + length; 456 invalidate_dcache_range(start, end); 457 458 /* Receive one packet and return length. */ 459 *packetp = phys_to_virt(curr->data_addr); 460 return length; 461 } 462 463 static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet, 464 int length) 465 { 466 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 467 struct ag7xxx_dma_desc *curr; 468 u32 start, end; 469 470 curr = &priv->rx_mac_descrtable[priv->rx_currdescnum]; 471 472 curr->config = AG7XXX_DMADESC_IS_EMPTY; 473 474 /* Cache: Flush descriptor. */ 475 start = (u32)curr; 476 end = start + sizeof(*curr); 477 flush_dcache_range(start, end); 478 479 /* Switch to next RX descriptor. */ 480 priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM; 481 482 return 0; 483 } 484 485 static int ag7xxx_eth_start(struct udevice *dev) 486 { 487 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 488 489 /* FIXME: Check if link up */ 490 491 /* Clear the DMA rings. */ 492 ag7xxx_dma_clean_tx(dev); 493 ag7xxx_dma_clean_rx(dev); 494 495 /* Load DMA descriptors and start the RX DMA. */ 496 writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]), 497 priv->regs + AG7XXX_ETH_DMA_TX_DESC); 498 writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]), 499 priv->regs + AG7XXX_ETH_DMA_RX_DESC); 500 writel(AG7XXX_ETH_DMA_RX_CTRL_RXE, 501 priv->regs + AG7XXX_ETH_DMA_RX_CTRL); 502 503 return 0; 504 } 505 506 static void ag7xxx_eth_stop(struct udevice *dev) 507 { 508 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 509 510 /* Stop the TX DMA. */ 511 writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL); 512 wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0, 513 1000, 0); 514 515 /* Stop the RX DMA. */ 516 writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL); 517 wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0, 518 1000, 0); 519 } 520 521 /* 522 * Hardware setup 523 */ 524 static int ag7xxx_eth_write_hwaddr(struct udevice *dev) 525 { 526 struct eth_pdata *pdata = dev_get_platdata(dev); 527 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 528 unsigned char *mac = pdata->enetaddr; 529 u32 macid_lo, macid_hi; 530 531 macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24); 532 macid_lo = (mac[5] << 16) | (mac[4] << 24); 533 534 writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1); 535 writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2); 536 537 return 0; 538 } 539 540 static void ag7xxx_hw_setup(struct udevice *dev) 541 { 542 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 543 u32 speed; 544 545 setbits_be32(priv->regs + AG7XXX_ETH_CFG1, 546 AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST | 547 AG7XXX_ETH_CFG1_SOFT_RST); 548 549 mdelay(10); 550 551 writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN, 552 priv->regs + AG7XXX_ETH_CFG1); 553 554 if (priv->interface == PHY_INTERFACE_MODE_RMII) 555 speed = AG7XXX_ETH_CFG2_IF_10_100; 556 else 557 speed = AG7XXX_ETH_CFG2_IF_1000; 558 559 clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2, 560 AG7XXX_ETH_CFG2_IF_SPEED_MASK, 561 speed | AG7XXX_ETH_CFG2_PAD_CRC_EN | 562 AG7XXX_ETH_CFG2_LEN_CHECK); 563 564 writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1); 565 writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2); 566 567 writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0); 568 setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff); 569 writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1); 570 writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2); 571 writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5); 572 writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3); 573 } 574 575 static int ag7xxx_mii_get_div(void) 576 { 577 ulong freq = get_bus_freq(0); 578 579 switch (freq / 1000000) { 580 case 150: return 0x7; 581 case 175: return 0x5; 582 case 200: return 0x4; 583 case 210: return 0x9; 584 case 220: return 0x9; 585 default: return 0x7; 586 } 587 } 588 589 static int ag7xxx_mii_setup(struct udevice *dev) 590 { 591 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 592 int i, ret, div = ag7xxx_mii_get_div(); 593 u32 reg; 594 595 if (priv->model == AG7XXX_MODEL_AG933X) { 596 /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */ 597 if (priv->interface == PHY_INTERFACE_MODE_RMII) 598 return 0; 599 } 600 601 if (priv->model == AG7XXX_MODEL_AG934X) { 602 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | 0x4, 603 priv->regs + AG7XXX_ETH_MII_MGMT_CFG); 604 writel(0x4, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); 605 return 0; 606 } 607 608 for (i = 0; i < 10; i++) { 609 writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div, 610 priv->regs + AG7XXX_ETH_MII_MGMT_CFG); 611 writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG); 612 613 /* Check the switch */ 614 ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, ®); 615 if (ret) 616 continue; 617 618 if (reg != 0x18007fff) 619 continue; 620 621 return 0; 622 } 623 624 return -EINVAL; 625 } 626 627 static int ag933x_phy_setup_wan(struct udevice *dev) 628 { 629 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 630 631 /* Configure switch port 4 (GMAC0) */ 632 return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000); 633 } 634 635 static int ag933x_phy_setup_lan(struct udevice *dev) 636 { 637 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 638 int i, ret; 639 u32 reg; 640 641 /* Reset the switch */ 642 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); 643 if (ret) 644 return ret; 645 reg |= BIT(31); 646 ret = ag7xxx_switch_reg_write(priv->bus, 0, reg); 647 if (ret) 648 return ret; 649 650 do { 651 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); 652 if (ret) 653 return ret; 654 } while (reg & BIT(31)); 655 656 /* Configure switch ports 0...3 (GMAC1) */ 657 for (i = 0; i < 4; i++) { 658 ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000); 659 if (ret) 660 return ret; 661 } 662 663 /* Enable CPU port */ 664 ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8)); 665 if (ret) 666 return ret; 667 668 for (i = 0; i < 4; i++) { 669 ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9)); 670 if (ret) 671 return ret; 672 } 673 674 /* QM Control */ 675 ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e); 676 if (ret) 677 return ret; 678 679 /* Disable Atheros header */ 680 ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004); 681 if (ret) 682 return ret; 683 684 /* Tag priority mapping */ 685 ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50); 686 if (ret) 687 return ret; 688 689 /* Enable ARP packets to the CPU */ 690 ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®); 691 if (ret) 692 return ret; 693 reg |= 0x100000; 694 ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg); 695 if (ret) 696 return ret; 697 698 return 0; 699 } 700 701 static int ag933x_phy_setup_reset_set(struct udevice *dev, int port) 702 { 703 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 704 int ret; 705 706 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE, 707 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | 708 ADVERTISE_PAUSE_ASYM); 709 if (ret) 710 return ret; 711 712 if (priv->model == AG7XXX_MODEL_AG934X) { 713 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000, 714 ADVERTISE_1000FULL); 715 if (ret) 716 return ret; 717 } 718 719 return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR, 720 BMCR_ANENABLE | BMCR_RESET); 721 } 722 723 static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port) 724 { 725 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 726 int ret; 727 728 do { 729 ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR); 730 if (ret < 0) 731 return ret; 732 mdelay(10); 733 } while (ret & BMCR_RESET); 734 735 return 0; 736 } 737 738 static int ag933x_phy_setup_common(struct udevice *dev) 739 { 740 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 741 int i, ret, phymax; 742 743 if (priv->model == AG7XXX_MODEL_AG933X) 744 phymax = 4; 745 else if (priv->model == AG7XXX_MODEL_AG934X) 746 phymax = 5; 747 else 748 return -EINVAL; 749 750 if (priv->interface == PHY_INTERFACE_MODE_RMII) { 751 ret = ag933x_phy_setup_reset_set(dev, phymax); 752 if (ret) 753 return ret; 754 755 ret = ag933x_phy_setup_reset_fin(dev, phymax); 756 if (ret) 757 return ret; 758 759 /* Read out link status */ 760 ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR); 761 if (ret < 0) 762 return ret; 763 764 return 0; 765 } 766 767 /* Switch ports */ 768 for (i = 0; i < phymax; i++) { 769 ret = ag933x_phy_setup_reset_set(dev, i); 770 if (ret) 771 return ret; 772 } 773 774 for (i = 0; i < phymax; i++) { 775 ret = ag933x_phy_setup_reset_fin(dev, i); 776 if (ret) 777 return ret; 778 } 779 780 for (i = 0; i < phymax; i++) { 781 /* Read out link status */ 782 ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR); 783 if (ret < 0) 784 return ret; 785 } 786 787 return 0; 788 } 789 790 static int ag934x_phy_setup(struct udevice *dev) 791 { 792 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 793 int i, ret; 794 u32 reg; 795 796 ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f); 797 if (ret) 798 return ret; 799 ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000); 800 if (ret) 801 return ret; 802 ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000); 803 if (ret) 804 return ret; 805 ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000); 806 if (ret) 807 return ret; 808 ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e); 809 if (ret) 810 return ret; 811 812 /* AR8327/AR8328 v1.0 fixup */ 813 ret = ag7xxx_switch_reg_read(priv->bus, 0, ®); 814 if (ret) 815 return ret; 816 if ((reg & 0xffff) == 0x1201) { 817 for (i = 0; i < 5; i++) { 818 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0); 819 if (ret) 820 return ret; 821 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea); 822 if (ret) 823 return ret; 824 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d); 825 if (ret) 826 return ret; 827 ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0); 828 if (ret) 829 return ret; 830 } 831 } 832 833 ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, ®); 834 if (ret) 835 return ret; 836 reg &= ~0x70000; 837 ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg); 838 if (ret) 839 return ret; 840 841 return 0; 842 } 843 844 static int ag7xxx_mac_probe(struct udevice *dev) 845 { 846 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 847 int ret; 848 849 ag7xxx_hw_setup(dev); 850 ret = ag7xxx_mii_setup(dev); 851 if (ret) 852 return ret; 853 854 ag7xxx_eth_write_hwaddr(dev); 855 856 if (priv->model == AG7XXX_MODEL_AG933X) { 857 if (priv->interface == PHY_INTERFACE_MODE_RMII) 858 ret = ag933x_phy_setup_wan(dev); 859 else 860 ret = ag933x_phy_setup_lan(dev); 861 } else if (priv->model == AG7XXX_MODEL_AG934X) { 862 ret = ag934x_phy_setup(dev); 863 } else { 864 return -EINVAL; 865 } 866 867 if (ret) 868 return ret; 869 870 return ag933x_phy_setup_common(dev); 871 } 872 873 static int ag7xxx_mdio_probe(struct udevice *dev) 874 { 875 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 876 struct mii_dev *bus = mdio_alloc(); 877 878 if (!bus) 879 return -ENOMEM; 880 881 bus->read = ag7xxx_mdio_read; 882 bus->write = ag7xxx_mdio_write; 883 snprintf(bus->name, sizeof(bus->name), dev->name); 884 885 bus->priv = (void *)priv; 886 887 return mdio_register(bus); 888 } 889 890 static int ag7xxx_get_phy_iface_offset(struct udevice *dev) 891 { 892 int offset; 893 894 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy"); 895 if (offset <= 0) { 896 debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset); 897 return -EINVAL; 898 } 899 900 offset = fdt_parent_offset(gd->fdt_blob, offset); 901 if (offset <= 0) { 902 debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n", 903 __func__, offset); 904 return -EINVAL; 905 } 906 907 offset = fdt_parent_offset(gd->fdt_blob, offset); 908 if (offset <= 0) { 909 debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n", 910 __func__, offset); 911 return -EINVAL; 912 } 913 914 return offset; 915 } 916 917 static int ag7xxx_eth_probe(struct udevice *dev) 918 { 919 struct eth_pdata *pdata = dev_get_platdata(dev); 920 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 921 void __iomem *iobase, *phyiobase; 922 int ret, phyreg; 923 924 /* Decoding of convoluted PHY wiring on Atheros MIPS. */ 925 ret = ag7xxx_get_phy_iface_offset(dev); 926 if (ret <= 0) 927 return ret; 928 phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1); 929 930 iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE); 931 phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE); 932 933 debug("%s, iobase=%p, phyiobase=%p, priv=%p\n", 934 __func__, iobase, phyiobase, priv); 935 priv->regs = iobase; 936 priv->phyregs = phyiobase; 937 priv->interface = pdata->phy_interface; 938 priv->model = dev_get_driver_data(dev); 939 940 ret = ag7xxx_mdio_probe(dev); 941 if (ret) 942 return ret; 943 944 priv->bus = miiphy_get_dev_by_name(dev->name); 945 946 ret = ag7xxx_mac_probe(dev); 947 debug("%s, ret=%d\n", __func__, ret); 948 949 return ret; 950 } 951 952 static int ag7xxx_eth_remove(struct udevice *dev) 953 { 954 struct ar7xxx_eth_priv *priv = dev_get_priv(dev); 955 956 free(priv->phydev); 957 mdio_unregister(priv->bus); 958 mdio_free(priv->bus); 959 960 return 0; 961 } 962 963 static const struct eth_ops ag7xxx_eth_ops = { 964 .start = ag7xxx_eth_start, 965 .send = ag7xxx_eth_send, 966 .recv = ag7xxx_eth_recv, 967 .free_pkt = ag7xxx_eth_free_pkt, 968 .stop = ag7xxx_eth_stop, 969 .write_hwaddr = ag7xxx_eth_write_hwaddr, 970 }; 971 972 static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev) 973 { 974 struct eth_pdata *pdata = dev_get_platdata(dev); 975 const char *phy_mode; 976 int ret; 977 978 pdata->iobase = devfdt_get_addr(dev); 979 pdata->phy_interface = -1; 980 981 /* Decoding of convoluted PHY wiring on Atheros MIPS. */ 982 ret = ag7xxx_get_phy_iface_offset(dev); 983 if (ret <= 0) 984 return ret; 985 986 phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL); 987 if (phy_mode) 988 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 989 if (pdata->phy_interface == -1) { 990 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 991 return -EINVAL; 992 } 993 994 return 0; 995 } 996 997 static const struct udevice_id ag7xxx_eth_ids[] = { 998 { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X }, 999 { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X }, 1000 { } 1001 }; 1002 1003 U_BOOT_DRIVER(eth_ag7xxx) = { 1004 .name = "eth_ag7xxx", 1005 .id = UCLASS_ETH, 1006 .of_match = ag7xxx_eth_ids, 1007 .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata, 1008 .probe = ag7xxx_eth_probe, 1009 .remove = ag7xxx_eth_remove, 1010 .ops = &ag7xxx_eth_ops, 1011 .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv), 1012 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1013 .flags = DM_FLAG_ALLOC_PRIV_DMA, 1014 }; 1015