1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2e40095f6SMarek Vasut /*
3e40095f6SMarek Vasut * Atheros AR71xx / AR9xxx GMAC driver
4e40095f6SMarek Vasut *
5e40095f6SMarek Vasut * Copyright (C) 2016 Marek Vasut <marex@denx.de>
6e40095f6SMarek Vasut */
7e40095f6SMarek Vasut
8e40095f6SMarek Vasut #include <common.h>
9e40095f6SMarek Vasut #include <dm.h>
10e40095f6SMarek Vasut #include <errno.h>
11e40095f6SMarek Vasut #include <miiphy.h>
12e40095f6SMarek Vasut #include <malloc.h>
13e40095f6SMarek Vasut #include <linux/compiler.h>
14e40095f6SMarek Vasut #include <linux/err.h>
15e40095f6SMarek Vasut #include <linux/mii.h>
16e40095f6SMarek Vasut #include <wait_bit.h>
17e40095f6SMarek Vasut #include <asm/io.h>
18e40095f6SMarek Vasut
19e40095f6SMarek Vasut #include <mach/ath79.h>
20e40095f6SMarek Vasut
21e40095f6SMarek Vasut DECLARE_GLOBAL_DATA_PTR;
22e40095f6SMarek Vasut
23e40095f6SMarek Vasut enum ag7xxx_model {
24e40095f6SMarek Vasut AG7XXX_MODEL_AG933X,
25e40095f6SMarek Vasut AG7XXX_MODEL_AG934X,
26e40095f6SMarek Vasut };
27e40095f6SMarek Vasut
289240a2f5SJoe Hershberger /* MAC Configuration 1 */
29e40095f6SMarek Vasut #define AG7XXX_ETH_CFG1 0x00
30e40095f6SMarek Vasut #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
31e40095f6SMarek Vasut #define AG7XXX_ETH_CFG1_RX_RST BIT(19)
32e40095f6SMarek Vasut #define AG7XXX_ETH_CFG1_TX_RST BIT(18)
33e40095f6SMarek Vasut #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
34e40095f6SMarek Vasut #define AG7XXX_ETH_CFG1_RX_EN BIT(2)
35e40095f6SMarek Vasut #define AG7XXX_ETH_CFG1_TX_EN BIT(0)
36e40095f6SMarek Vasut
379240a2f5SJoe Hershberger /* MAC Configuration 2 */
38e40095f6SMarek Vasut #define AG7XXX_ETH_CFG2 0x04
39e40095f6SMarek Vasut #define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
40e40095f6SMarek Vasut #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
41e40095f6SMarek Vasut #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
42e40095f6SMarek Vasut #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
43e40095f6SMarek Vasut #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
44e40095f6SMarek Vasut #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
45e40095f6SMarek Vasut #define AG7XXX_ETH_CFG2_FDX BIT(0)
46e40095f6SMarek Vasut
479240a2f5SJoe Hershberger /* MII Configuration */
48e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_CFG 0x20
49e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
50e40095f6SMarek Vasut
519240a2f5SJoe Hershberger /* MII Command */
52e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_CMD 0x24
53e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
54e40095f6SMarek Vasut
559240a2f5SJoe Hershberger /* MII Address */
56e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
57e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
58e40095f6SMarek Vasut
599240a2f5SJoe Hershberger /* MII Control */
60e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
61e40095f6SMarek Vasut
629240a2f5SJoe Hershberger /* MII Status */
63e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_STATUS 0x30
64e40095f6SMarek Vasut
659240a2f5SJoe Hershberger /* MII Indicators */
66e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_IND 0x34
67e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
68e40095f6SMarek Vasut #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
69e40095f6SMarek Vasut
709240a2f5SJoe Hershberger /* STA Address 1 & 2 */
71e40095f6SMarek Vasut #define AG7XXX_ETH_ADDR1 0x40
72e40095f6SMarek Vasut #define AG7XXX_ETH_ADDR2 0x44
73e40095f6SMarek Vasut
749240a2f5SJoe Hershberger /* ETH Configuration 0 - 5 */
75e40095f6SMarek Vasut #define AG7XXX_ETH_FIFO_CFG_0 0x48
76e40095f6SMarek Vasut #define AG7XXX_ETH_FIFO_CFG_1 0x4c
77e40095f6SMarek Vasut #define AG7XXX_ETH_FIFO_CFG_2 0x50
78e40095f6SMarek Vasut #define AG7XXX_ETH_FIFO_CFG_3 0x54
79e40095f6SMarek Vasut #define AG7XXX_ETH_FIFO_CFG_4 0x58
80e40095f6SMarek Vasut #define AG7XXX_ETH_FIFO_CFG_5 0x5c
81e40095f6SMarek Vasut
829240a2f5SJoe Hershberger /* DMA Transfer Control for Queue 0 */
83e40095f6SMarek Vasut #define AG7XXX_ETH_DMA_TX_CTRL 0x180
84e40095f6SMarek Vasut #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
85e40095f6SMarek Vasut
869240a2f5SJoe Hershberger /* Descriptor Address for Queue 0 Tx */
87e40095f6SMarek Vasut #define AG7XXX_ETH_DMA_TX_DESC 0x184
88e40095f6SMarek Vasut
899240a2f5SJoe Hershberger /* DMA Tx Status */
90e40095f6SMarek Vasut #define AG7XXX_ETH_DMA_TX_STATUS 0x188
91e40095f6SMarek Vasut
929240a2f5SJoe Hershberger /* Rx Control */
93e40095f6SMarek Vasut #define AG7XXX_ETH_DMA_RX_CTRL 0x18c
94e40095f6SMarek Vasut #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
95e40095f6SMarek Vasut
969240a2f5SJoe Hershberger /* Pointer to Rx Descriptor */
97e40095f6SMarek Vasut #define AG7XXX_ETH_DMA_RX_DESC 0x190
98e40095f6SMarek Vasut
999240a2f5SJoe Hershberger /* Rx Status */
100e40095f6SMarek Vasut #define AG7XXX_ETH_DMA_RX_STATUS 0x194
101e40095f6SMarek Vasut
102e40095f6SMarek Vasut /* Custom register at 0x18070000 */
103e40095f6SMarek Vasut #define AG7XXX_GMAC_ETH_CFG 0x00
104e40095f6SMarek Vasut #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
105e40095f6SMarek Vasut #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
106e40095f6SMarek Vasut #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
107e40095f6SMarek Vasut #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
108e40095f6SMarek Vasut #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
109e40095f6SMarek Vasut #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
110e40095f6SMarek Vasut #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
111e40095f6SMarek Vasut #define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
112e40095f6SMarek Vasut #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
113e40095f6SMarek Vasut
114e40095f6SMarek Vasut #define CONFIG_TX_DESCR_NUM 8
115e40095f6SMarek Vasut #define CONFIG_RX_DESCR_NUM 8
116e40095f6SMarek Vasut #define CONFIG_ETH_BUFSIZE 2048
117e40095f6SMarek Vasut #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
118e40095f6SMarek Vasut #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
119e40095f6SMarek Vasut
120e40095f6SMarek Vasut /* DMA descriptor. */
121e40095f6SMarek Vasut struct ag7xxx_dma_desc {
122e40095f6SMarek Vasut u32 data_addr;
123e40095f6SMarek Vasut #define AG7XXX_DMADESC_IS_EMPTY BIT(31)
124e40095f6SMarek Vasut #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
125e40095f6SMarek Vasut #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
126e40095f6SMarek Vasut #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
127e40095f6SMarek Vasut u32 config;
128e40095f6SMarek Vasut u32 next_desc;
129e40095f6SMarek Vasut u32 _pad[5];
130e40095f6SMarek Vasut };
131e40095f6SMarek Vasut
132e40095f6SMarek Vasut struct ar7xxx_eth_priv {
133e40095f6SMarek Vasut struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
134e40095f6SMarek Vasut struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
135e40095f6SMarek Vasut char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
136e40095f6SMarek Vasut char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
137e40095f6SMarek Vasut
138e40095f6SMarek Vasut void __iomem *regs;
139e40095f6SMarek Vasut void __iomem *phyregs;
140e40095f6SMarek Vasut
141e40095f6SMarek Vasut struct eth_device *dev;
142e40095f6SMarek Vasut struct phy_device *phydev;
143e40095f6SMarek Vasut struct mii_dev *bus;
144e40095f6SMarek Vasut
145e40095f6SMarek Vasut u32 interface;
146e40095f6SMarek Vasut u32 tx_currdescnum;
147e40095f6SMarek Vasut u32 rx_currdescnum;
148e40095f6SMarek Vasut enum ag7xxx_model model;
149e40095f6SMarek Vasut };
150e40095f6SMarek Vasut
151e40095f6SMarek Vasut /*
152e40095f6SMarek Vasut * Switch and MDIO access
153e40095f6SMarek Vasut */
ag7xxx_switch_read(struct mii_dev * bus,int addr,int reg,u16 * val)154e40095f6SMarek Vasut static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
155e40095f6SMarek Vasut {
156e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = bus->priv;
157e40095f6SMarek Vasut void __iomem *regs = priv->phyregs;
158e40095f6SMarek Vasut int ret;
159e40095f6SMarek Vasut
160e40095f6SMarek Vasut writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
161e40095f6SMarek Vasut writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
162e40095f6SMarek Vasut regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
163e40095f6SMarek Vasut writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
164e40095f6SMarek Vasut regs + AG7XXX_ETH_MII_MGMT_CMD);
165e40095f6SMarek Vasut
16648263504SÁlvaro Fernández Rojas ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
167e40095f6SMarek Vasut AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
168e40095f6SMarek Vasut if (ret)
169e40095f6SMarek Vasut return ret;
170e40095f6SMarek Vasut
171e40095f6SMarek Vasut *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
172e40095f6SMarek Vasut writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
173e40095f6SMarek Vasut
174e40095f6SMarek Vasut return 0;
175e40095f6SMarek Vasut }
176e40095f6SMarek Vasut
ag7xxx_switch_write(struct mii_dev * bus,int addr,int reg,u16 val)177e40095f6SMarek Vasut static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
178e40095f6SMarek Vasut {
179e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = bus->priv;
180e40095f6SMarek Vasut void __iomem *regs = priv->phyregs;
181e40095f6SMarek Vasut int ret;
182e40095f6SMarek Vasut
183e40095f6SMarek Vasut writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
184e40095f6SMarek Vasut regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
185e40095f6SMarek Vasut writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
186e40095f6SMarek Vasut
18748263504SÁlvaro Fernández Rojas ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
188e40095f6SMarek Vasut AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
189e40095f6SMarek Vasut
190e40095f6SMarek Vasut return ret;
191e40095f6SMarek Vasut }
192e40095f6SMarek Vasut
ag7xxx_switch_reg_read(struct mii_dev * bus,int reg,u32 * val)193e40095f6SMarek Vasut static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
194e40095f6SMarek Vasut {
195e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = bus->priv;
196e40095f6SMarek Vasut u32 phy_addr;
197e40095f6SMarek Vasut u32 reg_addr;
198e40095f6SMarek Vasut u32 phy_temp;
199e40095f6SMarek Vasut u32 reg_temp;
200e40095f6SMarek Vasut u16 rv = 0;
201e40095f6SMarek Vasut int ret;
202e40095f6SMarek Vasut
203e40095f6SMarek Vasut if (priv->model == AG7XXX_MODEL_AG933X) {
204e40095f6SMarek Vasut phy_addr = 0x1f;
205e40095f6SMarek Vasut reg_addr = 0x10;
206e40095f6SMarek Vasut } else if (priv->model == AG7XXX_MODEL_AG934X) {
207e40095f6SMarek Vasut phy_addr = 0x18;
208e40095f6SMarek Vasut reg_addr = 0x00;
209e40095f6SMarek Vasut } else
210e40095f6SMarek Vasut return -EINVAL;
211e40095f6SMarek Vasut
212e40095f6SMarek Vasut ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
213e40095f6SMarek Vasut if (ret)
214e40095f6SMarek Vasut return ret;
215e40095f6SMarek Vasut
216e40095f6SMarek Vasut phy_temp = ((reg >> 6) & 0x7) | 0x10;
217e40095f6SMarek Vasut reg_temp = (reg >> 1) & 0x1e;
218e40095f6SMarek Vasut *val = 0;
219e40095f6SMarek Vasut
220e40095f6SMarek Vasut ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
221e40095f6SMarek Vasut if (ret < 0)
222e40095f6SMarek Vasut return ret;
223e40095f6SMarek Vasut *val |= rv;
224e40095f6SMarek Vasut
225e40095f6SMarek Vasut ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
226e40095f6SMarek Vasut if (ret < 0)
227e40095f6SMarek Vasut return ret;
228e40095f6SMarek Vasut *val |= (rv << 16);
229e40095f6SMarek Vasut
230e40095f6SMarek Vasut return 0;
231e40095f6SMarek Vasut }
232e40095f6SMarek Vasut
ag7xxx_switch_reg_write(struct mii_dev * bus,int reg,u32 val)233e40095f6SMarek Vasut static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
234e40095f6SMarek Vasut {
235e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = bus->priv;
236e40095f6SMarek Vasut u32 phy_addr;
237e40095f6SMarek Vasut u32 reg_addr;
238e40095f6SMarek Vasut u32 phy_temp;
239e40095f6SMarek Vasut u32 reg_temp;
240e40095f6SMarek Vasut int ret;
241e40095f6SMarek Vasut
242e40095f6SMarek Vasut if (priv->model == AG7XXX_MODEL_AG933X) {
243e40095f6SMarek Vasut phy_addr = 0x1f;
244e40095f6SMarek Vasut reg_addr = 0x10;
245e40095f6SMarek Vasut } else if (priv->model == AG7XXX_MODEL_AG934X) {
246e40095f6SMarek Vasut phy_addr = 0x18;
247e40095f6SMarek Vasut reg_addr = 0x00;
248e40095f6SMarek Vasut } else
249e40095f6SMarek Vasut return -EINVAL;
250e40095f6SMarek Vasut
251e40095f6SMarek Vasut ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
252e40095f6SMarek Vasut if (ret)
253e40095f6SMarek Vasut return ret;
254e40095f6SMarek Vasut
255e40095f6SMarek Vasut phy_temp = ((reg >> 6) & 0x7) | 0x10;
256e40095f6SMarek Vasut reg_temp = (reg >> 1) & 0x1e;
257e40095f6SMarek Vasut
258e40095f6SMarek Vasut /*
259e40095f6SMarek Vasut * The switch on AR933x has some special register behavior, which
260e40095f6SMarek Vasut * expects particular write order of their nibbles:
261e40095f6SMarek Vasut * 0x40 ..... MSB first, LSB second
262e40095f6SMarek Vasut * 0x50 ..... MSB first, LSB second
263e40095f6SMarek Vasut * 0x98 ..... LSB first, MSB second
264e40095f6SMarek Vasut * others ... don't care
265e40095f6SMarek Vasut */
266e40095f6SMarek Vasut if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
267e40095f6SMarek Vasut ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
268e40095f6SMarek Vasut if (ret < 0)
269e40095f6SMarek Vasut return ret;
270e40095f6SMarek Vasut
271e40095f6SMarek Vasut ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
272e40095f6SMarek Vasut if (ret < 0)
273e40095f6SMarek Vasut return ret;
274e40095f6SMarek Vasut } else {
275e40095f6SMarek Vasut ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
276e40095f6SMarek Vasut if (ret < 0)
277e40095f6SMarek Vasut return ret;
278e40095f6SMarek Vasut
279e40095f6SMarek Vasut ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
280e40095f6SMarek Vasut if (ret < 0)
281e40095f6SMarek Vasut return ret;
282e40095f6SMarek Vasut }
283e40095f6SMarek Vasut
284e40095f6SMarek Vasut return 0;
285e40095f6SMarek Vasut }
286e40095f6SMarek Vasut
ag7xxx_mdio_rw(struct mii_dev * bus,int addr,int reg,u32 val)2872fd519f7SJoe Hershberger static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
288e40095f6SMarek Vasut {
289e40095f6SMarek Vasut u32 data;
2902fd519f7SJoe Hershberger unsigned long start;
2912fd519f7SJoe Hershberger int ret;
2922fd519f7SJoe Hershberger /* No idea if this is long enough or too long */
2932fd519f7SJoe Hershberger int timeout_ms = 1000;
294e40095f6SMarek Vasut
295e40095f6SMarek Vasut /* Dummy read followed by PHY read/write command. */
2962fd519f7SJoe Hershberger ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
2972fd519f7SJoe Hershberger if (ret < 0)
2982fd519f7SJoe Hershberger return ret;
299e40095f6SMarek Vasut data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
3002fd519f7SJoe Hershberger ret = ag7xxx_switch_reg_write(bus, 0x98, data);
3012fd519f7SJoe Hershberger if (ret < 0)
3022fd519f7SJoe Hershberger return ret;
3032fd519f7SJoe Hershberger
3042fd519f7SJoe Hershberger start = get_timer(0);
305e40095f6SMarek Vasut
306e40095f6SMarek Vasut /* Wait for operation to finish */
307e40095f6SMarek Vasut do {
3082fd519f7SJoe Hershberger ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
3092fd519f7SJoe Hershberger if (ret < 0)
3102fd519f7SJoe Hershberger return ret;
3112fd519f7SJoe Hershberger
3122fd519f7SJoe Hershberger if (get_timer(start) > timeout_ms)
3132fd519f7SJoe Hershberger return -ETIMEDOUT;
314e40095f6SMarek Vasut } while (data & BIT(31));
315e40095f6SMarek Vasut
316e40095f6SMarek Vasut return data & 0xffff;
317e40095f6SMarek Vasut }
318e40095f6SMarek Vasut
ag7xxx_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)319e40095f6SMarek Vasut static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
320e40095f6SMarek Vasut {
321e40095f6SMarek Vasut return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
322e40095f6SMarek Vasut }
323e40095f6SMarek Vasut
ag7xxx_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)324e40095f6SMarek Vasut static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
325e40095f6SMarek Vasut u16 val)
326e40095f6SMarek Vasut {
3272fd519f7SJoe Hershberger int ret;
3282fd519f7SJoe Hershberger
3292fd519f7SJoe Hershberger ret = ag7xxx_mdio_rw(bus, addr, reg, val);
3302fd519f7SJoe Hershberger if (ret < 0)
3312fd519f7SJoe Hershberger return ret;
332e40095f6SMarek Vasut return 0;
333e40095f6SMarek Vasut }
334e40095f6SMarek Vasut
335e40095f6SMarek Vasut /*
336e40095f6SMarek Vasut * DMA ring handlers
337e40095f6SMarek Vasut */
ag7xxx_dma_clean_tx(struct udevice * dev)338e40095f6SMarek Vasut static void ag7xxx_dma_clean_tx(struct udevice *dev)
339e40095f6SMarek Vasut {
340e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
341e40095f6SMarek Vasut struct ag7xxx_dma_desc *curr, *next;
342e40095f6SMarek Vasut u32 start, end;
343e40095f6SMarek Vasut int i;
344e40095f6SMarek Vasut
345e40095f6SMarek Vasut for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
346e40095f6SMarek Vasut curr = &priv->tx_mac_descrtable[i];
347e40095f6SMarek Vasut next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
348e40095f6SMarek Vasut
349e40095f6SMarek Vasut curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
350e40095f6SMarek Vasut curr->config = AG7XXX_DMADESC_IS_EMPTY;
351e40095f6SMarek Vasut curr->next_desc = virt_to_phys(next);
352e40095f6SMarek Vasut }
353e40095f6SMarek Vasut
354e40095f6SMarek Vasut priv->tx_currdescnum = 0;
355e40095f6SMarek Vasut
356e40095f6SMarek Vasut /* Cache: Flush descriptors, don't care about buffers. */
357e40095f6SMarek Vasut start = (u32)(&priv->tx_mac_descrtable[0]);
358e40095f6SMarek Vasut end = start + sizeof(priv->tx_mac_descrtable);
359e40095f6SMarek Vasut flush_dcache_range(start, end);
360e40095f6SMarek Vasut }
361e40095f6SMarek Vasut
ag7xxx_dma_clean_rx(struct udevice * dev)362e40095f6SMarek Vasut static void ag7xxx_dma_clean_rx(struct udevice *dev)
363e40095f6SMarek Vasut {
364e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
365e40095f6SMarek Vasut struct ag7xxx_dma_desc *curr, *next;
366e40095f6SMarek Vasut u32 start, end;
367e40095f6SMarek Vasut int i;
368e40095f6SMarek Vasut
369e40095f6SMarek Vasut for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
370e40095f6SMarek Vasut curr = &priv->rx_mac_descrtable[i];
371e40095f6SMarek Vasut next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
372e40095f6SMarek Vasut
373e40095f6SMarek Vasut curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
374e40095f6SMarek Vasut curr->config = AG7XXX_DMADESC_IS_EMPTY;
375e40095f6SMarek Vasut curr->next_desc = virt_to_phys(next);
376e40095f6SMarek Vasut }
377e40095f6SMarek Vasut
378e40095f6SMarek Vasut priv->rx_currdescnum = 0;
379e40095f6SMarek Vasut
380e40095f6SMarek Vasut /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
381e40095f6SMarek Vasut start = (u32)(&priv->rx_mac_descrtable[0]);
382e40095f6SMarek Vasut end = start + sizeof(priv->rx_mac_descrtable);
383e40095f6SMarek Vasut flush_dcache_range(start, end);
384e40095f6SMarek Vasut invalidate_dcache_range(start, end);
385e40095f6SMarek Vasut
386e40095f6SMarek Vasut start = (u32)&priv->rxbuffs;
387e40095f6SMarek Vasut end = start + sizeof(priv->rxbuffs);
388e40095f6SMarek Vasut invalidate_dcache_range(start, end);
389e40095f6SMarek Vasut }
390e40095f6SMarek Vasut
391e40095f6SMarek Vasut /*
392e40095f6SMarek Vasut * Ethernet I/O
393e40095f6SMarek Vasut */
ag7xxx_eth_send(struct udevice * dev,void * packet,int length)394e40095f6SMarek Vasut static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
395e40095f6SMarek Vasut {
396e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
397e40095f6SMarek Vasut struct ag7xxx_dma_desc *curr;
398e40095f6SMarek Vasut u32 start, end;
399e40095f6SMarek Vasut
400e40095f6SMarek Vasut curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
401e40095f6SMarek Vasut
402e40095f6SMarek Vasut /* Cache: Invalidate descriptor. */
403e40095f6SMarek Vasut start = (u32)curr;
404e40095f6SMarek Vasut end = start + sizeof(*curr);
405e40095f6SMarek Vasut invalidate_dcache_range(start, end);
406e40095f6SMarek Vasut
407e40095f6SMarek Vasut if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
408e40095f6SMarek Vasut printf("ag7xxx: Out of TX DMA descriptors!\n");
409e40095f6SMarek Vasut return -EPERM;
410e40095f6SMarek Vasut }
411e40095f6SMarek Vasut
412e40095f6SMarek Vasut /* Copy the packet into the data buffer. */
413e40095f6SMarek Vasut memcpy(phys_to_virt(curr->data_addr), packet, length);
414e40095f6SMarek Vasut curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
415e40095f6SMarek Vasut
416e40095f6SMarek Vasut /* Cache: Flush descriptor, Flush buffer. */
417e40095f6SMarek Vasut start = (u32)curr;
418e40095f6SMarek Vasut end = start + sizeof(*curr);
419e40095f6SMarek Vasut flush_dcache_range(start, end);
420e40095f6SMarek Vasut start = (u32)phys_to_virt(curr->data_addr);
421e40095f6SMarek Vasut end = start + length;
422e40095f6SMarek Vasut flush_dcache_range(start, end);
423e40095f6SMarek Vasut
424e40095f6SMarek Vasut /* Load the DMA descriptor and start TX DMA. */
425e40095f6SMarek Vasut writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
426e40095f6SMarek Vasut priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
427e40095f6SMarek Vasut
428e40095f6SMarek Vasut /* Switch to next TX descriptor. */
429e40095f6SMarek Vasut priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
430e40095f6SMarek Vasut
431e40095f6SMarek Vasut return 0;
432e40095f6SMarek Vasut }
433e40095f6SMarek Vasut
ag7xxx_eth_recv(struct udevice * dev,int flags,uchar ** packetp)434e40095f6SMarek Vasut static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
435e40095f6SMarek Vasut {
436e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
437e40095f6SMarek Vasut struct ag7xxx_dma_desc *curr;
438e40095f6SMarek Vasut u32 start, end, length;
439e40095f6SMarek Vasut
440e40095f6SMarek Vasut curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
441e40095f6SMarek Vasut
442e40095f6SMarek Vasut /* Cache: Invalidate descriptor. */
443e40095f6SMarek Vasut start = (u32)curr;
444e40095f6SMarek Vasut end = start + sizeof(*curr);
445e40095f6SMarek Vasut invalidate_dcache_range(start, end);
446e40095f6SMarek Vasut
447e40095f6SMarek Vasut /* No packets received. */
448e40095f6SMarek Vasut if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
449e40095f6SMarek Vasut return -EAGAIN;
450e40095f6SMarek Vasut
451e40095f6SMarek Vasut length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
452e40095f6SMarek Vasut
453e40095f6SMarek Vasut /* Cache: Invalidate buffer. */
454e40095f6SMarek Vasut start = (u32)phys_to_virt(curr->data_addr);
455e40095f6SMarek Vasut end = start + length;
456e40095f6SMarek Vasut invalidate_dcache_range(start, end);
457e40095f6SMarek Vasut
458e40095f6SMarek Vasut /* Receive one packet and return length. */
459e40095f6SMarek Vasut *packetp = phys_to_virt(curr->data_addr);
460e40095f6SMarek Vasut return length;
461e40095f6SMarek Vasut }
462e40095f6SMarek Vasut
ag7xxx_eth_free_pkt(struct udevice * dev,uchar * packet,int length)463e40095f6SMarek Vasut static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
464e40095f6SMarek Vasut int length)
465e40095f6SMarek Vasut {
466e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
467e40095f6SMarek Vasut struct ag7xxx_dma_desc *curr;
468e40095f6SMarek Vasut u32 start, end;
469e40095f6SMarek Vasut
470e40095f6SMarek Vasut curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
471e40095f6SMarek Vasut
472e40095f6SMarek Vasut curr->config = AG7XXX_DMADESC_IS_EMPTY;
473e40095f6SMarek Vasut
474e40095f6SMarek Vasut /* Cache: Flush descriptor. */
475e40095f6SMarek Vasut start = (u32)curr;
476e40095f6SMarek Vasut end = start + sizeof(*curr);
477e40095f6SMarek Vasut flush_dcache_range(start, end);
478e40095f6SMarek Vasut
479e40095f6SMarek Vasut /* Switch to next RX descriptor. */
480e40095f6SMarek Vasut priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
481e40095f6SMarek Vasut
482e40095f6SMarek Vasut return 0;
483e40095f6SMarek Vasut }
484e40095f6SMarek Vasut
ag7xxx_eth_start(struct udevice * dev)485e40095f6SMarek Vasut static int ag7xxx_eth_start(struct udevice *dev)
486e40095f6SMarek Vasut {
487e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
488e40095f6SMarek Vasut
489e40095f6SMarek Vasut /* FIXME: Check if link up */
490e40095f6SMarek Vasut
491e40095f6SMarek Vasut /* Clear the DMA rings. */
492e40095f6SMarek Vasut ag7xxx_dma_clean_tx(dev);
493e40095f6SMarek Vasut ag7xxx_dma_clean_rx(dev);
494e40095f6SMarek Vasut
495e40095f6SMarek Vasut /* Load DMA descriptors and start the RX DMA. */
496e40095f6SMarek Vasut writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
497e40095f6SMarek Vasut priv->regs + AG7XXX_ETH_DMA_TX_DESC);
498e40095f6SMarek Vasut writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
499e40095f6SMarek Vasut priv->regs + AG7XXX_ETH_DMA_RX_DESC);
500e40095f6SMarek Vasut writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
501e40095f6SMarek Vasut priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
502e40095f6SMarek Vasut
503e40095f6SMarek Vasut return 0;
504e40095f6SMarek Vasut }
505e40095f6SMarek Vasut
ag7xxx_eth_stop(struct udevice * dev)506e40095f6SMarek Vasut static void ag7xxx_eth_stop(struct udevice *dev)
507e40095f6SMarek Vasut {
508e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
509e40095f6SMarek Vasut
510e40095f6SMarek Vasut /* Stop the TX DMA. */
511e40095f6SMarek Vasut writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
51248263504SÁlvaro Fernández Rojas wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
513e40095f6SMarek Vasut 1000, 0);
514e40095f6SMarek Vasut
515e40095f6SMarek Vasut /* Stop the RX DMA. */
516e40095f6SMarek Vasut writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
51748263504SÁlvaro Fernández Rojas wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
518e40095f6SMarek Vasut 1000, 0);
519e40095f6SMarek Vasut }
520e40095f6SMarek Vasut
521e40095f6SMarek Vasut /*
522e40095f6SMarek Vasut * Hardware setup
523e40095f6SMarek Vasut */
ag7xxx_eth_write_hwaddr(struct udevice * dev)524e40095f6SMarek Vasut static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
525e40095f6SMarek Vasut {
526e40095f6SMarek Vasut struct eth_pdata *pdata = dev_get_platdata(dev);
527e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
528e40095f6SMarek Vasut unsigned char *mac = pdata->enetaddr;
529e40095f6SMarek Vasut u32 macid_lo, macid_hi;
530e40095f6SMarek Vasut
531e40095f6SMarek Vasut macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
532e40095f6SMarek Vasut macid_lo = (mac[5] << 16) | (mac[4] << 24);
533e40095f6SMarek Vasut
534e40095f6SMarek Vasut writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
535e40095f6SMarek Vasut writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
536e40095f6SMarek Vasut
537e40095f6SMarek Vasut return 0;
538e40095f6SMarek Vasut }
539e40095f6SMarek Vasut
ag7xxx_hw_setup(struct udevice * dev)540e40095f6SMarek Vasut static void ag7xxx_hw_setup(struct udevice *dev)
541e40095f6SMarek Vasut {
542e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
543e40095f6SMarek Vasut u32 speed;
544e40095f6SMarek Vasut
545e40095f6SMarek Vasut setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
546e40095f6SMarek Vasut AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
547e40095f6SMarek Vasut AG7XXX_ETH_CFG1_SOFT_RST);
548e40095f6SMarek Vasut
549e40095f6SMarek Vasut mdelay(10);
550e40095f6SMarek Vasut
551e40095f6SMarek Vasut writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
552e40095f6SMarek Vasut priv->regs + AG7XXX_ETH_CFG1);
553e40095f6SMarek Vasut
554e40095f6SMarek Vasut if (priv->interface == PHY_INTERFACE_MODE_RMII)
555e40095f6SMarek Vasut speed = AG7XXX_ETH_CFG2_IF_10_100;
556e40095f6SMarek Vasut else
557e40095f6SMarek Vasut speed = AG7XXX_ETH_CFG2_IF_1000;
558e40095f6SMarek Vasut
559e40095f6SMarek Vasut clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
560e40095f6SMarek Vasut AG7XXX_ETH_CFG2_IF_SPEED_MASK,
561e40095f6SMarek Vasut speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
562e40095f6SMarek Vasut AG7XXX_ETH_CFG2_LEN_CHECK);
563e40095f6SMarek Vasut
564e40095f6SMarek Vasut writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
565e40095f6SMarek Vasut writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
566e40095f6SMarek Vasut
567e40095f6SMarek Vasut writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
568e40095f6SMarek Vasut setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
569e40095f6SMarek Vasut writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
570e40095f6SMarek Vasut writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
571e40095f6SMarek Vasut writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
572e40095f6SMarek Vasut writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
573e40095f6SMarek Vasut }
574e40095f6SMarek Vasut
ag7xxx_mii_get_div(void)575e40095f6SMarek Vasut static int ag7xxx_mii_get_div(void)
576e40095f6SMarek Vasut {
577e40095f6SMarek Vasut ulong freq = get_bus_freq(0);
578e40095f6SMarek Vasut
579e40095f6SMarek Vasut switch (freq / 1000000) {
580e40095f6SMarek Vasut case 150: return 0x7;
581e40095f6SMarek Vasut case 175: return 0x5;
582e40095f6SMarek Vasut case 200: return 0x4;
583e40095f6SMarek Vasut case 210: return 0x9;
584e40095f6SMarek Vasut case 220: return 0x9;
585e40095f6SMarek Vasut default: return 0x7;
586e40095f6SMarek Vasut }
587e40095f6SMarek Vasut }
588e40095f6SMarek Vasut
ag7xxx_mii_setup(struct udevice * dev)589e40095f6SMarek Vasut static int ag7xxx_mii_setup(struct udevice *dev)
590e40095f6SMarek Vasut {
591e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
592e40095f6SMarek Vasut int i, ret, div = ag7xxx_mii_get_div();
593e40095f6SMarek Vasut u32 reg;
594e40095f6SMarek Vasut
595e40095f6SMarek Vasut if (priv->model == AG7XXX_MODEL_AG933X) {
596e40095f6SMarek Vasut /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
597e40095f6SMarek Vasut if (priv->interface == PHY_INTERFACE_MODE_RMII)
598e40095f6SMarek Vasut return 0;
599e40095f6SMarek Vasut }
600e40095f6SMarek Vasut
601e40095f6SMarek Vasut if (priv->model == AG7XXX_MODEL_AG934X) {
602e40095f6SMarek Vasut writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | 0x4,
603e40095f6SMarek Vasut priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
604e40095f6SMarek Vasut writel(0x4, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
605e40095f6SMarek Vasut return 0;
606e40095f6SMarek Vasut }
607e40095f6SMarek Vasut
608e40095f6SMarek Vasut for (i = 0; i < 10; i++) {
609e40095f6SMarek Vasut writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
610e40095f6SMarek Vasut priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
611e40095f6SMarek Vasut writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
612e40095f6SMarek Vasut
613e40095f6SMarek Vasut /* Check the switch */
614e40095f6SMarek Vasut ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, ®);
615e40095f6SMarek Vasut if (ret)
616e40095f6SMarek Vasut continue;
617e40095f6SMarek Vasut
618e40095f6SMarek Vasut if (reg != 0x18007fff)
619e40095f6SMarek Vasut continue;
620e40095f6SMarek Vasut
621e40095f6SMarek Vasut return 0;
622e40095f6SMarek Vasut }
623e40095f6SMarek Vasut
624e40095f6SMarek Vasut return -EINVAL;
625e40095f6SMarek Vasut }
626e40095f6SMarek Vasut
ag933x_phy_setup_wan(struct udevice * dev)627e40095f6SMarek Vasut static int ag933x_phy_setup_wan(struct udevice *dev)
628e40095f6SMarek Vasut {
629e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
630e40095f6SMarek Vasut
631e40095f6SMarek Vasut /* Configure switch port 4 (GMAC0) */
632e40095f6SMarek Vasut return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
633e40095f6SMarek Vasut }
634e40095f6SMarek Vasut
ag933x_phy_setup_lan(struct udevice * dev)635e40095f6SMarek Vasut static int ag933x_phy_setup_lan(struct udevice *dev)
636e40095f6SMarek Vasut {
637e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
638e40095f6SMarek Vasut int i, ret;
639e40095f6SMarek Vasut u32 reg;
640e40095f6SMarek Vasut
641e40095f6SMarek Vasut /* Reset the switch */
642e40095f6SMarek Vasut ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
643e40095f6SMarek Vasut if (ret)
644e40095f6SMarek Vasut return ret;
645e40095f6SMarek Vasut reg |= BIT(31);
646e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
647e40095f6SMarek Vasut if (ret)
648e40095f6SMarek Vasut return ret;
649e40095f6SMarek Vasut
650e40095f6SMarek Vasut do {
651e40095f6SMarek Vasut ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
652e40095f6SMarek Vasut if (ret)
653e40095f6SMarek Vasut return ret;
654e40095f6SMarek Vasut } while (reg & BIT(31));
655e40095f6SMarek Vasut
656e40095f6SMarek Vasut /* Configure switch ports 0...3 (GMAC1) */
657e40095f6SMarek Vasut for (i = 0; i < 4; i++) {
658e40095f6SMarek Vasut ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
659e40095f6SMarek Vasut if (ret)
660e40095f6SMarek Vasut return ret;
661e40095f6SMarek Vasut }
662e40095f6SMarek Vasut
663e40095f6SMarek Vasut /* Enable CPU port */
664e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
665e40095f6SMarek Vasut if (ret)
666e40095f6SMarek Vasut return ret;
667e40095f6SMarek Vasut
668e40095f6SMarek Vasut for (i = 0; i < 4; i++) {
669e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
670e40095f6SMarek Vasut if (ret)
671e40095f6SMarek Vasut return ret;
672e40095f6SMarek Vasut }
673e40095f6SMarek Vasut
674e40095f6SMarek Vasut /* QM Control */
675e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
676e40095f6SMarek Vasut if (ret)
677e40095f6SMarek Vasut return ret;
678e40095f6SMarek Vasut
679e40095f6SMarek Vasut /* Disable Atheros header */
680e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
681e40095f6SMarek Vasut if (ret)
682e40095f6SMarek Vasut return ret;
683e40095f6SMarek Vasut
684e40095f6SMarek Vasut /* Tag priority mapping */
685e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
686e40095f6SMarek Vasut if (ret)
687e40095f6SMarek Vasut return ret;
688e40095f6SMarek Vasut
689e40095f6SMarek Vasut /* Enable ARP packets to the CPU */
690e40095f6SMarek Vasut ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, ®);
691e40095f6SMarek Vasut if (ret)
692e40095f6SMarek Vasut return ret;
693e40095f6SMarek Vasut reg |= 0x100000;
694e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
695e40095f6SMarek Vasut if (ret)
696e40095f6SMarek Vasut return ret;
697e40095f6SMarek Vasut
698e40095f6SMarek Vasut return 0;
699e40095f6SMarek Vasut }
700e40095f6SMarek Vasut
ag933x_phy_setup_reset_set(struct udevice * dev,int port)701e40095f6SMarek Vasut static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
702e40095f6SMarek Vasut {
703e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
704e40095f6SMarek Vasut int ret;
705e40095f6SMarek Vasut
706e40095f6SMarek Vasut ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
707e40095f6SMarek Vasut ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
708e40095f6SMarek Vasut ADVERTISE_PAUSE_ASYM);
709e40095f6SMarek Vasut if (ret)
710e40095f6SMarek Vasut return ret;
711e40095f6SMarek Vasut
712e40095f6SMarek Vasut if (priv->model == AG7XXX_MODEL_AG934X) {
713e40095f6SMarek Vasut ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
714e40095f6SMarek Vasut ADVERTISE_1000FULL);
715e40095f6SMarek Vasut if (ret)
716e40095f6SMarek Vasut return ret;
717e40095f6SMarek Vasut }
718e40095f6SMarek Vasut
719e40095f6SMarek Vasut return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
720e40095f6SMarek Vasut BMCR_ANENABLE | BMCR_RESET);
721e40095f6SMarek Vasut }
722e40095f6SMarek Vasut
ag933x_phy_setup_reset_fin(struct udevice * dev,int port)723e40095f6SMarek Vasut static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
724e40095f6SMarek Vasut {
725e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
726e40095f6SMarek Vasut int ret;
727e40095f6SMarek Vasut
728e40095f6SMarek Vasut do {
729e40095f6SMarek Vasut ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
730e40095f6SMarek Vasut if (ret < 0)
731e40095f6SMarek Vasut return ret;
732e40095f6SMarek Vasut mdelay(10);
733e40095f6SMarek Vasut } while (ret & BMCR_RESET);
734e40095f6SMarek Vasut
735e40095f6SMarek Vasut return 0;
736e40095f6SMarek Vasut }
737e40095f6SMarek Vasut
ag933x_phy_setup_common(struct udevice * dev)738e40095f6SMarek Vasut static int ag933x_phy_setup_common(struct udevice *dev)
739e40095f6SMarek Vasut {
740e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
741e40095f6SMarek Vasut int i, ret, phymax;
742e40095f6SMarek Vasut
743e40095f6SMarek Vasut if (priv->model == AG7XXX_MODEL_AG933X)
744e40095f6SMarek Vasut phymax = 4;
745e40095f6SMarek Vasut else if (priv->model == AG7XXX_MODEL_AG934X)
746e40095f6SMarek Vasut phymax = 5;
747e40095f6SMarek Vasut else
748e40095f6SMarek Vasut return -EINVAL;
749e40095f6SMarek Vasut
750e40095f6SMarek Vasut if (priv->interface == PHY_INTERFACE_MODE_RMII) {
751e40095f6SMarek Vasut ret = ag933x_phy_setup_reset_set(dev, phymax);
752e40095f6SMarek Vasut if (ret)
753e40095f6SMarek Vasut return ret;
754e40095f6SMarek Vasut
755e40095f6SMarek Vasut ret = ag933x_phy_setup_reset_fin(dev, phymax);
756e40095f6SMarek Vasut if (ret)
757e40095f6SMarek Vasut return ret;
758e40095f6SMarek Vasut
759e40095f6SMarek Vasut /* Read out link status */
760e40095f6SMarek Vasut ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
761e40095f6SMarek Vasut if (ret < 0)
762e40095f6SMarek Vasut return ret;
763e40095f6SMarek Vasut
764e40095f6SMarek Vasut return 0;
765e40095f6SMarek Vasut }
766e40095f6SMarek Vasut
767e40095f6SMarek Vasut /* Switch ports */
768e40095f6SMarek Vasut for (i = 0; i < phymax; i++) {
769e40095f6SMarek Vasut ret = ag933x_phy_setup_reset_set(dev, i);
770e40095f6SMarek Vasut if (ret)
771e40095f6SMarek Vasut return ret;
772e40095f6SMarek Vasut }
773e40095f6SMarek Vasut
774e40095f6SMarek Vasut for (i = 0; i < phymax; i++) {
775e40095f6SMarek Vasut ret = ag933x_phy_setup_reset_fin(dev, i);
776e40095f6SMarek Vasut if (ret)
777e40095f6SMarek Vasut return ret;
778e40095f6SMarek Vasut }
779e40095f6SMarek Vasut
780e40095f6SMarek Vasut for (i = 0; i < phymax; i++) {
781e40095f6SMarek Vasut /* Read out link status */
782e40095f6SMarek Vasut ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
783e40095f6SMarek Vasut if (ret < 0)
784e40095f6SMarek Vasut return ret;
785e40095f6SMarek Vasut }
786e40095f6SMarek Vasut
787e40095f6SMarek Vasut return 0;
788e40095f6SMarek Vasut }
789e40095f6SMarek Vasut
ag934x_phy_setup(struct udevice * dev)790e40095f6SMarek Vasut static int ag934x_phy_setup(struct udevice *dev)
791e40095f6SMarek Vasut {
792e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
793e40095f6SMarek Vasut int i, ret;
794e40095f6SMarek Vasut u32 reg;
795e40095f6SMarek Vasut
796e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
797e40095f6SMarek Vasut if (ret)
798e40095f6SMarek Vasut return ret;
799e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
800e40095f6SMarek Vasut if (ret)
801e40095f6SMarek Vasut return ret;
802e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
803e40095f6SMarek Vasut if (ret)
804e40095f6SMarek Vasut return ret;
805e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
806e40095f6SMarek Vasut if (ret)
807e40095f6SMarek Vasut return ret;
808e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
809e40095f6SMarek Vasut if (ret)
810e40095f6SMarek Vasut return ret;
811e40095f6SMarek Vasut
812e40095f6SMarek Vasut /* AR8327/AR8328 v1.0 fixup */
813e40095f6SMarek Vasut ret = ag7xxx_switch_reg_read(priv->bus, 0, ®);
814e40095f6SMarek Vasut if (ret)
815e40095f6SMarek Vasut return ret;
816e40095f6SMarek Vasut if ((reg & 0xffff) == 0x1201) {
817e40095f6SMarek Vasut for (i = 0; i < 5; i++) {
818e40095f6SMarek Vasut ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
819e40095f6SMarek Vasut if (ret)
820e40095f6SMarek Vasut return ret;
821e40095f6SMarek Vasut ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
822e40095f6SMarek Vasut if (ret)
823e40095f6SMarek Vasut return ret;
824e40095f6SMarek Vasut ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
825e40095f6SMarek Vasut if (ret)
826e40095f6SMarek Vasut return ret;
827e40095f6SMarek Vasut ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
828e40095f6SMarek Vasut if (ret)
829e40095f6SMarek Vasut return ret;
830e40095f6SMarek Vasut }
831e40095f6SMarek Vasut }
832e40095f6SMarek Vasut
833e40095f6SMarek Vasut ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, ®);
834e40095f6SMarek Vasut if (ret)
835e40095f6SMarek Vasut return ret;
836e40095f6SMarek Vasut reg &= ~0x70000;
837e40095f6SMarek Vasut ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
838e40095f6SMarek Vasut if (ret)
839e40095f6SMarek Vasut return ret;
840e40095f6SMarek Vasut
841e40095f6SMarek Vasut return 0;
842e40095f6SMarek Vasut }
843e40095f6SMarek Vasut
ag7xxx_mac_probe(struct udevice * dev)844e40095f6SMarek Vasut static int ag7xxx_mac_probe(struct udevice *dev)
845e40095f6SMarek Vasut {
846e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
847e40095f6SMarek Vasut int ret;
848e40095f6SMarek Vasut
849e40095f6SMarek Vasut ag7xxx_hw_setup(dev);
850e40095f6SMarek Vasut ret = ag7xxx_mii_setup(dev);
851e40095f6SMarek Vasut if (ret)
852e40095f6SMarek Vasut return ret;
853e40095f6SMarek Vasut
854e40095f6SMarek Vasut ag7xxx_eth_write_hwaddr(dev);
855e40095f6SMarek Vasut
856e40095f6SMarek Vasut if (priv->model == AG7XXX_MODEL_AG933X) {
857e40095f6SMarek Vasut if (priv->interface == PHY_INTERFACE_MODE_RMII)
858e40095f6SMarek Vasut ret = ag933x_phy_setup_wan(dev);
859e40095f6SMarek Vasut else
860e40095f6SMarek Vasut ret = ag933x_phy_setup_lan(dev);
861e40095f6SMarek Vasut } else if (priv->model == AG7XXX_MODEL_AG934X) {
862e40095f6SMarek Vasut ret = ag934x_phy_setup(dev);
863e40095f6SMarek Vasut } else {
864e40095f6SMarek Vasut return -EINVAL;
865e40095f6SMarek Vasut }
866e40095f6SMarek Vasut
867e40095f6SMarek Vasut if (ret)
868e40095f6SMarek Vasut return ret;
869e40095f6SMarek Vasut
870e40095f6SMarek Vasut return ag933x_phy_setup_common(dev);
871e40095f6SMarek Vasut }
872e40095f6SMarek Vasut
ag7xxx_mdio_probe(struct udevice * dev)873e40095f6SMarek Vasut static int ag7xxx_mdio_probe(struct udevice *dev)
874e40095f6SMarek Vasut {
875e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
876e40095f6SMarek Vasut struct mii_dev *bus = mdio_alloc();
877e40095f6SMarek Vasut
878e40095f6SMarek Vasut if (!bus)
879e40095f6SMarek Vasut return -ENOMEM;
880e40095f6SMarek Vasut
881e40095f6SMarek Vasut bus->read = ag7xxx_mdio_read;
882e40095f6SMarek Vasut bus->write = ag7xxx_mdio_write;
883e40095f6SMarek Vasut snprintf(bus->name, sizeof(bus->name), dev->name);
884e40095f6SMarek Vasut
885e40095f6SMarek Vasut bus->priv = (void *)priv;
886e40095f6SMarek Vasut
887e40095f6SMarek Vasut return mdio_register(bus);
888e40095f6SMarek Vasut }
889e40095f6SMarek Vasut
ag7xxx_get_phy_iface_offset(struct udevice * dev)890e40095f6SMarek Vasut static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
891e40095f6SMarek Vasut {
892e40095f6SMarek Vasut int offset;
893e40095f6SMarek Vasut
894e160f7d4SSimon Glass offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy");
895e40095f6SMarek Vasut if (offset <= 0) {
896e40095f6SMarek Vasut debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
897e40095f6SMarek Vasut return -EINVAL;
898e40095f6SMarek Vasut }
899e40095f6SMarek Vasut
900e40095f6SMarek Vasut offset = fdt_parent_offset(gd->fdt_blob, offset);
901e40095f6SMarek Vasut if (offset <= 0) {
902e40095f6SMarek Vasut debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
903e40095f6SMarek Vasut __func__, offset);
904e40095f6SMarek Vasut return -EINVAL;
905e40095f6SMarek Vasut }
906e40095f6SMarek Vasut
907e40095f6SMarek Vasut offset = fdt_parent_offset(gd->fdt_blob, offset);
908e40095f6SMarek Vasut if (offset <= 0) {
909e40095f6SMarek Vasut debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
910e40095f6SMarek Vasut __func__, offset);
911e40095f6SMarek Vasut return -EINVAL;
912e40095f6SMarek Vasut }
913e40095f6SMarek Vasut
914e40095f6SMarek Vasut return offset;
915e40095f6SMarek Vasut }
916e40095f6SMarek Vasut
ag7xxx_eth_probe(struct udevice * dev)917e40095f6SMarek Vasut static int ag7xxx_eth_probe(struct udevice *dev)
918e40095f6SMarek Vasut {
919e40095f6SMarek Vasut struct eth_pdata *pdata = dev_get_platdata(dev);
920e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
921e40095f6SMarek Vasut void __iomem *iobase, *phyiobase;
922e40095f6SMarek Vasut int ret, phyreg;
923e40095f6SMarek Vasut
924e40095f6SMarek Vasut /* Decoding of convoluted PHY wiring on Atheros MIPS. */
925e40095f6SMarek Vasut ret = ag7xxx_get_phy_iface_offset(dev);
926e40095f6SMarek Vasut if (ret <= 0)
927e40095f6SMarek Vasut return ret;
928e40095f6SMarek Vasut phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
929e40095f6SMarek Vasut
930e40095f6SMarek Vasut iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
931e40095f6SMarek Vasut phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
932e40095f6SMarek Vasut
933e40095f6SMarek Vasut debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
934e40095f6SMarek Vasut __func__, iobase, phyiobase, priv);
935e40095f6SMarek Vasut priv->regs = iobase;
936e40095f6SMarek Vasut priv->phyregs = phyiobase;
937e40095f6SMarek Vasut priv->interface = pdata->phy_interface;
938e40095f6SMarek Vasut priv->model = dev_get_driver_data(dev);
939e40095f6SMarek Vasut
940e40095f6SMarek Vasut ret = ag7xxx_mdio_probe(dev);
941e40095f6SMarek Vasut if (ret)
942e40095f6SMarek Vasut return ret;
943e40095f6SMarek Vasut
944e40095f6SMarek Vasut priv->bus = miiphy_get_dev_by_name(dev->name);
945e40095f6SMarek Vasut
946e40095f6SMarek Vasut ret = ag7xxx_mac_probe(dev);
947e40095f6SMarek Vasut debug("%s, ret=%d\n", __func__, ret);
948e40095f6SMarek Vasut
949e40095f6SMarek Vasut return ret;
950e40095f6SMarek Vasut }
951e40095f6SMarek Vasut
ag7xxx_eth_remove(struct udevice * dev)952e40095f6SMarek Vasut static int ag7xxx_eth_remove(struct udevice *dev)
953e40095f6SMarek Vasut {
954e40095f6SMarek Vasut struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
955e40095f6SMarek Vasut
956e40095f6SMarek Vasut free(priv->phydev);
957e40095f6SMarek Vasut mdio_unregister(priv->bus);
958e40095f6SMarek Vasut mdio_free(priv->bus);
959e40095f6SMarek Vasut
960e40095f6SMarek Vasut return 0;
961e40095f6SMarek Vasut }
962e40095f6SMarek Vasut
963e40095f6SMarek Vasut static const struct eth_ops ag7xxx_eth_ops = {
964e40095f6SMarek Vasut .start = ag7xxx_eth_start,
965e40095f6SMarek Vasut .send = ag7xxx_eth_send,
966e40095f6SMarek Vasut .recv = ag7xxx_eth_recv,
967e40095f6SMarek Vasut .free_pkt = ag7xxx_eth_free_pkt,
968e40095f6SMarek Vasut .stop = ag7xxx_eth_stop,
969e40095f6SMarek Vasut .write_hwaddr = ag7xxx_eth_write_hwaddr,
970e40095f6SMarek Vasut };
971e40095f6SMarek Vasut
ag7xxx_eth_ofdata_to_platdata(struct udevice * dev)972e40095f6SMarek Vasut static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev)
973e40095f6SMarek Vasut {
974e40095f6SMarek Vasut struct eth_pdata *pdata = dev_get_platdata(dev);
975e40095f6SMarek Vasut const char *phy_mode;
976e40095f6SMarek Vasut int ret;
977e40095f6SMarek Vasut
978a821c4afSSimon Glass pdata->iobase = devfdt_get_addr(dev);
979e40095f6SMarek Vasut pdata->phy_interface = -1;
980e40095f6SMarek Vasut
981e40095f6SMarek Vasut /* Decoding of convoluted PHY wiring on Atheros MIPS. */
982e40095f6SMarek Vasut ret = ag7xxx_get_phy_iface_offset(dev);
983e40095f6SMarek Vasut if (ret <= 0)
984e40095f6SMarek Vasut return ret;
985e40095f6SMarek Vasut
986e40095f6SMarek Vasut phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
987e40095f6SMarek Vasut if (phy_mode)
988e40095f6SMarek Vasut pdata->phy_interface = phy_get_interface_by_name(phy_mode);
989e40095f6SMarek Vasut if (pdata->phy_interface == -1) {
990e40095f6SMarek Vasut debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
991e40095f6SMarek Vasut return -EINVAL;
992e40095f6SMarek Vasut }
993e40095f6SMarek Vasut
994e40095f6SMarek Vasut return 0;
995e40095f6SMarek Vasut }
996e40095f6SMarek Vasut
997e40095f6SMarek Vasut static const struct udevice_id ag7xxx_eth_ids[] = {
998e40095f6SMarek Vasut { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
999e40095f6SMarek Vasut { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
1000e40095f6SMarek Vasut { }
1001e40095f6SMarek Vasut };
1002e40095f6SMarek Vasut
1003e40095f6SMarek Vasut U_BOOT_DRIVER(eth_ag7xxx) = {
1004e40095f6SMarek Vasut .name = "eth_ag7xxx",
1005e40095f6SMarek Vasut .id = UCLASS_ETH,
1006e40095f6SMarek Vasut .of_match = ag7xxx_eth_ids,
1007e40095f6SMarek Vasut .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata,
1008e40095f6SMarek Vasut .probe = ag7xxx_eth_probe,
1009e40095f6SMarek Vasut .remove = ag7xxx_eth_remove,
1010e40095f6SMarek Vasut .ops = &ag7xxx_eth_ops,
1011e40095f6SMarek Vasut .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv),
1012e40095f6SMarek Vasut .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1013e40095f6SMarek Vasut .flags = DM_FLAG_ALLOC_PRIV_DMA,
1014e40095f6SMarek Vasut };
1015