1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * SPI flash internal definitions 4 * 5 * Copyright (C) 2008 Atmel Corporation 6 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 7 */ 8 9 #ifndef _SF_INTERNAL_H_ 10 #define _SF_INTERNAL_H_ 11 12 #include <linux/types.h> 13 #include <linux/compiler.h> 14 15 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ 16 enum spi_dual_flash { 17 SF_SINGLE_FLASH = 0, 18 SF_DUAL_STACKED_FLASH = BIT(0), 19 SF_DUAL_PARALLEL_FLASH = BIT(1), 20 }; 21 22 enum spi_nor_option_flags { 23 SNOR_F_SST_WR = BIT(0), 24 SNOR_F_USE_FSR = BIT(1), 25 SNOR_F_USE_UPAGE = BIT(3), 26 }; 27 28 #define SPI_FLASH_3B_ADDR_LEN 3 29 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) 30 #define SPI_FLASH_16MB_BOUN 0x1000000 31 32 /* CFI Manufacture ID's */ 33 #define SPI_FLASH_CFI_MFR_SPANSION 0x01 34 #define SPI_FLASH_CFI_MFR_STMICRO 0x20 35 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 36 #define SPI_FLASH_CFI_MFR_SST 0xbf 37 #define SPI_FLASH_CFI_MFR_WINBOND 0xef 38 #define SPI_FLASH_CFI_MFR_ATMEL 0x1f 39 40 /* Erase commands */ 41 #define CMD_ERASE_4K 0x20 42 #define CMD_ERASE_CHIP 0xc7 43 #define CMD_ERASE_64K 0xd8 44 45 /* Write commands */ 46 #define CMD_WRITE_STATUS 0x01 47 #define CMD_PAGE_PROGRAM 0x02 48 #define CMD_WRITE_DISABLE 0x04 49 #define CMD_WRITE_ENABLE 0x06 50 #define CMD_QUAD_PAGE_PROGRAM 0x32 51 52 /* Read commands */ 53 #define CMD_READ_ARRAY_SLOW 0x03 54 #define CMD_READ_ARRAY_FAST 0x0b 55 #define CMD_READ_DUAL_OUTPUT_FAST 0x3b 56 #define CMD_READ_DUAL_IO_FAST 0xbb 57 #define CMD_READ_QUAD_OUTPUT_FAST 0x6b 58 #define CMD_READ_QUAD_IO_FAST 0xeb 59 #define CMD_READ_ID 0x9f 60 #define CMD_READ_STATUS 0x05 61 #define CMD_READ_STATUS1 0x35 62 #define CMD_READ_CONFIG 0x35 63 #define CMD_FLAG_STATUS 0x70 64 65 /* Bank addr access commands */ 66 #ifdef CONFIG_SPI_FLASH_BAR 67 # define CMD_BANKADDR_BRWR 0x17 68 # define CMD_BANKADDR_BRRD 0x16 69 # define CMD_EXTNADDR_WREAR 0xC5 70 # define CMD_EXTNADDR_RDEAR 0xC8 71 #endif 72 73 /* Common status */ 74 #define STATUS_WIP BIT(0) 75 #define STATUS_QEB_WINSPAN BIT(1) 76 #define STATUS_QEB_MXIC BIT(6) 77 #define STATUS_PEC BIT(7) 78 #define SR_BP0 BIT(2) /* Block protect 0 */ 79 #define SR_BP1 BIT(3) /* Block protect 1 */ 80 #define SR_BP2 BIT(4) /* Block protect 2 */ 81 82 /* Flash timeout values */ 83 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) 84 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) 85 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) 86 87 /* SST specific */ 88 #ifdef CONFIG_SPI_FLASH_SST 89 #define SST26_CMD_READ_BPR 0x72 90 #define SST26_CMD_WRITE_BPR 0x42 91 92 #define SST26_BPR_8K_NUM 4 93 #define SST26_MAX_BPR_REG_LEN (18 + 1) 94 #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K) 95 96 enum lock_ctl { 97 SST26_CTL_LOCK, 98 SST26_CTL_UNLOCK, 99 SST26_CTL_CHECK 100 }; 101 102 # define CMD_SST_BP 0x02 /* Byte Program */ 103 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ 104 105 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 106 const void *buf); 107 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 108 const void *buf); 109 #endif 110 111 #define JEDEC_MFR(info) ((info)->id[0]) 112 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2])) 113 #define JEDEC_EXT(info) (((info)->id[3]) << 8 | ((info)->id[4])) 114 #define SPI_FLASH_MAX_ID_LEN 6 115 116 struct spi_flash_info { 117 /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */ 118 const char *name; 119 120 /* 121 * This array stores the ID bytes. 122 * The first three bytes are the JEDIC ID. 123 * JEDEC ID zero means "no ID" (mostly older chips). 124 */ 125 u8 id[SPI_FLASH_MAX_ID_LEN]; 126 u8 id_len; 127 128 /* 129 * The size listed here is what works with SPINOR_OP_SE, which isn't 130 * necessarily called a "sector" by the vendor. 131 */ 132 u32 sector_size; 133 u32 n_sectors; 134 135 u16 page_size; 136 137 u16 flags; 138 #define SECT_4K BIT(0) /* CMD_ERASE_4K works uniformly */ 139 #define E_FSR BIT(1) /* use flag status register for */ 140 #define SST_WR BIT(2) /* use SST byte/word programming */ 141 #define WR_QPP BIT(3) /* use Quad Page Program */ 142 #define RD_QUAD BIT(4) /* use Quad Read */ 143 #define RD_DUAL BIT(5) /* use Dual Read */ 144 #define RD_QUADIO BIT(6) /* use Quad IO Read */ 145 #define RD_DUALIO BIT(7) /* use Dual IO Read */ 146 #define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO) 147 }; 148 149 extern const struct spi_flash_info spi_flash_ids[]; 150 151 /* Send a single-byte command to the device and read the response */ 152 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 153 154 /* 155 * Send a multi-byte command to the device and read the response. Used 156 * for flash array reads, etc. 157 */ 158 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 159 size_t cmd_len, void *data, size_t data_len); 160 161 /* 162 * Send a multi-byte command to the device followed by (optional) 163 * data. Used for programming the flash array, etc. 164 */ 165 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 166 const void *data, size_t data_len); 167 168 169 /* Flash erase(sectors) operation, support all possible erase commands */ 170 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); 171 172 /* Lock stmicro spi flash region */ 173 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len); 174 175 /* Unlock stmicro spi flash region */ 176 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len); 177 178 /* Check if a stmicro spi flash region is completely locked */ 179 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len); 180 181 /* Enable writing on the SPI flash */ 182 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) 183 { 184 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); 185 } 186 187 /* Disable writing on the SPI flash */ 188 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) 189 { 190 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); 191 } 192 193 /* 194 * Used for spi_flash write operation 195 * - SPI claim 196 * - spi_flash_cmd_write_enable 197 * - spi_flash_cmd_write 198 * - spi_flash_wait_till_ready 199 * - SPI release 200 */ 201 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 202 size_t cmd_len, const void *buf, size_t buf_len); 203 204 /* 205 * Flash write operation, support all possible write commands. 206 * Write the requested data out breaking it up into multiple write 207 * commands as needed per the write size. 208 */ 209 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 210 size_t len, const void *buf); 211 212 /* 213 * Same as spi_flash_cmd_read() except it also claims/releases the SPI 214 * bus. Used as common part of the ->read() operation. 215 */ 216 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 217 size_t cmd_len, void *data, size_t data_len); 218 219 /* Flash read operation, support all possible read commands */ 220 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 221 size_t len, void *data); 222 223 #ifdef CONFIG_SPI_FLASH_MTD 224 int spi_flash_mtd_register(struct spi_flash *flash); 225 void spi_flash_mtd_unregister(void); 226 #endif 227 228 /** 229 * spi_flash_scan - scan the SPI FLASH 230 * @flash: the spi flash structure 231 * 232 * The drivers can use this fuction to scan the SPI FLASH. 233 * In the scanning, it will try to get all the necessary information to 234 * fill the spi_flash{}. 235 * 236 * Return: 0 for success, others for failure. 237 */ 238 int spi_flash_scan(struct spi_flash *flash); 239 240 #endif /* _SF_INTERNAL_H_ */ 241