1 /* 2 * SPI flash internal definitions 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _SF_INTERNAL_H_ 11 #define _SF_INTERNAL_H_ 12 13 #include <linux/types.h> 14 #include <linux/compiler.h> 15 16 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ 17 enum spi_dual_flash { 18 SF_SINGLE_FLASH = 0, 19 SF_DUAL_STACKED_FLASH = 1 << 0, 20 SF_DUAL_PARALLEL_FLASH = 1 << 1, 21 }; 22 23 /* Enum list - Full read commands */ 24 enum spi_read_cmds { 25 ARRAY_SLOW = 1 << 0, 26 ARRAY_FAST = 1 << 1, 27 DUAL_OUTPUT_FAST = 1 << 2, 28 DUAL_IO_FAST = 1 << 3, 29 QUAD_OUTPUT_FAST = 1 << 4, 30 QUAD_IO_FAST = 1 << 5, 31 }; 32 33 /* Normal - Extended - Full command set */ 34 #define RD_NORM (ARRAY_SLOW | ARRAY_FAST) 35 #define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) 36 #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST) 37 38 /* sf param flags */ 39 enum { 40 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 41 SECT_4K = 1 << 0, 42 #else 43 SECT_4K = 0 << 0, 44 #endif 45 SECT_32K = 1 << 1, 46 E_FSR = 1 << 2, 47 SST_BP = 1 << 3, 48 SST_WP = 1 << 4, 49 WR_QPP = 1 << 5, 50 }; 51 52 #define SST_WR (SST_BP | SST_WP) 53 54 #define SPI_FLASH_3B_ADDR_LEN 3 55 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) 56 #define SPI_FLASH_16MB_BOUN 0x1000000 57 58 /* CFI Manufacture ID's */ 59 #define SPI_FLASH_CFI_MFR_SPANSION 0x01 60 #define SPI_FLASH_CFI_MFR_STMICRO 0x20 61 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 62 #define SPI_FLASH_CFI_MFR_WINBOND 0xef 63 64 /* Erase commands */ 65 #define CMD_ERASE_4K 0x20 66 #define CMD_ERASE_32K 0x52 67 #define CMD_ERASE_CHIP 0xc7 68 #define CMD_ERASE_64K 0xd8 69 70 /* Write commands */ 71 #define CMD_WRITE_STATUS 0x01 72 #define CMD_PAGE_PROGRAM 0x02 73 #define CMD_WRITE_DISABLE 0x04 74 #define CMD_READ_STATUS 0x05 75 #define CMD_QUAD_PAGE_PROGRAM 0x32 76 #define CMD_READ_STATUS1 0x35 77 #define CMD_WRITE_ENABLE 0x06 78 #define CMD_READ_CONFIG 0x35 79 #define CMD_FLAG_STATUS 0x70 80 81 /* Read commands */ 82 #define CMD_READ_ARRAY_SLOW 0x03 83 #define CMD_READ_ARRAY_FAST 0x0b 84 #define CMD_READ_DUAL_OUTPUT_FAST 0x3b 85 #define CMD_READ_DUAL_IO_FAST 0xbb 86 #define CMD_READ_QUAD_OUTPUT_FAST 0x6b 87 #define CMD_READ_QUAD_IO_FAST 0xeb 88 #define CMD_READ_ID 0x9f 89 90 /* Bank addr access commands */ 91 #ifdef CONFIG_SPI_FLASH_BAR 92 # define CMD_BANKADDR_BRWR 0x17 93 # define CMD_BANKADDR_BRRD 0x16 94 # define CMD_EXTNADDR_WREAR 0xC5 95 # define CMD_EXTNADDR_RDEAR 0xC8 96 #endif 97 98 /* Common status */ 99 #define STATUS_WIP (1 << 0) 100 #define STATUS_QEB_WINSPAN (1 << 1) 101 #define STATUS_QEB_MXIC (1 << 6) 102 #define STATUS_PEC (1 << 7) 103 104 /* Flash timeout values */ 105 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) 106 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) 107 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) 108 109 /* SST specific */ 110 #ifdef CONFIG_SPI_FLASH_SST 111 # define CMD_SST_BP 0x02 /* Byte Program */ 112 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ 113 114 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 115 const void *buf); 116 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 117 const void *buf); 118 #endif 119 120 /** 121 * struct spi_flash_params - SPI/QSPI flash device params structure 122 * 123 * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) 124 * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) 125 * @ext_jedec: Device ext_jedec ID 126 * @sector_size: Isn't necessarily a sector size from vendor, 127 * the size listed here is what works with CMD_ERASE_64K 128 * @nr_sectors: No.of sectors on this device 129 * @e_rd_cmd: Enum list for read commands 130 * @flags: Important param, for flash specific behaviour 131 */ 132 struct spi_flash_params { 133 const char *name; 134 u32 jedec; 135 u16 ext_jedec; 136 u32 sector_size; 137 u32 nr_sectors; 138 u8 e_rd_cmd; 139 u16 flags; 140 }; 141 142 extern const struct spi_flash_params spi_flash_params_table[]; 143 144 /* Send a single-byte command to the device and read the response */ 145 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 146 147 /* 148 * Send a multi-byte command to the device and read the response. Used 149 * for flash array reads, etc. 150 */ 151 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 152 size_t cmd_len, void *data, size_t data_len); 153 154 /* 155 * Send a multi-byte command to the device followed by (optional) 156 * data. Used for programming the flash array, etc. 157 */ 158 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 159 const void *data, size_t data_len); 160 161 162 /* Flash erase(sectors) operation, support all possible erase commands */ 163 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); 164 165 /* Read the status register */ 166 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); 167 168 /* Program the status register */ 169 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); 170 171 /* Read the config register */ 172 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); 173 174 /* Program the config register */ 175 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc); 176 177 /* Enable writing on the SPI flash */ 178 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) 179 { 180 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); 181 } 182 183 /* Disable writing on the SPI flash */ 184 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) 185 { 186 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); 187 } 188 189 /* 190 * Send the read status command to the device and wait for the wip 191 * (write-in-progress) bit to clear itself. 192 */ 193 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); 194 195 /* 196 * Used for spi_flash write operation 197 * - SPI claim 198 * - spi_flash_cmd_write_enable 199 * - spi_flash_cmd_write 200 * - spi_flash_cmd_wait_ready 201 * - SPI release 202 */ 203 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 204 size_t cmd_len, const void *buf, size_t buf_len); 205 206 /* 207 * Flash write operation, support all possible write commands. 208 * Write the requested data out breaking it up into multiple write 209 * commands as needed per the write size. 210 */ 211 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 212 size_t len, const void *buf); 213 214 /* 215 * Same as spi_flash_cmd_read() except it also claims/releases the SPI 216 * bus. Used as common part of the ->read() operation. 217 */ 218 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 219 size_t cmd_len, void *data, size_t data_len); 220 221 /* Flash read operation, support all possible read commands */ 222 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 223 size_t len, void *data); 224 225 #ifdef CONFIG_SPI_FLASH_MTD 226 int spi_flash_mtd_register(struct spi_flash *flash); 227 void spi_flash_mtd_unregister(void); 228 #endif 229 230 #endif /* _SF_INTERNAL_H_ */ 231