1 /* 2 * SPI flash internal definitions 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _SF_INTERNAL_H_ 11 #define _SF_INTERNAL_H_ 12 13 #include <linux/types.h> 14 #include <linux/compiler.h> 15 16 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ 17 enum spi_dual_flash { 18 SF_SINGLE_FLASH = 0, 19 SF_DUAL_STACKED_FLASH = 1 << 0, 20 SF_DUAL_PARALLEL_FLASH = 1 << 1, 21 }; 22 23 /* Enum list - Full read commands */ 24 enum spi_read_cmds { 25 ARRAY_SLOW = 1 << 0, 26 ARRAY_FAST = 1 << 1, 27 DUAL_OUTPUT_FAST = 1 << 2, 28 DUAL_IO_FAST = 1 << 3, 29 QUAD_OUTPUT_FAST = 1 << 4, 30 QUAD_IO_FAST = 1 << 5, 31 }; 32 33 /* Normal - Extended - Full command set */ 34 #define RD_NORM (ARRAY_SLOW | ARRAY_FAST) 35 #define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) 36 #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST) 37 38 /* sf param flags */ 39 enum { 40 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 41 SECT_4K = 1 << 0, 42 #else 43 SECT_4K = 0 << 0, 44 #endif 45 SECT_32K = 1 << 1, 46 E_FSR = 1 << 2, 47 SST_WR = 1 << 3, 48 WR_QPP = 1 << 4, 49 }; 50 51 enum spi_nor_option_flags { 52 SNOR_F_SST_WR = (1 << 0), 53 SNOR_F_USE_FSR = (1 << 1), 54 }; 55 56 #define SPI_FLASH_3B_ADDR_LEN 3 57 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) 58 #define SPI_FLASH_16MB_BOUN 0x1000000 59 60 /* CFI Manufacture ID's */ 61 #define SPI_FLASH_CFI_MFR_SPANSION 0x01 62 #define SPI_FLASH_CFI_MFR_STMICRO 0x20 63 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 64 #define SPI_FLASH_CFI_MFR_SST 0xbf 65 #define SPI_FLASH_CFI_MFR_WINBOND 0xef 66 #define SPI_FLASH_CFI_MFR_ATMEL 0x1f 67 68 /* Erase commands */ 69 #define CMD_ERASE_4K 0x20 70 #define CMD_ERASE_32K 0x52 71 #define CMD_ERASE_CHIP 0xc7 72 #define CMD_ERASE_64K 0xd8 73 74 /* Write commands */ 75 #define CMD_WRITE_STATUS 0x01 76 #define CMD_PAGE_PROGRAM 0x02 77 #define CMD_WRITE_DISABLE 0x04 78 #define CMD_READ_STATUS 0x05 79 #define CMD_QUAD_PAGE_PROGRAM 0x32 80 #define CMD_READ_STATUS1 0x35 81 #define CMD_WRITE_ENABLE 0x06 82 #define CMD_READ_CONFIG 0x35 83 #define CMD_FLAG_STATUS 0x70 84 85 /* Read commands */ 86 #define CMD_READ_ARRAY_SLOW 0x03 87 #define CMD_READ_ARRAY_FAST 0x0b 88 #define CMD_READ_DUAL_OUTPUT_FAST 0x3b 89 #define CMD_READ_DUAL_IO_FAST 0xbb 90 #define CMD_READ_QUAD_OUTPUT_FAST 0x6b 91 #define CMD_READ_QUAD_IO_FAST 0xeb 92 #define CMD_READ_ID 0x9f 93 94 /* Bank addr access commands */ 95 #ifdef CONFIG_SPI_FLASH_BAR 96 # define CMD_BANKADDR_BRWR 0x17 97 # define CMD_BANKADDR_BRRD 0x16 98 # define CMD_EXTNADDR_WREAR 0xC5 99 # define CMD_EXTNADDR_RDEAR 0xC8 100 #endif 101 102 /* Common status */ 103 #define STATUS_WIP (1 << 0) 104 #define STATUS_QEB_WINSPAN (1 << 1) 105 #define STATUS_QEB_MXIC (1 << 6) 106 #define STATUS_PEC (1 << 7) 107 #define SR_BP0 BIT(2) /* Block protect 0 */ 108 #define SR_BP1 BIT(3) /* Block protect 1 */ 109 #define SR_BP2 BIT(4) /* Block protect 2 */ 110 111 /* Flash timeout values */ 112 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) 113 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) 114 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) 115 116 /* SST specific */ 117 #ifdef CONFIG_SPI_FLASH_SST 118 # define CMD_SST_BP 0x02 /* Byte Program */ 119 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ 120 121 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 122 const void *buf); 123 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 124 const void *buf); 125 #endif 126 127 /** 128 * struct spi_flash_params - SPI/QSPI flash device params structure 129 * 130 * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) 131 * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) 132 * @ext_jedec: Device ext_jedec ID 133 * @sector_size: Isn't necessarily a sector size from vendor, 134 * the size listed here is what works with CMD_ERASE_64K 135 * @nr_sectors: No.of sectors on this device 136 * @e_rd_cmd: Enum list for read commands 137 * @flags: Important param, for flash specific behaviour 138 */ 139 struct spi_flash_params { 140 const char *name; 141 u32 jedec; 142 u16 ext_jedec; 143 u32 sector_size; 144 u32 nr_sectors; 145 u8 e_rd_cmd; 146 u16 flags; 147 }; 148 149 extern const struct spi_flash_params spi_flash_params_table[]; 150 151 /* Send a single-byte command to the device and read the response */ 152 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 153 154 /* 155 * Send a multi-byte command to the device and read the response. Used 156 * for flash array reads, etc. 157 */ 158 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 159 size_t cmd_len, void *data, size_t data_len); 160 161 /* 162 * Send a multi-byte command to the device followed by (optional) 163 * data. Used for programming the flash array, etc. 164 */ 165 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 166 const void *data, size_t data_len); 167 168 169 /* Flash erase(sectors) operation, support all possible erase commands */ 170 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); 171 172 /* Lock stmicro spi flash region */ 173 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len); 174 175 /* Unlock stmicro spi flash region */ 176 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len); 177 178 /* Check if a stmicro spi flash region is completely locked */ 179 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len); 180 181 /* Enable writing on the SPI flash */ 182 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) 183 { 184 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); 185 } 186 187 /* Disable writing on the SPI flash */ 188 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) 189 { 190 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); 191 } 192 193 /* 194 * Used for spi_flash write operation 195 * - SPI claim 196 * - spi_flash_cmd_write_enable 197 * - spi_flash_cmd_write 198 * - spi_flash_cmd_wait_ready 199 * - SPI release 200 */ 201 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 202 size_t cmd_len, const void *buf, size_t buf_len); 203 204 /* 205 * Flash write operation, support all possible write commands. 206 * Write the requested data out breaking it up into multiple write 207 * commands as needed per the write size. 208 */ 209 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 210 size_t len, const void *buf); 211 212 /* 213 * Same as spi_flash_cmd_read() except it also claims/releases the SPI 214 * bus. Used as common part of the ->read() operation. 215 */ 216 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 217 size_t cmd_len, void *data, size_t data_len); 218 219 /* Flash read operation, support all possible read commands */ 220 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 221 size_t len, void *data); 222 223 #ifdef CONFIG_SPI_FLASH_MTD 224 int spi_flash_mtd_register(struct spi_flash *flash); 225 void spi_flash_mtd_unregister(void); 226 #endif 227 228 /** 229 * spi_flash_scan - scan the SPI FLASH 230 * @flash: the spi flash structure 231 * 232 * The drivers can use this fuction to scan the SPI FLASH. 233 * In the scanning, it will try to get all the necessary information to 234 * fill the spi_flash{}. 235 * 236 * Return: 0 for success, others for failure. 237 */ 238 int spi_flash_scan(struct spi_flash *flash); 239 240 #endif /* _SF_INTERNAL_H_ */ 241