xref: /openbmc/u-boot/drivers/mtd/spi/sf_internal.h (revision 83bf0057)
1 /*
2  * SPI flash internal definitions
3  *
4  * Copyright (C) 2008 Atmel Corporation
5  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef _SF_INTERNAL_H_
11 #define _SF_INTERNAL_H_
12 
13 #include <linux/types.h>
14 #include <linux/compiler.h>
15 
16 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */
17 enum spi_dual_flash {
18 	SF_SINGLE_FLASH	= 0,
19 	SF_DUAL_STACKED_FLASH	= 1 << 0,
20 	SF_DUAL_PARALLEL_FLASH	= 1 << 1,
21 };
22 
23 /* Enum list - Full read commands */
24 enum spi_read_cmds {
25 	ARRAY_SLOW		= 1 << 0,
26 	ARRAY_FAST		= 1 << 1,
27 	DUAL_OUTPUT_FAST	= 1 << 2,
28 	DUAL_IO_FAST		= 1 << 3,
29 	QUAD_OUTPUT_FAST	= 1 << 4,
30 	QUAD_IO_FAST		= 1 << 5,
31 };
32 
33 /* Normal - Extended - Full command set */
34 #define RD_NORM		(ARRAY_SLOW | ARRAY_FAST)
35 #define RD_EXTN		(RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
36 #define RD_FULL		(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
37 
38 /* sf param flags */
39 enum {
40 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
41 	SECT_4K		= 1 << 0,
42 #else
43 	SECT_4K		= 0 << 0,
44 #endif
45 	SECT_32K	= 1 << 1,
46 	E_FSR		= 1 << 2,
47 	SST_BP		= 1 << 3,
48 	SST_WP		= 1 << 4,
49 	WR_QPP		= 1 << 5,
50 };
51 
52 #define SST_WR		(SST_BP | SST_WP)
53 
54 enum spi_nor_option_flags {
55 	SNOR_F_SST_WR		= (1 << 0),
56 	SNOR_F_USE_FSR		= (1 << 1),
57 };
58 
59 #define SPI_FLASH_3B_ADDR_LEN		3
60 #define SPI_FLASH_CMD_LEN		(1 + SPI_FLASH_3B_ADDR_LEN)
61 #define SPI_FLASH_16MB_BOUN		0x1000000
62 
63 /* CFI Manufacture ID's */
64 #define SPI_FLASH_CFI_MFR_SPANSION	0x01
65 #define SPI_FLASH_CFI_MFR_STMICRO	0x20
66 #define SPI_FLASH_CFI_MFR_MACRONIX	0xc2
67 #define SPI_FLASH_CFI_MFR_WINBOND	0xef
68 
69 /* Erase commands */
70 #define CMD_ERASE_4K			0x20
71 #define CMD_ERASE_32K			0x52
72 #define CMD_ERASE_CHIP			0xc7
73 #define CMD_ERASE_64K			0xd8
74 
75 /* Write commands */
76 #define CMD_WRITE_STATUS		0x01
77 #define CMD_PAGE_PROGRAM		0x02
78 #define CMD_WRITE_DISABLE		0x04
79 #define CMD_READ_STATUS			0x05
80 #define CMD_QUAD_PAGE_PROGRAM		0x32
81 #define CMD_READ_STATUS1		0x35
82 #define CMD_WRITE_ENABLE		0x06
83 #define CMD_READ_CONFIG			0x35
84 #define CMD_FLAG_STATUS			0x70
85 
86 /* Read commands */
87 #define CMD_READ_ARRAY_SLOW		0x03
88 #define CMD_READ_ARRAY_FAST		0x0b
89 #define CMD_READ_DUAL_OUTPUT_FAST	0x3b
90 #define CMD_READ_DUAL_IO_FAST		0xbb
91 #define CMD_READ_QUAD_OUTPUT_FAST	0x6b
92 #define CMD_READ_QUAD_IO_FAST		0xeb
93 #define CMD_READ_ID			0x9f
94 
95 /* Bank addr access commands */
96 #ifdef CONFIG_SPI_FLASH_BAR
97 # define CMD_BANKADDR_BRWR		0x17
98 # define CMD_BANKADDR_BRRD		0x16
99 # define CMD_EXTNADDR_WREAR		0xC5
100 # define CMD_EXTNADDR_RDEAR		0xC8
101 #endif
102 
103 /* Common status */
104 #define STATUS_WIP			(1 << 0)
105 #define STATUS_QEB_WINSPAN		(1 << 1)
106 #define STATUS_QEB_MXIC		(1 << 6)
107 #define STATUS_PEC			(1 << 7)
108 
109 /* Flash timeout values */
110 #define SPI_FLASH_PROG_TIMEOUT		(2 * CONFIG_SYS_HZ)
111 #define SPI_FLASH_PAGE_ERASE_TIMEOUT	(5 * CONFIG_SYS_HZ)
112 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT	(10 * CONFIG_SYS_HZ)
113 
114 /* SST specific */
115 #ifdef CONFIG_SPI_FLASH_SST
116 # define CMD_SST_BP		0x02    /* Byte Program */
117 # define CMD_SST_AAI_WP		0xAD	/* Auto Address Incr Word Program */
118 
119 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
120 		const void *buf);
121 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
122 		const void *buf);
123 #endif
124 
125 /**
126  * struct spi_flash_params - SPI/QSPI flash device params structure
127  *
128  * @name:		Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
129  * @jedec:		Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
130  * @ext_jedec:		Device ext_jedec ID
131  * @sector_size:	Isn't necessarily a sector size from vendor,
132  *			the size listed here is what works with CMD_ERASE_64K
133  * @nr_sectors:		No.of sectors on this device
134  * @e_rd_cmd:		Enum list for read commands
135  * @flags:		Important param, for flash specific behaviour
136  */
137 struct spi_flash_params {
138 	const char *name;
139 	u32 jedec;
140 	u16 ext_jedec;
141 	u32 sector_size;
142 	u32 nr_sectors;
143 	u8 e_rd_cmd;
144 	u16 flags;
145 };
146 
147 extern const struct spi_flash_params spi_flash_params_table[];
148 
149 /* Send a single-byte command to the device and read the response */
150 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
151 
152 /*
153  * Send a multi-byte command to the device and read the response. Used
154  * for flash array reads, etc.
155  */
156 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
157 		size_t cmd_len, void *data, size_t data_len);
158 
159 /*
160  * Send a multi-byte command to the device followed by (optional)
161  * data. Used for programming the flash array, etc.
162  */
163 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
164 		const void *data, size_t data_len);
165 
166 
167 /* Flash erase(sectors) operation, support all possible erase commands */
168 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
169 
170 /* Read the status register */
171 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
172 
173 /* Program the status register */
174 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
175 
176 /* Read the config register */
177 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
178 
179 /* Program the config register */
180 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
181 
182 /* Enable writing on the SPI flash */
183 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
184 {
185 	return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
186 }
187 
188 /* Disable writing on the SPI flash */
189 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
190 {
191 	return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
192 }
193 
194 /*
195  * Send the read status command to the device and wait for the wip
196  * (write-in-progress) bit to clear itself.
197  */
198 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
199 
200 /*
201  * Used for spi_flash write operation
202  * - SPI claim
203  * - spi_flash_cmd_write_enable
204  * - spi_flash_cmd_write
205  * - spi_flash_cmd_wait_ready
206  * - SPI release
207  */
208 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
209 		size_t cmd_len, const void *buf, size_t buf_len);
210 
211 /*
212  * Flash write operation, support all possible write commands.
213  * Write the requested data out breaking it up into multiple write
214  * commands as needed per the write size.
215  */
216 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
217 		size_t len, const void *buf);
218 
219 /*
220  * Same as spi_flash_cmd_read() except it also claims/releases the SPI
221  * bus. Used as common part of the ->read() operation.
222  */
223 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
224 		size_t cmd_len, void *data, size_t data_len);
225 
226 /* Flash read operation, support all possible read commands */
227 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
228 		size_t len, void *data);
229 
230 #ifdef CONFIG_SPI_FLASH_MTD
231 int spi_flash_mtd_register(struct spi_flash *flash);
232 void spi_flash_mtd_unregister(void);
233 #endif
234 
235 #endif /* _SF_INTERNAL_H_ */
236