1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * SPI flash internal definitions 4 * 5 * Copyright (C) 2008 Atmel Corporation 6 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 7 */ 8 9 #ifndef _SF_INTERNAL_H_ 10 #define _SF_INTERNAL_H_ 11 12 #include <linux/types.h> 13 #include <linux/compiler.h> 14 15 #define SPI_NOR_MAX_ID_LEN 6 16 #define SPI_NOR_MAX_ADDR_WIDTH 4 17 18 struct flash_info { 19 #if !CONFIG_IS_ENABLED(SPI_FLASH_TINY) 20 char *name; 21 #endif 22 23 /* 24 * This array stores the ID bytes. 25 * The first three bytes are the JEDIC ID. 26 * JEDEC ID zero means "no ID" (mostly older chips). 27 */ 28 u8 id[SPI_NOR_MAX_ID_LEN]; 29 u8 id_len; 30 31 /* The size listed here is what works with SPINOR_OP_SE, which isn't 32 * necessarily called a "sector" by the vendor. 33 */ 34 unsigned int sector_size; 35 u16 n_sectors; 36 37 u16 page_size; 38 u16 addr_width; 39 40 u16 flags; 41 #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ 42 #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ 43 #define SST_WRITE BIT(2) /* use SST byte programming */ 44 #define SPI_NOR_NO_FR BIT(3) /* Can't do fastread */ 45 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */ 46 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */ 47 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */ 48 #define USE_FSR BIT(7) /* use flag status register */ 49 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */ 50 #define SPI_NOR_HAS_TB BIT(9) /* 51 * Flash SR has Top/Bottom (TB) protect 52 * bit. Must be used with 53 * SPI_NOR_HAS_LOCK. 54 */ 55 #define SPI_S3AN BIT(10) /* 56 * Xilinx Spartan 3AN In-System Flash 57 * (MFR cannot be used for probing 58 * because it has the same value as 59 * ATMEL flashes) 60 */ 61 #define SPI_NOR_4B_OPCODES BIT(11) /* 62 * Use dedicated 4byte address op codes 63 * to support memory size above 128Mib. 64 */ 65 #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */ 66 #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */ 67 #define USE_CLSR BIT(14) /* use CLSR command */ 68 }; 69 70 extern const struct flash_info spi_nor_ids[]; 71 72 #define JEDEC_MFR(info) ((info)->id[0]) 73 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2])) 74 75 /* Send a single-byte command to the device and read the response */ 76 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 77 78 /* 79 * Send a multi-byte command to the device and read the response. Used 80 * for flash array reads, etc. 81 */ 82 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 83 size_t cmd_len, void *data, size_t data_len); 84 85 /* 86 * Send a multi-byte command to the device followed by (optional) 87 * data. Used for programming the flash array, etc. 88 */ 89 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 90 const void *data, size_t data_len); 91 92 93 /* Get software write-protect value (BP bits) */ 94 int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash); 95 96 int spi_flash_wlock_by_host_ctrl(struct spi_flash *flash, 97 u32 offset, size_t len); 98 int spi_flash_wunlock_by_host_ctrl(struct spi_flash *flash, 99 u32 offset, size_t len); 100 int spi_nor_ctrl_wlock(struct spi_slave *slave, u32 offset, size_t len); 101 int spi_nor_ctrl_wunlock(struct spi_slave *slave, u32 offset, size_t len); 102 103 #ifdef CONFIG_SPI_FLASH_MTD 104 int spi_flash_mtd_register(struct spi_flash *flash); 105 void spi_flash_mtd_unregister(void); 106 #endif 107 #endif /* _SF_INTERNAL_H_ */ 108