1 /* 2 * SPI flash internal definitions 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _SF_INTERNAL_H_ 11 #define _SF_INTERNAL_H_ 12 13 #include <linux/types.h> 14 #include <linux/compiler.h> 15 16 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ 17 enum spi_dual_flash { 18 SF_SINGLE_FLASH = 0, 19 SF_DUAL_STACKED_FLASH = BIT(0), 20 SF_DUAL_PARALLEL_FLASH = BIT(1), 21 }; 22 23 enum spi_nor_option_flags { 24 SNOR_F_SST_WR = BIT(0), 25 SNOR_F_USE_FSR = BIT(1), 26 SNOR_F_USE_UPAGE = BIT(3), 27 }; 28 29 #define SPI_FLASH_3B_ADDR_LEN 3 30 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) 31 #define SPI_FLASH_16MB_BOUN 0x1000000 32 33 /* CFI Manufacture ID's */ 34 #define SPI_FLASH_CFI_MFR_SPANSION 0x01 35 #define SPI_FLASH_CFI_MFR_STMICRO 0x20 36 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 37 #define SPI_FLASH_CFI_MFR_SST 0xbf 38 #define SPI_FLASH_CFI_MFR_WINBOND 0xef 39 #define SPI_FLASH_CFI_MFR_ATMEL 0x1f 40 41 /* Erase commands */ 42 #define CMD_ERASE_4K 0x20 43 #define CMD_ERASE_CHIP 0xc7 44 #define CMD_ERASE_64K 0xd8 45 46 /* Write commands */ 47 #define CMD_WRITE_STATUS 0x01 48 #define CMD_PAGE_PROGRAM 0x02 49 #define CMD_WRITE_DISABLE 0x04 50 #define CMD_WRITE_ENABLE 0x06 51 #define CMD_QUAD_PAGE_PROGRAM 0x32 52 #define CMD_WRITE_EVCR 0x61 53 54 /* Read commands */ 55 #define CMD_READ_ARRAY_SLOW 0x03 56 #define CMD_READ_ARRAY_FAST 0x0b 57 #define CMD_READ_DUAL_OUTPUT_FAST 0x3b 58 #define CMD_READ_DUAL_IO_FAST 0xbb 59 #define CMD_READ_QUAD_OUTPUT_FAST 0x6b 60 #define CMD_READ_QUAD_IO_FAST 0xeb 61 #define CMD_READ_ID 0x9f 62 #define CMD_READ_STATUS 0x05 63 #define CMD_READ_STATUS1 0x35 64 #define CMD_READ_CONFIG 0x35 65 #define CMD_FLAG_STATUS 0x70 66 #define CMD_READ_EVCR 0x65 67 68 /* Bank addr access commands */ 69 #ifdef CONFIG_SPI_FLASH_BAR 70 # define CMD_BANKADDR_BRWR 0x17 71 # define CMD_BANKADDR_BRRD 0x16 72 # define CMD_EXTNADDR_WREAR 0xC5 73 # define CMD_EXTNADDR_RDEAR 0xC8 74 #endif 75 76 /* Common status */ 77 #define STATUS_WIP BIT(0) 78 #define STATUS_QEB_WINSPAN BIT(1) 79 #define STATUS_QEB_MXIC BIT(6) 80 #define STATUS_PEC BIT(7) 81 #define STATUS_QEB_MICRON BIT(7) 82 #define SR_BP0 BIT(2) /* Block protect 0 */ 83 #define SR_BP1 BIT(3) /* Block protect 1 */ 84 #define SR_BP2 BIT(4) /* Block protect 2 */ 85 86 /* Flash timeout values */ 87 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) 88 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) 89 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) 90 91 /* SST specific */ 92 #ifdef CONFIG_SPI_FLASH_SST 93 # define CMD_SST_BP 0x02 /* Byte Program */ 94 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ 95 96 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 97 const void *buf); 98 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 99 const void *buf); 100 #endif 101 102 #define JEDEC_MFR(info) ((info)->id[0]) 103 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2])) 104 #define JEDEC_EXT(info) (((info)->id[3]) << 8 | ((info)->id[4])) 105 #define SPI_FLASH_MAX_ID_LEN 6 106 107 struct spi_flash_info { 108 /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */ 109 const char *name; 110 111 /* 112 * This array stores the ID bytes. 113 * The first three bytes are the JEDIC ID. 114 * JEDEC ID zero means "no ID" (mostly older chips). 115 */ 116 u8 id[SPI_FLASH_MAX_ID_LEN]; 117 u8 id_len; 118 119 /* 120 * The size listed here is what works with SPINOR_OP_SE, which isn't 121 * necessarily called a "sector" by the vendor. 122 */ 123 u32 sector_size; 124 u32 n_sectors; 125 126 u16 page_size; 127 128 u16 flags; 129 #define SECT_4K BIT(0) /* CMD_ERASE_4K works uniformly */ 130 #define E_FSR BIT(1) /* use flag status register for */ 131 #define SST_WR BIT(2) /* use SST byte/word programming */ 132 #define WR_QPP BIT(3) /* use Quad Page Program */ 133 #define RD_QUAD BIT(4) /* use Quad Read */ 134 #define RD_DUAL BIT(5) /* use Dual Read */ 135 #define RD_QUADIO BIT(6) /* use Quad IO Read */ 136 #define RD_DUALIO BIT(7) /* use Dual IO Read */ 137 #define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO) 138 }; 139 140 extern const struct spi_flash_info spi_flash_ids[]; 141 142 /* Send a single-byte command to the device and read the response */ 143 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 144 145 /* 146 * Send a multi-byte command to the device and read the response. Used 147 * for flash array reads, etc. 148 */ 149 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 150 size_t cmd_len, void *data, size_t data_len); 151 152 /* 153 * Send a multi-byte command to the device followed by (optional) 154 * data. Used for programming the flash array, etc. 155 */ 156 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 157 const void *data, size_t data_len); 158 159 160 /* Flash erase(sectors) operation, support all possible erase commands */ 161 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); 162 163 /* Lock stmicro spi flash region */ 164 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len); 165 166 /* Unlock stmicro spi flash region */ 167 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len); 168 169 /* Check if a stmicro spi flash region is completely locked */ 170 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len); 171 172 /* Enable writing on the SPI flash */ 173 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) 174 { 175 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); 176 } 177 178 /* Disable writing on the SPI flash */ 179 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) 180 { 181 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); 182 } 183 184 /* 185 * Used for spi_flash write operation 186 * - SPI claim 187 * - spi_flash_cmd_write_enable 188 * - spi_flash_cmd_write 189 * - spi_flash_wait_till_ready 190 * - SPI release 191 */ 192 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 193 size_t cmd_len, const void *buf, size_t buf_len); 194 195 /* 196 * Flash write operation, support all possible write commands. 197 * Write the requested data out breaking it up into multiple write 198 * commands as needed per the write size. 199 */ 200 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 201 size_t len, const void *buf); 202 203 /* 204 * Same as spi_flash_cmd_read() except it also claims/releases the SPI 205 * bus. Used as common part of the ->read() operation. 206 */ 207 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 208 size_t cmd_len, void *data, size_t data_len); 209 210 /* Flash read operation, support all possible read commands */ 211 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 212 size_t len, void *data); 213 214 #ifdef CONFIG_SPI_FLASH_MTD 215 int spi_flash_mtd_register(struct spi_flash *flash); 216 void spi_flash_mtd_unregister(void); 217 #endif 218 219 /** 220 * spi_flash_scan - scan the SPI FLASH 221 * @flash: the spi flash structure 222 * 223 * The drivers can use this fuction to scan the SPI FLASH. 224 * In the scanning, it will try to get all the necessary information to 225 * fill the spi_flash{}. 226 * 227 * Return: 0 for success, others for failure. 228 */ 229 int spi_flash_scan(struct spi_flash *flash); 230 231 #endif /* _SF_INTERNAL_H_ */ 232