1 /* 2 * SPI flash internal definitions 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _SF_INTERNAL_H_ 11 #define _SF_INTERNAL_H_ 12 13 #include <linux/types.h> 14 #include <linux/compiler.h> 15 16 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ 17 enum spi_dual_flash { 18 SF_SINGLE_FLASH = 0, 19 SF_DUAL_STACKED_FLASH = 1 << 0, 20 SF_DUAL_PARALLEL_FLASH = 1 << 1, 21 }; 22 23 /* Enum list - Full read commands */ 24 enum spi_read_cmds { 25 ARRAY_SLOW = 1 << 0, 26 ARRAY_FAST = 1 << 1, 27 DUAL_OUTPUT_FAST = 1 << 2, 28 DUAL_IO_FAST = 1 << 3, 29 QUAD_OUTPUT_FAST = 1 << 4, 30 QUAD_IO_FAST = 1 << 5, 31 }; 32 33 /* Normal - Extended - Full command set */ 34 #define RD_NORM (ARRAY_SLOW | ARRAY_FAST) 35 #define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) 36 #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST) 37 38 /* sf param flags */ 39 enum { 40 SECT_4K = 1 << 0, 41 SECT_32K = 1 << 1, 42 E_FSR = 1 << 2, 43 WR_QPP = 1 << 3, 44 }; 45 46 #define SPI_FLASH_3B_ADDR_LEN 3 47 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) 48 #define SPI_FLASH_16MB_BOUN 0x1000000 49 50 /* CFI Manufacture ID's */ 51 #define SPI_FLASH_CFI_MFR_SPANSION 0x01 52 #define SPI_FLASH_CFI_MFR_STMICRO 0x20 53 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 54 #define SPI_FLASH_CFI_MFR_WINBOND 0xef 55 56 /* Erase commands */ 57 #define CMD_ERASE_4K 0x20 58 #define CMD_ERASE_32K 0x52 59 #define CMD_ERASE_CHIP 0xc7 60 #define CMD_ERASE_64K 0xd8 61 62 /* Write commands */ 63 #define CMD_WRITE_STATUS 0x01 64 #define CMD_PAGE_PROGRAM 0x02 65 #define CMD_WRITE_DISABLE 0x04 66 #define CMD_READ_STATUS 0x05 67 #define CMD_QUAD_PAGE_PROGRAM 0x32 68 #define CMD_READ_STATUS1 0x35 69 #define CMD_WRITE_ENABLE 0x06 70 #define CMD_READ_CONFIG 0x35 71 #define CMD_FLAG_STATUS 0x70 72 73 /* Read commands */ 74 #define CMD_READ_ARRAY_SLOW 0x03 75 #define CMD_READ_ARRAY_FAST 0x0b 76 #define CMD_READ_DUAL_OUTPUT_FAST 0x3b 77 #define CMD_READ_DUAL_IO_FAST 0xbb 78 #define CMD_READ_QUAD_OUTPUT_FAST 0x6b 79 #define CMD_READ_QUAD_IO_FAST 0xeb 80 #define CMD_READ_ID 0x9f 81 82 /* Bank addr access commands */ 83 #ifdef CONFIG_SPI_FLASH_BAR 84 # define CMD_BANKADDR_BRWR 0x17 85 # define CMD_BANKADDR_BRRD 0x16 86 # define CMD_EXTNADDR_WREAR 0xC5 87 # define CMD_EXTNADDR_RDEAR 0xC8 88 #endif 89 90 /* Common status */ 91 #define STATUS_WIP (1 << 0) 92 #define STATUS_QEB_WINSPAN (1 << 1) 93 #define STATUS_QEB_MXIC (1 << 6) 94 #define STATUS_PEC (1 << 7) 95 96 #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN 97 #define STATUS_SRWD (1 << 7) /* SR write protect */ 98 #endif 99 100 /* Flash timeout values */ 101 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) 102 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) 103 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) 104 105 /* SST specific */ 106 #ifdef CONFIG_SPI_FLASH_SST 107 # define SST_WP 0x01 /* Supports AAI word program */ 108 # define CMD_SST_BP 0x02 /* Byte Program */ 109 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ 110 111 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 112 const void *buf); 113 #endif 114 115 /** 116 * struct spi_flash_params - SPI/QSPI flash device params structure 117 * 118 * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) 119 * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) 120 * @ext_jedec: Device ext_jedec ID 121 * @sector_size: Sector size of this device 122 * @nr_sectors: No.of sectors on this device 123 * @e_rd_cmd: Enum list for read commands 124 * @flags: Important param, for flash specific behaviour 125 */ 126 struct spi_flash_params { 127 const char *name; 128 u32 jedec; 129 u16 ext_jedec; 130 u32 sector_size; 131 u32 nr_sectors; 132 u8 e_rd_cmd; 133 u16 flags; 134 }; 135 136 extern const struct spi_flash_params spi_flash_params_table[]; 137 138 /* Send a single-byte command to the device and read the response */ 139 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 140 141 /* 142 * Send a multi-byte command to the device and read the response. Used 143 * for flash array reads, etc. 144 */ 145 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 146 size_t cmd_len, void *data, size_t data_len); 147 148 /* 149 * Send a multi-byte command to the device followed by (optional) 150 * data. Used for programming the flash array, etc. 151 */ 152 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 153 const void *data, size_t data_len); 154 155 156 /* Flash erase(sectors) operation, support all possible erase commands */ 157 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); 158 159 /* Read the status register */ 160 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); 161 162 /* Program the status register */ 163 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); 164 165 /* Read the config register */ 166 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); 167 168 /* Program the config register */ 169 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc); 170 171 /* Enable writing on the SPI flash */ 172 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) 173 { 174 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); 175 } 176 177 /* Disable writing on the SPI flash */ 178 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) 179 { 180 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); 181 } 182 183 /* 184 * Send the read status command to the device and wait for the wip 185 * (write-in-progress) bit to clear itself. 186 */ 187 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); 188 189 /* 190 * Used for spi_flash write operation 191 * - SPI claim 192 * - spi_flash_cmd_write_enable 193 * - spi_flash_cmd_write 194 * - spi_flash_cmd_wait_ready 195 * - SPI release 196 */ 197 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 198 size_t cmd_len, const void *buf, size_t buf_len); 199 200 /* 201 * Flash write operation, support all possible write commands. 202 * Write the requested data out breaking it up into multiple write 203 * commands as needed per the write size. 204 */ 205 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 206 size_t len, const void *buf); 207 208 /* 209 * Same as spi_flash_cmd_read() except it also claims/releases the SPI 210 * bus. Used as common part of the ->read() operation. 211 */ 212 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 213 size_t cmd_len, void *data, size_t data_len); 214 215 /* Flash read operation, support all possible read commands */ 216 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 217 size_t len, void *data); 218 219 #endif /* _SF_INTERNAL_H_ */ 220