1 /* 2 * SPI flash internal definitions 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _SF_INTERNAL_H_ 11 #define _SF_INTERNAL_H_ 12 13 #define SPI_FLASH_3B_ADDR_LEN 3 14 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) 15 #define SPI_FLASH_16MB_BOUN 0x1000000 16 17 /* CFI Manufacture ID's */ 18 #define SPI_FLASH_CFI_MFR_SPANSION 0x01 19 #define SPI_FLASH_CFI_MFR_STMICRO 0x20 20 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 21 #define SPI_FLASH_CFI_MFR_WINBOND 0xef 22 23 /* Erase commands */ 24 #define CMD_ERASE_4K 0x20 25 #define CMD_ERASE_32K 0x52 26 #define CMD_ERASE_CHIP 0xc7 27 #define CMD_ERASE_64K 0xd8 28 29 /* Write commands */ 30 #define CMD_WRITE_STATUS 0x01 31 #define CMD_PAGE_PROGRAM 0x02 32 #define CMD_WRITE_DISABLE 0x04 33 #define CMD_READ_STATUS 0x05 34 #define CMD_QUAD_PAGE_PROGRAM 0x32 35 #define CMD_READ_STATUS1 0x35 36 #define CMD_WRITE_ENABLE 0x06 37 #define CMD_READ_CONFIG 0x35 38 #define CMD_FLAG_STATUS 0x70 39 40 /* Read commands */ 41 #define CMD_READ_ARRAY_SLOW 0x03 42 #define CMD_READ_ARRAY_FAST 0x0b 43 #define CMD_READ_DUAL_OUTPUT_FAST 0x3b 44 #define CMD_READ_DUAL_IO_FAST 0xbb 45 #define CMD_READ_QUAD_OUTPUT_FAST 0x6b 46 #define CMD_READ_QUAD_IO_FAST 0xeb 47 #define CMD_READ_ID 0x9f 48 49 /* Bank addr access commands */ 50 #ifdef CONFIG_SPI_FLASH_BAR 51 # define CMD_BANKADDR_BRWR 0x17 52 # define CMD_BANKADDR_BRRD 0x16 53 # define CMD_EXTNADDR_WREAR 0xC5 54 # define CMD_EXTNADDR_RDEAR 0xC8 55 #endif 56 57 /* Common status */ 58 #define STATUS_WIP (1 << 0) 59 #define STATUS_QEB_WINSPAN (1 << 1) 60 #define STATUS_QEB_MXIC (1 << 6) 61 #define STATUS_PEC (1 << 7) 62 63 #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN 64 #define STATUS_SRWD (1 << 7) /* SR write protect */ 65 #endif 66 67 /* Flash timeout values */ 68 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) 69 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) 70 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) 71 72 /* SST specific */ 73 #ifdef CONFIG_SPI_FLASH_SST 74 # define SST_WP 0x01 /* Supports AAI word program */ 75 # define CMD_SST_BP 0x02 /* Byte Program */ 76 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ 77 78 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 79 const void *buf); 80 #endif 81 82 /* Send a single-byte command to the device and read the response */ 83 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 84 85 /* 86 * Send a multi-byte command to the device and read the response. Used 87 * for flash array reads, etc. 88 */ 89 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 90 size_t cmd_len, void *data, size_t data_len); 91 92 /* 93 * Send a multi-byte command to the device followed by (optional) 94 * data. Used for programming the flash array, etc. 95 */ 96 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 97 const void *data, size_t data_len); 98 99 100 /* Flash erase(sectors) operation, support all possible erase commands */ 101 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); 102 103 /* Read the status register */ 104 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); 105 106 /* Program the status register */ 107 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); 108 109 /* Read the config register */ 110 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); 111 112 /* Program the config register */ 113 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc); 114 115 /* Enable writing on the SPI flash */ 116 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) 117 { 118 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); 119 } 120 121 /* Disable writing on the SPI flash */ 122 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) 123 { 124 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); 125 } 126 127 /* 128 * Send the read status command to the device and wait for the wip 129 * (write-in-progress) bit to clear itself. 130 */ 131 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); 132 133 /* 134 * Used for spi_flash write operation 135 * - SPI claim 136 * - spi_flash_cmd_write_enable 137 * - spi_flash_cmd_write 138 * - spi_flash_cmd_wait_ready 139 * - SPI release 140 */ 141 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 142 size_t cmd_len, const void *buf, size_t buf_len); 143 144 /* 145 * Flash write operation, support all possible write commands. 146 * Write the requested data out breaking it up into multiple write 147 * commands as needed per the write size. 148 */ 149 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 150 size_t len, const void *buf); 151 152 /* 153 * Same as spi_flash_cmd_read() except it also claims/releases the SPI 154 * bus. Used as common part of the ->read() operation. 155 */ 156 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 157 size_t cmd_len, void *data, size_t data_len); 158 159 /* Flash read operation, support all possible read commands */ 160 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 161 size_t len, void *data); 162 163 #endif /* _SF_INTERNAL_H_ */ 164