1 /* 2 * SPI flash internal definitions 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _SF_INTERNAL_H_ 11 #define _SF_INTERNAL_H_ 12 13 #include <linux/types.h> 14 #include <linux/compiler.h> 15 16 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ 17 enum spi_dual_flash { 18 SF_SINGLE_FLASH = 0, 19 SF_DUAL_STACKED_FLASH = BIT(0), 20 SF_DUAL_PARALLEL_FLASH = BIT(1), 21 }; 22 23 /* Enum list - Full read commands */ 24 enum spi_read_cmds { 25 ARRAY_SLOW = BIT(0), 26 ARRAY_FAST = BIT(1), 27 DUAL_OUTPUT_FAST = BIT(2), 28 QUAD_OUTPUT_FAST = BIT(3), 29 DUAL_IO_FAST = BIT(4), 30 QUAD_IO_FAST = BIT(5), 31 }; 32 33 /* Normal - Extended - Full command set */ 34 #define RD_NORM (ARRAY_SLOW | ARRAY_FAST) 35 #define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) 36 #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST) 37 38 /* sf param flags */ 39 enum { 40 #ifndef CONFIG_SPI_FLASH_USE_4K_SECTORS 41 SECT_4K = 0, 42 #else 43 SECT_4K = BIT(0), 44 #endif 45 SECT_32K = BIT(1), 46 E_FSR = BIT(2), 47 SST_WR = BIT(3), 48 WR_QPP = BIT(4), 49 }; 50 51 enum spi_nor_option_flags { 52 SNOR_F_SST_WR = BIT(0), 53 SNOR_F_USE_FSR = BIT(1), 54 }; 55 56 #define SPI_FLASH_3B_ADDR_LEN 3 57 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) 58 #define SPI_FLASH_16MB_BOUN 0x1000000 59 60 /* CFI Manufacture ID's */ 61 #define SPI_FLASH_CFI_MFR_SPANSION 0x01 62 #define SPI_FLASH_CFI_MFR_STMICRO 0x20 63 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 64 #define SPI_FLASH_CFI_MFR_SST 0xbf 65 #define SPI_FLASH_CFI_MFR_WINBOND 0xef 66 #define SPI_FLASH_CFI_MFR_ATMEL 0x1f 67 68 /* Erase commands */ 69 #define CMD_ERASE_4K 0x20 70 #define CMD_ERASE_32K 0x52 71 #define CMD_ERASE_CHIP 0xc7 72 #define CMD_ERASE_64K 0xd8 73 74 /* Write commands */ 75 #define CMD_WRITE_STATUS 0x01 76 #define CMD_PAGE_PROGRAM 0x02 77 #define CMD_WRITE_DISABLE 0x04 78 #define CMD_WRITE_ENABLE 0x06 79 #define CMD_QUAD_PAGE_PROGRAM 0x32 80 #define CMD_WRITE_EVCR 0x61 81 82 /* Read commands */ 83 #define CMD_READ_ARRAY_SLOW 0x03 84 #define CMD_READ_ARRAY_FAST 0x0b 85 #define CMD_READ_DUAL_OUTPUT_FAST 0x3b 86 #define CMD_READ_DUAL_IO_FAST 0xbb 87 #define CMD_READ_QUAD_OUTPUT_FAST 0x6b 88 #define CMD_READ_QUAD_IO_FAST 0xeb 89 #define CMD_READ_ID 0x9f 90 #define CMD_READ_STATUS 0x05 91 #define CMD_READ_STATUS1 0x35 92 #define CMD_READ_CONFIG 0x35 93 #define CMD_FLAG_STATUS 0x70 94 #define CMD_READ_EVCR 0x65 95 96 /* Bank addr access commands */ 97 #ifdef CONFIG_SPI_FLASH_BAR 98 # define CMD_BANKADDR_BRWR 0x17 99 # define CMD_BANKADDR_BRRD 0x16 100 # define CMD_EXTNADDR_WREAR 0xC5 101 # define CMD_EXTNADDR_RDEAR 0xC8 102 #endif 103 104 /* Common status */ 105 #define STATUS_WIP BIT(0) 106 #define STATUS_QEB_WINSPAN BIT(1) 107 #define STATUS_QEB_MXIC BIT(6) 108 #define STATUS_PEC BIT(7) 109 #define STATUS_QEB_MICRON BIT(7) 110 #define SR_BP0 BIT(2) /* Block protect 0 */ 111 #define SR_BP1 BIT(3) /* Block protect 1 */ 112 #define SR_BP2 BIT(4) /* Block protect 2 */ 113 114 /* Flash timeout values */ 115 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) 116 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) 117 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) 118 119 /* SST specific */ 120 #ifdef CONFIG_SPI_FLASH_SST 121 # define CMD_SST_BP 0x02 /* Byte Program */ 122 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ 123 124 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 125 const void *buf); 126 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 127 const void *buf); 128 #endif 129 130 /** 131 * struct spi_flash_params - SPI/QSPI flash device params structure 132 * 133 * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) 134 * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) 135 * @ext_jedec: Device ext_jedec ID 136 * @sector_size: Isn't necessarily a sector size from vendor, 137 * the size listed here is what works with CMD_ERASE_64K 138 * @nr_sectors: No.of sectors on this device 139 * @e_rd_cmd: Enum list for read commands 140 * @flags: Important param, for flash specific behaviour 141 */ 142 struct spi_flash_params { 143 const char *name; 144 u32 jedec; 145 u16 ext_jedec; 146 u32 sector_size; 147 u32 nr_sectors; 148 u8 e_rd_cmd; 149 u16 flags; 150 }; 151 152 extern const struct spi_flash_params spi_flash_params_table[]; 153 154 /* Send a single-byte command to the device and read the response */ 155 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 156 157 /* 158 * Send a multi-byte command to the device and read the response. Used 159 * for flash array reads, etc. 160 */ 161 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 162 size_t cmd_len, void *data, size_t data_len); 163 164 /* 165 * Send a multi-byte command to the device followed by (optional) 166 * data. Used for programming the flash array, etc. 167 */ 168 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 169 const void *data, size_t data_len); 170 171 172 /* Flash erase(sectors) operation, support all possible erase commands */ 173 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); 174 175 /* Lock stmicro spi flash region */ 176 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len); 177 178 /* Unlock stmicro spi flash region */ 179 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len); 180 181 /* Check if a stmicro spi flash region is completely locked */ 182 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len); 183 184 /* Enable writing on the SPI flash */ 185 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) 186 { 187 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); 188 } 189 190 /* Disable writing on the SPI flash */ 191 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) 192 { 193 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); 194 } 195 196 /* 197 * Used for spi_flash write operation 198 * - SPI claim 199 * - spi_flash_cmd_write_enable 200 * - spi_flash_cmd_write 201 * - spi_flash_cmd_wait_ready 202 * - SPI release 203 */ 204 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 205 size_t cmd_len, const void *buf, size_t buf_len); 206 207 /* 208 * Flash write operation, support all possible write commands. 209 * Write the requested data out breaking it up into multiple write 210 * commands as needed per the write size. 211 */ 212 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 213 size_t len, const void *buf); 214 215 /* 216 * Same as spi_flash_cmd_read() except it also claims/releases the SPI 217 * bus. Used as common part of the ->read() operation. 218 */ 219 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 220 size_t cmd_len, void *data, size_t data_len); 221 222 /* Flash read operation, support all possible read commands */ 223 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 224 size_t len, void *data); 225 226 #ifdef CONFIG_SPI_FLASH_MTD 227 int spi_flash_mtd_register(struct spi_flash *flash); 228 void spi_flash_mtd_unregister(void); 229 #endif 230 231 /** 232 * spi_flash_scan - scan the SPI FLASH 233 * @flash: the spi flash structure 234 * 235 * The drivers can use this fuction to scan the SPI FLASH. 236 * In the scanning, it will try to get all the necessary information to 237 * fill the spi_flash{}. 238 * 239 * Return: 0 for success, others for failure. 240 */ 241 int spi_flash_scan(struct spi_flash *flash); 242 243 #endif /* _SF_INTERNAL_H_ */ 244