1 /* 2 * Atmel DataFlash probing 3 * 4 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc. 5 * Haikun Wang (haikun.wang@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <fdtdec.h> 14 #include <spi.h> 15 #include <spi_flash.h> 16 #include <div64.h> 17 #include <linux/err.h> 18 #include <linux/math64.h> 19 20 #include "sf_internal.h" 21 22 /* reads can bypass the buffers */ 23 #define OP_READ_CONTINUOUS 0xE8 24 #define OP_READ_PAGE 0xD2 25 26 /* group B requests can run even while status reports "busy" */ 27 #define OP_READ_STATUS 0xD7 /* group B */ 28 29 /* move data between host and buffer */ 30 #define OP_READ_BUFFER1 0xD4 /* group B */ 31 #define OP_READ_BUFFER2 0xD6 /* group B */ 32 #define OP_WRITE_BUFFER1 0x84 /* group B */ 33 #define OP_WRITE_BUFFER2 0x87 /* group B */ 34 35 /* erasing flash */ 36 #define OP_ERASE_PAGE 0x81 37 #define OP_ERASE_BLOCK 0x50 38 39 /* move data between buffer and flash */ 40 #define OP_TRANSFER_BUF1 0x53 41 #define OP_TRANSFER_BUF2 0x55 42 #define OP_MREAD_BUFFER1 0xD4 43 #define OP_MREAD_BUFFER2 0xD6 44 #define OP_MWERASE_BUFFER1 0x83 45 #define OP_MWERASE_BUFFER2 0x86 46 #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */ 47 #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */ 48 49 /* write to buffer, then write-erase to flash */ 50 #define OP_PROGRAM_VIA_BUF1 0x82 51 #define OP_PROGRAM_VIA_BUF2 0x85 52 53 /* compare buffer to flash */ 54 #define OP_COMPARE_BUF1 0x60 55 #define OP_COMPARE_BUF2 0x61 56 57 /* read flash to buffer, then write-erase to flash */ 58 #define OP_REWRITE_VIA_BUF1 0x58 59 #define OP_REWRITE_VIA_BUF2 0x59 60 61 /* 62 * newer chips report JEDEC manufacturer and device IDs; chip 63 * serial number and OTP bits; and per-sector writeprotect. 64 */ 65 #define OP_READ_ID 0x9F 66 #define OP_READ_SECURITY 0x77 67 #define OP_WRITE_SECURITY_REVC 0x9A 68 #define OP_WRITE_SECURITY 0x9B /* revision D */ 69 70 struct dataflash { 71 uint8_t command[16]; 72 unsigned short page_offset; /* offset in flash address */ 73 }; 74 75 /* Return the status of the DataFlash device */ 76 static inline int dataflash_status(struct spi_slave *spi) 77 { 78 int ret; 79 u8 status; 80 /* 81 * NOTE: at45db321c over 25 MHz wants to write 82 * a dummy byte after the opcode... 83 */ 84 ret = spi_flash_cmd(spi, OP_READ_STATUS, &status, 1); 85 return ret ? -EIO : status; 86 } 87 88 /* 89 * Poll the DataFlash device until it is READY. 90 * This usually takes 5-20 msec or so; more for sector erase. 91 * ready: return > 0 92 */ 93 static int dataflash_waitready(struct spi_slave *spi) 94 { 95 int status; 96 int timeout = 2 * CONFIG_SYS_HZ; 97 int timebase; 98 99 timebase = get_timer(0); 100 do { 101 status = dataflash_status(spi); 102 if (status < 0) 103 status = 0; 104 105 if (status & (1 << 7)) /* RDY/nBSY */ 106 return status; 107 108 mdelay(3); 109 } while (get_timer(timebase) < timeout); 110 111 return -ETIME; 112 } 113 114 /* Erase pages of flash */ 115 static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len) 116 { 117 struct dataflash *dataflash; 118 struct spi_flash *spi_flash; 119 struct spi_slave *spi; 120 unsigned blocksize; 121 uint8_t *command; 122 uint32_t rem; 123 int status; 124 125 dataflash = dev_get_priv(dev); 126 spi_flash = dev_get_uclass_priv(dev); 127 spi = spi_flash->spi; 128 129 blocksize = spi_flash->page_size << 3; 130 131 memset(dataflash->command, 0 , sizeof(dataflash->command)); 132 command = dataflash->command; 133 134 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len); 135 136 div_u64_rem(len, spi_flash->page_size, &rem); 137 if (rem) 138 return -EINVAL; 139 div_u64_rem(offset, spi_flash->page_size, &rem); 140 if (rem) 141 return -EINVAL; 142 143 status = spi_claim_bus(spi); 144 if (status) { 145 debug("dataflash: unable to claim SPI bus\n"); 146 return status; 147 } 148 149 while (len > 0) { 150 unsigned int pageaddr; 151 int do_block; 152 /* 153 * Calculate flash page address; use block erase (for speed) if 154 * we're at a block boundary and need to erase the whole block. 155 */ 156 pageaddr = div_u64(offset, spi_flash->page_size); 157 do_block = (pageaddr & 0x7) == 0 && len >= blocksize; 158 pageaddr = pageaddr << dataflash->page_offset; 159 160 command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE; 161 command[1] = (uint8_t)(pageaddr >> 16); 162 command[2] = (uint8_t)(pageaddr >> 8); 163 command[3] = 0; 164 165 debug("%s ERASE %s: (%x) %x %x %x [%d]\n", 166 dev->name, do_block ? "block" : "page", 167 command[0], command[1], command[2], command[3], 168 pageaddr); 169 170 status = spi_flash_cmd_write(spi, command, 4, NULL, 0); 171 if (status < 0) { 172 debug("%s: erase send command error!\n", dev->name); 173 return -EIO; 174 } 175 176 status = dataflash_waitready(spi); 177 if (status < 0) { 178 debug("%s: erase waitready error!\n", dev->name); 179 return status; 180 } 181 182 if (do_block) { 183 offset += blocksize; 184 len -= blocksize; 185 } else { 186 offset += spi_flash->page_size; 187 len -= spi_flash->page_size; 188 } 189 } 190 191 spi_release_bus(spi); 192 193 return 0; 194 } 195 196 /* 197 * Read from the DataFlash device. 198 * offset : Start offset in flash device 199 * len : Amount to read 200 * buf : Buffer containing the data 201 */ 202 static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len, 203 void *buf) 204 { 205 struct dataflash *dataflash; 206 struct spi_flash *spi_flash; 207 struct spi_slave *spi; 208 unsigned int addr; 209 uint8_t *command; 210 int status; 211 212 dataflash = dev_get_priv(dev); 213 spi_flash = dev_get_uclass_priv(dev); 214 spi = spi_flash->spi; 215 216 memset(dataflash->command, 0 , sizeof(dataflash->command)); 217 command = dataflash->command; 218 219 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len); 220 debug("READ: (%x) %x %x %x\n", 221 command[0], command[1], command[2], command[3]); 222 223 /* Calculate flash page/byte address */ 224 addr = (((unsigned)offset / spi_flash->page_size) 225 << dataflash->page_offset) 226 + ((unsigned)offset % spi_flash->page_size); 227 228 status = spi_claim_bus(spi); 229 if (status) { 230 debug("dataflash: unable to claim SPI bus\n"); 231 return status; 232 } 233 234 /* 235 * Continuous read, max clock = f(car) which may be less than 236 * the peak rate available. Some chips support commands with 237 * fewer "don't care" bytes. Both buffers stay unchanged. 238 */ 239 command[0] = OP_READ_CONTINUOUS; 240 command[1] = (uint8_t)(addr >> 16); 241 command[2] = (uint8_t)(addr >> 8); 242 command[3] = (uint8_t)(addr >> 0); 243 244 /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */ 245 status = spi_flash_cmd_read(spi, command, 8, buf, len); 246 247 spi_release_bus(spi); 248 249 return status; 250 } 251 252 /* 253 * Write to the DataFlash device. 254 * offset : Start offset in flash device 255 * len : Amount to write 256 * buf : Buffer containing the data 257 */ 258 int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len, 259 const void *buf) 260 { 261 struct dataflash *dataflash; 262 struct spi_flash *spi_flash; 263 struct spi_slave *spi; 264 uint8_t *command; 265 unsigned int pageaddr, addr, to, writelen; 266 size_t remaining = len; 267 u_char *writebuf = (u_char *)buf; 268 int status = -EINVAL; 269 270 dataflash = dev_get_priv(dev); 271 spi_flash = dev_get_uclass_priv(dev); 272 spi = spi_flash->spi; 273 274 memset(dataflash->command, 0 , sizeof(dataflash->command)); 275 command = dataflash->command; 276 277 debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len)); 278 279 pageaddr = ((unsigned)offset / spi_flash->page_size); 280 to = ((unsigned)offset % spi_flash->page_size); 281 if (to + len > spi_flash->page_size) 282 writelen = spi_flash->page_size - to; 283 else 284 writelen = len; 285 286 status = spi_claim_bus(spi); 287 if (status) { 288 debug("dataflash: unable to claim SPI bus\n"); 289 return status; 290 } 291 292 while (remaining > 0) { 293 debug("write @ %d:%d len=%d\n", pageaddr, to, writelen); 294 295 /* 296 * REVISIT: 297 * (a) each page in a sector must be rewritten at least 298 * once every 10K sibling erase/program operations. 299 * (b) for pages that are already erased, we could 300 * use WRITE+MWRITE not PROGRAM for ~30% speedup. 301 * (c) WRITE to buffer could be done while waiting for 302 * a previous MWRITE/MWERASE to complete ... 303 * (d) error handling here seems to be mostly missing. 304 * 305 * Two persistent bits per page, plus a per-sector counter, 306 * could support (a) and (b) ... we might consider using 307 * the second half of sector zero, which is just one block, 308 * to track that state. (On AT91, that sector should also 309 * support boot-from-DataFlash.) 310 */ 311 312 addr = pageaddr << dataflash->page_offset; 313 314 /* (1) Maybe transfer partial page to Buffer1 */ 315 if (writelen != spi_flash->page_size) { 316 command[0] = OP_TRANSFER_BUF1; 317 command[1] = (addr & 0x00FF0000) >> 16; 318 command[2] = (addr & 0x0000FF00) >> 8; 319 command[3] = 0; 320 321 debug("TRANSFER: (%x) %x %x %x\n", 322 command[0], command[1], command[2], command[3]); 323 324 status = spi_flash_cmd_write(spi, command, 4, NULL, 0); 325 if (status < 0) { 326 debug("%s: write(<pagesize) command error!\n", 327 dev->name); 328 return -EIO; 329 } 330 331 status = dataflash_waitready(spi); 332 if (status < 0) { 333 debug("%s: write(<pagesize) waitready error!\n", 334 dev->name); 335 return status; 336 } 337 } 338 339 /* (2) Program full page via Buffer1 */ 340 addr += to; 341 command[0] = OP_PROGRAM_VIA_BUF1; 342 command[1] = (addr & 0x00FF0000) >> 16; 343 command[2] = (addr & 0x0000FF00) >> 8; 344 command[3] = (addr & 0x000000FF); 345 346 debug("PROGRAM: (%x) %x %x %x\n", 347 command[0], command[1], command[2], command[3]); 348 349 status = spi_flash_cmd_write(spi, command, 350 4, writebuf, writelen); 351 if (status < 0) { 352 debug("%s: write send command error!\n", dev->name); 353 return -EIO; 354 } 355 356 status = dataflash_waitready(spi); 357 if (status < 0) { 358 debug("%s: write waitready error!\n", dev->name); 359 return status; 360 } 361 362 #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY 363 /* (3) Compare to Buffer1 */ 364 addr = pageaddr << dataflash->page_offset; 365 command[0] = OP_COMPARE_BUF1; 366 command[1] = (addr & 0x00FF0000) >> 16; 367 command[2] = (addr & 0x0000FF00) >> 8; 368 command[3] = 0; 369 370 debug("COMPARE: (%x) %x %x %x\n", 371 command[0], command[1], command[2], command[3]); 372 373 status = spi_flash_cmd_write(spi, command, 374 4, writebuf, writelen); 375 if (status < 0) { 376 debug("%s: write(compare) send command error!\n", 377 dev->name); 378 return -EIO; 379 } 380 381 status = dataflash_waitready(spi); 382 383 /* Check result of the compare operation */ 384 if (status & (1 << 6)) { 385 printf("dataflash: write compare page %u, err %d\n", 386 pageaddr, status); 387 remaining = 0; 388 status = -EIO; 389 break; 390 } else { 391 status = 0; 392 } 393 394 #endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */ 395 remaining = remaining - writelen; 396 pageaddr++; 397 to = 0; 398 writebuf += writelen; 399 400 if (remaining > spi_flash->page_size) 401 writelen = spi_flash->page_size; 402 else 403 writelen = remaining; 404 } 405 406 spi_release_bus(spi); 407 408 return 0; 409 } 410 411 static int add_dataflash(struct udevice *dev, char *name, int nr_pages, 412 int pagesize, int pageoffset, char revision) 413 { 414 struct spi_flash *spi_flash; 415 struct dataflash *dataflash; 416 417 dataflash = dev_get_priv(dev); 418 spi_flash = dev_get_uclass_priv(dev); 419 420 dataflash->page_offset = pageoffset; 421 422 spi_flash->name = name; 423 spi_flash->page_size = pagesize; 424 spi_flash->size = nr_pages * pagesize; 425 spi_flash->erase_size = pagesize; 426 427 #ifndef CONFIG_SPL_BUILD 428 printf("SPI DataFlash: Detected %s with page size ", spi_flash->name); 429 print_size(spi_flash->page_size, ", erase size "); 430 print_size(spi_flash->erase_size, ", total "); 431 print_size(spi_flash->size, ""); 432 printf(", revision %c", revision); 433 puts("\n"); 434 #endif 435 436 return 0; 437 } 438 439 struct flash_info { 440 char *name; 441 442 /* 443 * JEDEC id has a high byte of zero plus three data bytes: 444 * the manufacturer id, then a two byte device id. 445 */ 446 uint32_t jedec_id; 447 448 /* The size listed here is what works with OP_ERASE_PAGE. */ 449 unsigned nr_pages; 450 uint16_t pagesize; 451 uint16_t pageoffset; 452 453 uint16_t flags; 454 #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */ 455 #define IS_POW2PS 0x0001 /* uses 2^N byte pages */ 456 }; 457 458 static struct flash_info dataflash_data[] = { 459 /* 460 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries, 461 * one with IS_POW2PS and the other without. The entry with the 462 * non-2^N byte page size can't name exact chip revisions without 463 * losing backwards compatibility for cmdlinepart. 464 * 465 * Those two entries have different name spelling format in order to 466 * show their difference obviously. 467 * The upper case refer to the chip isn't in normal 2^N bytes page-size 468 * mode. 469 * The lower case refer to the chip is in normal 2^N bytes page-size 470 * mode. 471 * 472 * These newer chips also support 128-byte security registers (with 473 * 64 bytes one-time-programmable) and software write-protection. 474 */ 475 { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS}, 476 { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS}, 477 478 { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS}, 479 { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS}, 480 481 { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS}, 482 { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS}, 483 484 { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS}, 485 { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS}, 486 487 { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS}, 488 { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS}, 489 490 { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */ 491 492 { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS}, 493 { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS}, 494 495 { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS}, 496 { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS}, 497 }; 498 499 static struct flash_info *jedec_probe(struct spi_slave *spi) 500 { 501 int tmp; 502 uint8_t id[5]; 503 uint32_t jedec; 504 struct flash_info *info; 505 int status; 506 507 /* 508 * JEDEC also defines an optional "extended device information" 509 * string for after vendor-specific data, after the three bytes 510 * we use here. Supporting some chips might require using it. 511 * 512 * If the vendor ID isn't Atmel's (0x1f), assume this call failed. 513 * That's not an error; only rev C and newer chips handle it, and 514 * only Atmel sells these chips. 515 */ 516 tmp = spi_flash_cmd(spi, CMD_READ_ID, id, sizeof(id)); 517 if (tmp < 0) { 518 printf("dataflash: error %d reading JEDEC ID\n", tmp); 519 return ERR_PTR(tmp); 520 } 521 if (id[0] != 0x1f) 522 return NULL; 523 524 jedec = id[0]; 525 jedec = jedec << 8; 526 jedec |= id[1]; 527 jedec = jedec << 8; 528 jedec |= id[2]; 529 530 for (tmp = 0, info = dataflash_data; 531 tmp < ARRAY_SIZE(dataflash_data); 532 tmp++, info++) { 533 if (info->jedec_id == jedec) { 534 if (info->flags & SUP_POW2PS) { 535 status = dataflash_status(spi); 536 if (status < 0) { 537 debug("dataflash: status error %d\n", 538 status); 539 return NULL; 540 } 541 if (status & 0x1) { 542 if (info->flags & IS_POW2PS) 543 return info; 544 } else { 545 if (!(info->flags & IS_POW2PS)) 546 return info; 547 } 548 } else { 549 return info; 550 } 551 } 552 } 553 554 /* 555 * Treat other chips as errors ... we won't know the right page 556 * size (it might be binary) even when we can tell which density 557 * class is involved (legacy chip id scheme). 558 */ 559 printf("dataflash: JEDEC id %06x not handled\n", jedec); 560 return ERR_PTR(-ENODEV); 561 } 562 563 /* 564 * Detect and initialize DataFlash device, using JEDEC IDs on newer chips 565 * or else the ID code embedded in the status bits: 566 * 567 * Device Density ID code #Pages PageSize Offset 568 * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9 569 * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9 570 * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9 571 * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9 572 * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10 573 * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10 574 * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11 575 * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11 576 */ 577 static int spi_dataflash_probe(struct udevice *dev) 578 { 579 struct spi_slave *spi = dev_get_parent_priv(dev); 580 struct spi_flash *spi_flash; 581 struct flash_info *info; 582 int status; 583 584 spi_flash = dev_get_uclass_priv(dev); 585 spi_flash->spi = spi; 586 spi_flash->dev = dev; 587 588 status = spi_claim_bus(spi); 589 if (status) 590 return status; 591 592 /* 593 * Try to detect dataflash by JEDEC ID. 594 * If it succeeds we know we have either a C or D part. 595 * D will support power of 2 pagesize option. 596 * Both support the security register, though with different 597 * write procedures. 598 */ 599 info = jedec_probe(spi); 600 if (IS_ERR(info)) 601 goto err_jedec_probe; 602 if (info != NULL) { 603 status = add_dataflash(dev, info->name, info->nr_pages, 604 info->pagesize, info->pageoffset, 605 (info->flags & SUP_POW2PS) ? 'd' : 'c'); 606 if (status < 0) 607 goto err_status; 608 } 609 610 /* 611 * Older chips support only legacy commands, identifing 612 * capacity using bits in the status byte. 613 */ 614 status = dataflash_status(spi); 615 if (status <= 0 || status == 0xff) { 616 printf("dataflash: read status error %d\n", status); 617 if (status == 0 || status == 0xff) 618 status = -ENODEV; 619 goto err_jedec_probe; 620 } 621 622 /* 623 * if there's a device there, assume it's dataflash. 624 * board setup should have set spi->max_speed_max to 625 * match f(car) for continuous reads, mode 0 or 3. 626 */ 627 switch (status & 0x3c) { 628 case 0x0c: /* 0 0 1 1 x x */ 629 status = add_dataflash(dev, "AT45DB011B", 512, 264, 9, 0); 630 break; 631 case 0x14: /* 0 1 0 1 x x */ 632 status = add_dataflash(dev, "AT45DB021B", 1024, 264, 9, 0); 633 break; 634 case 0x1c: /* 0 1 1 1 x x */ 635 status = add_dataflash(dev, "AT45DB041x", 2048, 264, 9, 0); 636 break; 637 case 0x24: /* 1 0 0 1 x x */ 638 status = add_dataflash(dev, "AT45DB081B", 4096, 264, 9, 0); 639 break; 640 case 0x2c: /* 1 0 1 1 x x */ 641 status = add_dataflash(dev, "AT45DB161x", 4096, 528, 10, 0); 642 break; 643 case 0x34: /* 1 1 0 1 x x */ 644 status = add_dataflash(dev, "AT45DB321x", 8192, 528, 10, 0); 645 break; 646 case 0x38: /* 1 1 1 x x x */ 647 case 0x3c: 648 status = add_dataflash(dev, "AT45DB642x", 8192, 1056, 11, 0); 649 break; 650 /* obsolete AT45DB1282 not (yet?) supported */ 651 default: 652 printf("dataflash: unsupported device (%x)\n", status & 0x3c); 653 status = -ENODEV; 654 goto err_status; 655 } 656 657 return status; 658 659 err_status: 660 spi_free_slave(spi); 661 err_jedec_probe: 662 spi_release_bus(spi); 663 return status; 664 } 665 666 static const struct dm_spi_flash_ops spi_dataflash_ops = { 667 .read = spi_dataflash_read, 668 .write = spi_dataflash_write, 669 .erase = spi_dataflash_erase, 670 }; 671 672 static const struct udevice_id spi_dataflash_ids[] = { 673 { .compatible = "atmel,at45", }, 674 { .compatible = "atmel,dataflash", }, 675 { } 676 }; 677 678 U_BOOT_DRIVER(spi_dataflash) = { 679 .name = "spi_dataflash", 680 .id = UCLASS_SPI_FLASH, 681 .of_match = spi_dataflash_ids, 682 .probe = spi_dataflash_probe, 683 .priv_auto_alloc_size = sizeof(struct dataflash), 684 .ops = &spi_dataflash_ops, 685 }; 686