1 /* 2 * Renesas RCar Gen3 RPC Hyperflash driver 3 * 4 * Copyright (C) 2016 Renesas Electronics Corporation 5 * Copyright (C) 2016 Cogent Embedded, Inc. 6 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <clk.h> 14 #include <dm.h> 15 #include <dm/of_access.h> 16 #include <errno.h> 17 #include <fdt_support.h> 18 #include <flash.h> 19 #include <mtd.h> 20 #include <wait_bit.h> 21 #include <mtd/cfi_flash.h> 22 23 #define RPC_CMNCR 0x0000 /* R/W */ 24 #define RPC_CMNCR_MD BIT(31) 25 #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) 26 #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) 27 #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) 28 #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) 29 #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \ 30 RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3)) 31 #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8) 32 #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12) 33 #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14) 34 #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \ 35 RPC_CMNCR_IO3FV(3)) 36 #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0) 37 38 #define RPC_SSLDR 0x0004 /* R/W */ 39 #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16) 40 #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8) 41 #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0) 42 43 #define RPC_DRCR 0x000C /* R/W */ 44 #define RPC_DRCR_SSLN BIT(24) 45 #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16) 46 #define RPC_DRCR_RCF BIT(9) 47 #define RPC_DRCR_RBE BIT(8) 48 #define RPC_DRCR_SSLE BIT(0) 49 50 #define RPC_DRCMR 0x0010 /* R/W */ 51 #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16) 52 #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0) 53 54 #define RPC_DREAR 0x0014 /* R/W */ 55 #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16) 56 #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0) 57 58 #define RPC_DROPR 0x0018 /* R/W */ 59 #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24) 60 #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16) 61 #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8) 62 #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0) 63 64 #define RPC_DRENR 0x001C /* R/W */ 65 #define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30)) 66 #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28) 67 #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24) 68 #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20) 69 #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16) 70 #define RPC_DRENR_DME BIT(15) 71 #define RPC_DRENR_CDE BIT(14) 72 #define RPC_DRENR_OCDE BIT(12) 73 #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8) 74 #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4) 75 76 #define RPC_SMCR 0x0020 /* R/W */ 77 #define RPC_SMCR_SSLKP BIT(8) 78 #define RPC_SMCR_SPIRE BIT(2) 79 #define RPC_SMCR_SPIWE BIT(1) 80 #define RPC_SMCR_SPIE BIT(0) 81 82 #define RPC_SMCMR 0x0024 /* R/W */ 83 #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16) 84 #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0) 85 86 #define RPC_SMADR 0x0028 /* R/W */ 87 #define RPC_SMOPR 0x002C /* R/W */ 88 #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0) 89 #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8) 90 #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16) 91 #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24) 92 93 #define RPC_SMENR 0x0030 /* R/W */ 94 #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30) 95 #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28) 96 #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24) 97 #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20) 98 #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16) 99 #define RPC_SMENR_DME BIT(15) 100 #define RPC_SMENR_CDE BIT(14) 101 #define RPC_SMENR_OCDE BIT(12) 102 #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8) 103 #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4) 104 #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0) 105 106 #define RPC_SMRDR0 0x0038 /* R */ 107 #define RPC_SMRDR1 0x003C /* R */ 108 #define RPC_SMWDR0 0x0040 /* R/W */ 109 #define RPC_SMWDR1 0x0044 /* R/W */ 110 #define RPC_CMNSR 0x0048 /* R */ 111 #define RPC_CMNSR_SSLF BIT(1) 112 #define RPC_CMNSR_TEND BIT(0) 113 114 #define RPC_DRDMCR 0x0058 /* R/W */ 115 #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0) 116 117 #define RPC_DRDRENR 0x005C /* R/W */ 118 #define RPC_DRDRENR_HYPE (0x5 << 12) 119 #define RPC_DRDRENR_ADDRE BIT(8) 120 #define RPC_DRDRENR_OPDRE BIT(4) 121 #define RPC_DRDRENR_DRDRE BIT(0) 122 123 #define RPC_SMDMCR 0x0060 /* R/W */ 124 #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0) 125 126 #define RPC_SMDRENR 0x0064 /* R/W */ 127 #define RPC_SMDRENR_HYPE (0x5 << 12) 128 #define RPC_SMDRENR_ADDRE BIT(8) 129 #define RPC_SMDRENR_OPDRE BIT(4) 130 #define RPC_SMDRENR_SPIDRE BIT(0) 131 132 #define RPC_PHYCNT 0x007C /* R/W */ 133 #define RPC_PHYCNT_CAL BIT(31) 134 #define PRC_PHYCNT_OCTA_AA BIT(22) 135 #define PRC_PHYCNT_OCTA_SA BIT(23) 136 #define PRC_PHYCNT_EXDS BIT(21) 137 #define RPC_PHYCNT_OCT BIT(20) 138 #define RPC_PHYCNT_WBUF2 BIT(4) 139 #define RPC_PHYCNT_WBUF BIT(2) 140 #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) 141 142 #define RPC_PHYINT 0x0088 /* R/W */ 143 #define RPC_PHYINT_RSTEN BIT(18) 144 #define RPC_PHYINT_WPEN BIT(17) 145 #define RPC_PHYINT_INTEN BIT(16) 146 #define RPC_PHYINT_RST BIT(2) 147 #define RPC_PHYINT_WP BIT(1) 148 #define RPC_PHYINT_INT BIT(0) 149 150 #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */ 151 #define RPC_WBUF_SIZE 0x100 152 153 static phys_addr_t rpc_base; 154 155 enum rpc_hf_size { 156 RPC_HF_SIZE_16BIT = RPC_SMENR_SPIDE(0x8), 157 RPC_HF_SIZE_32BIT = RPC_SMENR_SPIDE(0xC), 158 RPC_HF_SIZE_64BIT = RPC_SMENR_SPIDE(0xF), 159 }; 160 161 static int rpc_hf_wait_tend(void) 162 { 163 void __iomem *reg = (void __iomem *)rpc_base + RPC_CMNSR; 164 return wait_for_bit_le32(reg, RPC_CMNSR_TEND, true, 1000, 0); 165 } 166 167 static int rpc_hf_mode(bool man) 168 { 169 int ret; 170 171 ret = rpc_hf_wait_tend(); 172 if (ret) 173 return ret; 174 175 clrsetbits_le32(rpc_base + RPC_PHYCNT, 176 RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 | 177 RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3), 178 RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3)); 179 180 clrsetbits_le32(rpc_base + RPC_CMNCR, 181 RPC_CMNCR_MD | RPC_CMNCR_BSZ(3), 182 RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | 183 (man ? RPC_CMNCR_MD : 0) | RPC_CMNCR_BSZ(1)); 184 185 if (man) 186 return 0; 187 188 writel(RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF | RPC_DRCR_RBE, 189 rpc_base + RPC_DRCR); 190 191 writel(RPC_DRCMR_CMD(0xA0), rpc_base + RPC_DRCMR); 192 writel(RPC_DRENR_CDB(2) | RPC_DRENR_OCDB(2) | RPC_DRENR_ADB(2) | 193 RPC_DRENR_SPIDB(2) | RPC_DRENR_CDE | RPC_DRENR_OCDE | 194 RPC_DRENR_ADE(4), rpc_base + RPC_DRENR); 195 writel(RPC_DRDMCR_DMCYC(0xE), rpc_base + RPC_DRDMCR); 196 writel(RPC_DRDRENR_HYPE | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE, 197 rpc_base + RPC_DRDRENR); 198 199 /* Dummy read */ 200 readl(rpc_base + RPC_DRCR); 201 202 return 0; 203 } 204 205 static int rpc_hf_xfer(void *addr, u64 wdata, u64 *rdata, 206 enum rpc_hf_size size, bool write) 207 { 208 int ret; 209 u32 val; 210 211 ret = rpc_hf_mode(1); 212 if (ret) 213 return ret; 214 215 /* Submit HF address, SMCMR CMD[7] ~= CA Bit# 47 (R/nW) */ 216 writel(write ? 0 : RPC_SMCMR_CMD(0x80), rpc_base + RPC_SMCMR); 217 writel((uintptr_t)addr >> 1, rpc_base + RPC_SMADR); 218 writel(0x0, rpc_base + RPC_SMOPR); 219 220 writel(RPC_SMDRENR_HYPE | RPC_SMDRENR_ADDRE | RPC_SMDRENR_SPIDRE, 221 rpc_base + RPC_SMDRENR); 222 223 val = RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) | 224 RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) | 225 RPC_SMENR_CDE | RPC_SMENR_OCDE | RPC_SMENR_ADE(4) | size; 226 227 if (write) { 228 writel(val, rpc_base + RPC_SMENR); 229 230 if (size == RPC_HF_SIZE_64BIT) 231 writeq(cpu_to_be64(wdata), rpc_base + RPC_SMWDR0); 232 else 233 writel(cpu_to_be32(wdata), rpc_base + RPC_SMWDR0); 234 235 writel(RPC_SMCR_SPIWE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR); 236 } else { 237 val |= RPC_SMENR_DME; 238 239 writel(RPC_SMDMCR_DMCYC(0xE), rpc_base + RPC_SMDMCR); 240 241 writel(val, rpc_base + RPC_SMENR); 242 243 writel(RPC_SMCR_SPIRE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR); 244 245 ret = rpc_hf_wait_tend(); 246 if (ret) 247 return ret; 248 249 if (size == RPC_HF_SIZE_64BIT) 250 *rdata = be64_to_cpu(readq(rpc_base + RPC_SMRDR0)); 251 else 252 *rdata = be32_to_cpu(readl(rpc_base + RPC_SMRDR0)); 253 } 254 255 return rpc_hf_mode(0); 256 } 257 258 static void rpc_hf_write_cmd(void *addr, u64 wdata, enum rpc_hf_size size) 259 { 260 int ret; 261 262 ret = rpc_hf_xfer(addr, wdata, NULL, size, 1); 263 if (ret) 264 printf("RPC: Write failed, ret=%i\n", ret); 265 } 266 267 static u64 rpc_hf_read_reg(void *addr, enum rpc_hf_size size) 268 { 269 u64 rdata = 0; 270 int ret; 271 272 ret = rpc_hf_xfer(addr, 0, &rdata, size, 0); 273 if (ret) 274 printf("RPC: Read failed, ret=%i\n", ret); 275 276 return rdata; 277 } 278 279 void flash_write8(u8 value, void *addr) 280 { 281 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT); 282 } 283 284 void flash_write16(u16 value, void *addr) 285 { 286 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT); 287 } 288 289 void flash_write32(u32 value, void *addr) 290 { 291 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_32BIT); 292 } 293 294 void flash_write64(u64 value, void *addr) 295 { 296 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_64BIT); 297 } 298 299 u8 flash_read8(void *addr) 300 { 301 return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT); 302 } 303 304 u16 flash_read16(void *addr) 305 { 306 return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT); 307 } 308 309 u32 flash_read32(void *addr) 310 { 311 return rpc_hf_read_reg(addr, RPC_HF_SIZE_32BIT); 312 } 313 314 u64 flash_read64(void *addr) 315 { 316 return rpc_hf_read_reg(addr, RPC_HF_SIZE_64BIT); 317 } 318 319 static int rpc_hf_bind(struct udevice *parent) 320 { 321 const void *fdt = gd->fdt_blob; 322 ofnode node; 323 int ret, off; 324 325 /* 326 * Check if there are any SPI NOR child nodes, if so, do NOT bind 327 * as this controller will be operated by the QSPI driver instead. 328 */ 329 dev_for_each_subnode(node, parent) { 330 off = ofnode_to_offset(node); 331 332 ret = fdt_node_check_compatible(fdt, off, "spi-flash"); 333 if (!ret) 334 return -ENODEV; 335 336 ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor"); 337 if (!ret) 338 return -ENODEV; 339 } 340 341 return 0; 342 } 343 344 static int rpc_hf_probe(struct udevice *dev) 345 { 346 void *blob = (void *)gd->fdt_blob; 347 const fdt32_t *cell; 348 int node = dev_of_offset(dev); 349 int parent, addrc, sizec, len, ret; 350 struct clk clk; 351 phys_addr_t flash_base; 352 353 parent = fdt_parent_offset(blob, node); 354 fdt_support_default_count_cells(blob, parent, &addrc, &sizec); 355 cell = fdt_getprop(blob, node, "reg", &len); 356 if (!cell) 357 return -ENOENT; 358 359 if (addrc != 2 || sizec != 2) 360 return -EINVAL; 361 362 363 ret = clk_get_by_index(dev, 0, &clk); 364 if (ret < 0) { 365 dev_err(dev, "Failed to get RPC clock\n"); 366 return ret; 367 } 368 369 ret = clk_enable(&clk); 370 clk_free(&clk); 371 if (ret) { 372 dev_err(dev, "Failed to enable RPC clock\n"); 373 return ret; 374 } 375 376 rpc_base = fdt_translate_address(blob, node, cell); 377 flash_base = fdt_translate_address(blob, node, cell + addrc + sizec); 378 379 flash_info[0].dev = dev; 380 flash_info[0].base = flash_base; 381 cfi_flash_num_flash_banks = 1; 382 gd->bd->bi_flashstart = flash_base; 383 384 return 0; 385 } 386 387 static const struct udevice_id rpc_hf_ids[] = { 388 { .compatible = "renesas,rpc" }, 389 {} 390 }; 391 392 U_BOOT_DRIVER(rpc_hf) = { 393 .name = "rpc_hf", 394 .id = UCLASS_MTD, 395 .of_match = rpc_hf_ids, 396 .bind = rpc_hf_bind, 397 .probe = rpc_hf_probe, 398 }; 399