1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others 4 * 5 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver. 6 * Ported to U-Boot by Stefan Agner 7 * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir 8 * Jason ported to M54418TWR and MVFA5. 9 * Authors: Stefan Agner <stefan.agner@toradex.com> 10 * Bill Pringlemeir <bpringlemeir@nbsps.com> 11 * Shaohui Xie <b21989@freescale.com> 12 * Jason Jin <Jason.jin@freescale.com> 13 * 14 * Based on original driver mpc5121_nfc.c. 15 * 16 * Limitations: 17 * - Untested on MPC5125 and M54418. 18 * - DMA and pipelining not used. 19 * - 2K pages or less. 20 * - HW ECC: Only 2K page with 64+ OOB. 21 * - HW ECC: Only 24 and 32-bit error correction implemented. 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 27 #include <linux/mtd/mtd.h> 28 #include <linux/mtd/rawnand.h> 29 #include <linux/mtd/partitions.h> 30 31 #include <nand.h> 32 #include <errno.h> 33 #include <asm/io.h> 34 35 /* Register Offsets */ 36 #define NFC_FLASH_CMD1 0x3F00 37 #define NFC_FLASH_CMD2 0x3F04 38 #define NFC_COL_ADDR 0x3F08 39 #define NFC_ROW_ADDR 0x3F0c 40 #define NFC_ROW_ADDR_INC 0x3F14 41 #define NFC_FLASH_STATUS1 0x3F18 42 #define NFC_FLASH_STATUS2 0x3F1c 43 #define NFC_CACHE_SWAP 0x3F28 44 #define NFC_SECTOR_SIZE 0x3F2c 45 #define NFC_FLASH_CONFIG 0x3F30 46 #define NFC_IRQ_STATUS 0x3F38 47 48 /* Addresses for NFC MAIN RAM BUFFER areas */ 49 #define NFC_MAIN_AREA(n) ((n) * 0x1000) 50 51 #define PAGE_2K 0x0800 52 #define OOB_64 0x0040 53 #define OOB_MAX 0x0100 54 55 /* 56 * NFC_CMD2[CODE] values. See section: 57 * - 31.4.7 Flash Command Code Description, Vybrid manual 58 * - 23.8.6 Flash Command Sequencer, MPC5125 manual 59 * 60 * Briefly these are bitmasks of controller cycles. 61 */ 62 #define READ_PAGE_CMD_CODE 0x7EE0 63 #define READ_ONFI_PARAM_CMD_CODE 0x4860 64 #define PROGRAM_PAGE_CMD_CODE 0x7FC0 65 #define ERASE_CMD_CODE 0x4EC0 66 #define READ_ID_CMD_CODE 0x4804 67 #define RESET_CMD_CODE 0x4040 68 #define STATUS_READ_CMD_CODE 0x4068 69 70 /* NFC ECC mode define */ 71 #define ECC_BYPASS 0 72 #define ECC_45_BYTE 6 73 #define ECC_60_BYTE 7 74 75 /*** Register Mask and bit definitions */ 76 77 /* NFC_FLASH_CMD1 Field */ 78 #define CMD_BYTE2_MASK 0xFF000000 79 #define CMD_BYTE2_SHIFT 24 80 81 /* NFC_FLASH_CM2 Field */ 82 #define CMD_BYTE1_MASK 0xFF000000 83 #define CMD_BYTE1_SHIFT 24 84 #define CMD_CODE_MASK 0x00FFFF00 85 #define CMD_CODE_SHIFT 8 86 #define BUFNO_MASK 0x00000006 87 #define BUFNO_SHIFT 1 88 #define START_BIT (1<<0) 89 90 /* NFC_COL_ADDR Field */ 91 #define COL_ADDR_MASK 0x0000FFFF 92 #define COL_ADDR_SHIFT 0 93 94 /* NFC_ROW_ADDR Field */ 95 #define ROW_ADDR_MASK 0x00FFFFFF 96 #define ROW_ADDR_SHIFT 0 97 #define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 98 #define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 99 #define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 100 #define ROW_ADDR_CHIP_SEL_SHIFT 24 101 102 /* NFC_FLASH_STATUS2 Field */ 103 #define STATUS_BYTE1_MASK 0x000000FF 104 105 /* NFC_FLASH_CONFIG Field */ 106 #define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 107 #define CONFIG_ECC_SRAM_ADDR_SHIFT 22 108 #define CONFIG_ECC_SRAM_REQ_BIT (1<<21) 109 #define CONFIG_DMA_REQ_BIT (1<<20) 110 #define CONFIG_ECC_MODE_MASK 0x000E0000 111 #define CONFIG_ECC_MODE_SHIFT 17 112 #define CONFIG_FAST_FLASH_BIT (1<<16) 113 #define CONFIG_16BIT (1<<7) 114 #define CONFIG_BOOT_MODE_BIT (1<<6) 115 #define CONFIG_ADDR_AUTO_INCR_BIT (1<<5) 116 #define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4) 117 #define CONFIG_PAGE_CNT_MASK 0xF 118 #define CONFIG_PAGE_CNT_SHIFT 0 119 120 /* NFC_IRQ_STATUS Field */ 121 #define IDLE_IRQ_BIT (1<<29) 122 #define IDLE_EN_BIT (1<<20) 123 #define CMD_DONE_CLEAR_BIT (1<<18) 124 #define IDLE_CLEAR_BIT (1<<17) 125 126 #define NFC_TIMEOUT (1000) 127 128 /* 129 * ECC status - seems to consume 8 bytes (double word). The documented 130 * status byte is located in the lowest byte of the second word (which is 131 * the 4th or 7th byte depending on endianness). 132 * Calculate an offset to store the ECC status at the end of the buffer. 133 */ 134 #define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8) 135 136 #define ECC_STATUS 0x4 137 #define ECC_STATUS_MASK 0x80 138 #define ECC_STATUS_ERR_COUNT 0x3F 139 140 enum vf610_nfc_alt_buf { 141 ALT_BUF_DATA = 0, 142 ALT_BUF_ID = 1, 143 ALT_BUF_STAT = 2, 144 ALT_BUF_ONFI = 3, 145 }; 146 147 struct vf610_nfc { 148 struct nand_chip chip; 149 void __iomem *regs; 150 uint buf_offset; 151 int write_sz; 152 /* Status and ID are in alternate locations. */ 153 enum vf610_nfc_alt_buf alt_buf; 154 }; 155 156 #define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd)) 157 158 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES) 159 #define ECC_HW_MODE ECC_45_BYTE 160 161 static struct nand_ecclayout vf610_nfc_ecc = { 162 .eccbytes = 45, 163 .eccpos = {19, 20, 21, 22, 23, 164 24, 25, 26, 27, 28, 29, 30, 31, 165 32, 33, 34, 35, 36, 37, 38, 39, 166 40, 41, 42, 43, 44, 45, 46, 47, 167 48, 49, 50, 51, 52, 53, 54, 55, 168 56, 57, 58, 59, 60, 61, 62, 63}, 169 .oobfree = { 170 {.offset = 2, 171 .length = 17} } 172 }; 173 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES) 174 #define ECC_HW_MODE ECC_60_BYTE 175 176 static struct nand_ecclayout vf610_nfc_ecc = { 177 .eccbytes = 60, 178 .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11, 179 12, 13, 14, 15, 16, 17, 18, 19, 180 20, 21, 22, 23, 24, 25, 26, 27, 181 28, 29, 30, 31, 32, 33, 34, 35, 182 36, 37, 38, 39, 40, 41, 42, 43, 183 44, 45, 46, 47, 48, 49, 50, 51, 184 52, 53, 54, 55, 56, 57, 58, 59, 185 60, 61, 62, 63 }, 186 .oobfree = { 187 {.offset = 2, 188 .length = 2} } 189 }; 190 #endif 191 192 static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg) 193 { 194 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 195 196 return readl(nfc->regs + reg); 197 } 198 199 static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val) 200 { 201 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 202 203 writel(val, nfc->regs + reg); 204 } 205 206 static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits) 207 { 208 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits); 209 } 210 211 static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits) 212 { 213 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits); 214 } 215 216 static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg, 217 u32 mask, u32 shift, u32 val) 218 { 219 vf610_nfc_write(mtd, reg, 220 (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift); 221 } 222 223 static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n) 224 { 225 /* 226 * Use this accessor for the internal SRAM buffers. On the ARM 227 * Freescale Vybrid SoC it's known that the driver can treat 228 * the SRAM buffer as if it's memory. Other platform might need 229 * to treat the buffers differently. 230 * 231 * For the time being, use memcpy 232 */ 233 memcpy(dst, src, n); 234 } 235 236 /* Clear flags for upcoming command */ 237 static inline void vf610_nfc_clear_status(void __iomem *regbase) 238 { 239 void __iomem *reg = regbase + NFC_IRQ_STATUS; 240 u32 tmp = __raw_readl(reg); 241 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT; 242 __raw_writel(tmp, reg); 243 } 244 245 /* Wait for complete operation */ 246 static void vf610_nfc_done(struct mtd_info *mtd) 247 { 248 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 249 uint start; 250 251 /* 252 * Barrier is needed after this write. This write need 253 * to be done before reading the next register the first 254 * time. 255 * vf610_nfc_set implicates such a barrier by using writel 256 * to write to the register. 257 */ 258 vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT); 259 260 start = get_timer(0); 261 262 while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) { 263 if (get_timer(start) > NFC_TIMEOUT) { 264 printf("Timeout while waiting for IDLE.\n"); 265 return; 266 } 267 } 268 vf610_nfc_clear_status(nfc->regs); 269 } 270 271 static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col) 272 { 273 u32 flash_id; 274 275 if (col < 4) { 276 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1); 277 flash_id >>= (3 - col) * 8; 278 } else { 279 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2); 280 flash_id >>= 24; 281 } 282 283 return flash_id & 0xff; 284 } 285 286 static u8 vf610_nfc_get_status(struct mtd_info *mtd) 287 { 288 return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK; 289 } 290 291 /* Single command */ 292 static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1, 293 u32 cmd_code) 294 { 295 void __iomem *reg = regbase + NFC_FLASH_CMD2; 296 u32 tmp; 297 vf610_nfc_clear_status(regbase); 298 299 tmp = __raw_readl(reg); 300 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK); 301 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT; 302 tmp |= cmd_code << CMD_CODE_SHIFT; 303 __raw_writel(tmp, reg); 304 } 305 306 /* Two commands */ 307 static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1, 308 u32 cmd_byte2, u32 cmd_code) 309 { 310 void __iomem *reg = regbase + NFC_FLASH_CMD1; 311 u32 tmp; 312 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code); 313 314 tmp = __raw_readl(reg); 315 tmp &= ~CMD_BYTE2_MASK; 316 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT; 317 __raw_writel(tmp, reg); 318 } 319 320 static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) 321 { 322 if (column != -1) { 323 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 324 if (nfc->chip.options & NAND_BUSWIDTH_16) 325 column = column / 2; 326 vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK, 327 COL_ADDR_SHIFT, column); 328 } 329 if (page != -1) 330 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, 331 ROW_ADDR_SHIFT, page); 332 } 333 334 static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode) 335 { 336 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, 337 CONFIG_ECC_MODE_MASK, 338 CONFIG_ECC_MODE_SHIFT, ecc_mode); 339 } 340 341 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size) 342 { 343 __raw_writel(size, regbase + NFC_SECTOR_SIZE); 344 } 345 346 /* Send command to NAND chip */ 347 static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, 348 int column, int page) 349 { 350 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 351 int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0; 352 353 nfc->buf_offset = max(column, 0); 354 nfc->alt_buf = ALT_BUF_DATA; 355 356 switch (command) { 357 case NAND_CMD_SEQIN: 358 /* Use valid column/page from preread... */ 359 vf610_nfc_addr_cycle(mtd, column, page); 360 nfc->buf_offset = 0; 361 362 /* 363 * SEQIN => data => PAGEPROG sequence is done by the controller 364 * hence we do not need to issue the command here... 365 */ 366 return; 367 case NAND_CMD_PAGEPROG: 368 trfr_sz += nfc->write_sz; 369 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE); 370 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 371 vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN, 372 command, PROGRAM_PAGE_CMD_CODE); 373 break; 374 375 case NAND_CMD_RESET: 376 vf610_nfc_transfer_size(nfc->regs, 0); 377 vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE); 378 break; 379 380 case NAND_CMD_READOOB: 381 trfr_sz += mtd->oobsize; 382 column = mtd->writesize; 383 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 384 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, 385 NAND_CMD_READSTART, READ_PAGE_CMD_CODE); 386 vf610_nfc_addr_cycle(mtd, column, page); 387 vf610_nfc_ecc_mode(mtd, ECC_BYPASS); 388 break; 389 390 case NAND_CMD_READ0: 391 trfr_sz += mtd->writesize + mtd->oobsize; 392 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 393 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE); 394 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, 395 NAND_CMD_READSTART, READ_PAGE_CMD_CODE); 396 vf610_nfc_addr_cycle(mtd, column, page); 397 break; 398 399 case NAND_CMD_PARAM: 400 nfc->alt_buf = ALT_BUF_ONFI; 401 trfr_sz = 3 * sizeof(struct nand_onfi_params); 402 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 403 vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM, 404 READ_ONFI_PARAM_CMD_CODE); 405 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, 406 ROW_ADDR_SHIFT, column); 407 vf610_nfc_ecc_mode(mtd, ECC_BYPASS); 408 break; 409 410 case NAND_CMD_ERASE1: 411 vf610_nfc_transfer_size(nfc->regs, 0); 412 vf610_nfc_send_commands(nfc->regs, command, 413 NAND_CMD_ERASE2, ERASE_CMD_CODE); 414 vf610_nfc_addr_cycle(mtd, column, page); 415 break; 416 417 case NAND_CMD_READID: 418 nfc->alt_buf = ALT_BUF_ID; 419 nfc->buf_offset = 0; 420 vf610_nfc_transfer_size(nfc->regs, 0); 421 vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE); 422 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, 423 ROW_ADDR_SHIFT, column); 424 break; 425 426 case NAND_CMD_STATUS: 427 nfc->alt_buf = ALT_BUF_STAT; 428 vf610_nfc_transfer_size(nfc->regs, 0); 429 vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE); 430 break; 431 default: 432 return; 433 } 434 435 vf610_nfc_done(mtd); 436 437 nfc->write_sz = 0; 438 } 439 440 /* Read data from NFC buffers */ 441 static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) 442 { 443 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 444 uint c = nfc->buf_offset; 445 446 /* Alternate buffers are only supported through read_byte */ 447 if (nfc->alt_buf) 448 return; 449 450 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len); 451 452 nfc->buf_offset += len; 453 } 454 455 /* Write data to NFC buffers */ 456 static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, 457 int len) 458 { 459 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 460 uint c = nfc->buf_offset; 461 uint l; 462 463 l = min_t(uint, len, mtd->writesize + mtd->oobsize - c); 464 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); 465 466 nfc->write_sz += l; 467 nfc->buf_offset += l; 468 } 469 470 /* Read byte from NFC buffers */ 471 static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd) 472 { 473 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 474 u8 tmp; 475 uint c = nfc->buf_offset; 476 477 switch (nfc->alt_buf) { 478 case ALT_BUF_ID: 479 tmp = vf610_nfc_get_id(mtd, c); 480 break; 481 case ALT_BUF_STAT: 482 tmp = vf610_nfc_get_status(mtd); 483 break; 484 #ifdef __LITTLE_ENDIAN 485 case ALT_BUF_ONFI: 486 /* Reverse byte since the controller uses big endianness */ 487 c = nfc->buf_offset ^ 0x3; 488 /* fall-through */ 489 #endif 490 default: 491 tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c)); 492 break; 493 } 494 nfc->buf_offset++; 495 return tmp; 496 } 497 498 /* Read word from NFC buffers */ 499 static u16 vf610_nfc_read_word(struct mtd_info *mtd) 500 { 501 u16 tmp; 502 503 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp)); 504 return tmp; 505 } 506 507 /* If not provided, upper layers apply a fixed delay. */ 508 static int vf610_nfc_dev_ready(struct mtd_info *mtd) 509 { 510 /* NFC handles R/B internally; always ready. */ 511 return 1; 512 } 513 514 /* 515 * This function supports Vybrid only (MPC5125 would have full RB and four CS) 516 */ 517 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) 518 { 519 #ifdef CONFIG_VF610 520 u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR); 521 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK); 522 523 if (chip >= 0) { 524 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT; 525 tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT; 526 } 527 528 vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp); 529 #endif 530 } 531 532 /* Count the number of 0's in buff upto max_bits */ 533 static inline int count_written_bits(uint8_t *buff, int size, int max_bits) 534 { 535 uint32_t *buff32 = (uint32_t *)buff; 536 int k, written_bits = 0; 537 538 for (k = 0; k < (size / 4); k++) { 539 written_bits += hweight32(~buff32[k]); 540 if (written_bits > max_bits) 541 break; 542 } 543 544 return written_bits; 545 } 546 547 static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat, 548 uint8_t *oob, int page) 549 { 550 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 551 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS; 552 u8 ecc_status; 553 u8 ecc_count; 554 int flips; 555 int flips_threshold = nfc->chip.ecc.strength / 2; 556 557 ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff; 558 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT; 559 560 if (!(ecc_status & ECC_STATUS_MASK)) 561 return ecc_count; 562 563 /* Read OOB without ECC unit enabled */ 564 vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page); 565 vf610_nfc_read_buf(mtd, oob, mtd->oobsize); 566 567 /* 568 * On an erased page, bit count (including OOB) should be zero or 569 * at least less then half of the ECC strength. 570 */ 571 flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold); 572 flips += count_written_bits(oob, mtd->oobsize, flips_threshold); 573 574 if (unlikely(flips > flips_threshold)) 575 return -EINVAL; 576 577 /* Erased page. */ 578 memset(dat, 0xff, nfc->chip.ecc.size); 579 memset(oob, 0xff, mtd->oobsize); 580 return flips; 581 } 582 583 static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, 584 uint8_t *buf, int oob_required, int page) 585 { 586 int eccsize = chip->ecc.size; 587 int stat; 588 589 vf610_nfc_read_buf(mtd, buf, eccsize); 590 if (oob_required) 591 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); 592 593 stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page); 594 595 if (stat < 0) { 596 mtd->ecc_stats.failed++; 597 return 0; 598 } else { 599 mtd->ecc_stats.corrected += stat; 600 return stat; 601 } 602 } 603 604 /* 605 * ECC will be calculated automatically 606 */ 607 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, 608 const uint8_t *buf, int oob_required, int page) 609 { 610 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 611 612 vf610_nfc_write_buf(mtd, buf, mtd->writesize); 613 if (oob_required) 614 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize); 615 616 /* Always write whole page including OOB due to HW ECC */ 617 nfc->write_sz = mtd->writesize + mtd->oobsize; 618 619 return 0; 620 } 621 622 struct vf610_nfc_config { 623 int hardware_ecc; 624 int width; 625 int flash_bbt; 626 }; 627 628 static int vf610_nfc_nand_init(int devnum, void __iomem *addr) 629 { 630 struct mtd_info *mtd; 631 struct nand_chip *chip; 632 struct vf610_nfc *nfc; 633 int err = 0; 634 struct vf610_nfc_config cfg = { 635 .hardware_ecc = 1, 636 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT 637 .width = 16, 638 #else 639 .width = 8, 640 #endif 641 .flash_bbt = 1, 642 }; 643 644 nfc = malloc(sizeof(*nfc)); 645 if (!nfc) { 646 printf(KERN_ERR "%s: Memory exhausted!\n", __func__); 647 return -ENOMEM; 648 } 649 650 chip = &nfc->chip; 651 nfc->regs = addr; 652 653 mtd = nand_to_mtd(chip); 654 nand_set_controller_data(chip, nfc); 655 656 if (cfg.width == 16) 657 chip->options |= NAND_BUSWIDTH_16; 658 659 chip->dev_ready = vf610_nfc_dev_ready; 660 chip->cmdfunc = vf610_nfc_command; 661 chip->read_byte = vf610_nfc_read_byte; 662 chip->read_word = vf610_nfc_read_word; 663 chip->read_buf = vf610_nfc_read_buf; 664 chip->write_buf = vf610_nfc_write_buf; 665 chip->select_chip = vf610_nfc_select_chip; 666 667 chip->options |= NAND_NO_SUBPAGE_WRITE; 668 669 chip->ecc.size = PAGE_2K; 670 671 /* Set configuration register. */ 672 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); 673 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); 674 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); 675 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); 676 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); 677 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); 678 679 /* Disable virtual pages, only one elementary transfer unit */ 680 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, 681 CONFIG_PAGE_CNT_SHIFT, 1); 682 683 /* first scan to find the device and get the page size */ 684 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) { 685 err = -ENXIO; 686 goto error; 687 } 688 689 if (cfg.width == 16) 690 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); 691 692 /* Bad block options. */ 693 if (cfg.flash_bbt) 694 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB | 695 NAND_BBT_CREATE; 696 697 /* Single buffer only, max 256 OOB minus ECC status */ 698 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) { 699 dev_err(nfc->dev, "Unsupported flash page size\n"); 700 err = -ENXIO; 701 goto error; 702 } 703 704 if (cfg.hardware_ecc) { 705 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { 706 dev_err(nfc->dev, "Unsupported flash with hwecc\n"); 707 err = -ENXIO; 708 goto error; 709 } 710 711 if (chip->ecc.size != mtd->writesize) { 712 dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size); 713 dev_err(nfc->dev, "Step size needs to be page size\n"); 714 err = -ENXIO; 715 goto error; 716 } 717 718 /* Current HW ECC layouts only use 64 bytes of OOB */ 719 if (mtd->oobsize > 64) 720 mtd->oobsize = 64; 721 722 /* propagate ecc.layout to mtd_info */ 723 mtd->ecclayout = chip->ecc.layout; 724 chip->ecc.read_page = vf610_nfc_read_page; 725 chip->ecc.write_page = vf610_nfc_write_page; 726 chip->ecc.mode = NAND_ECC_HW; 727 728 chip->ecc.size = PAGE_2K; 729 chip->ecc.layout = &vf610_nfc_ecc; 730 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES) 731 chip->ecc.strength = 24; 732 chip->ecc.bytes = 45; 733 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES) 734 chip->ecc.strength = 32; 735 chip->ecc.bytes = 60; 736 #endif 737 738 /* Set ECC_STATUS offset */ 739 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, 740 CONFIG_ECC_SRAM_ADDR_MASK, 741 CONFIG_ECC_SRAM_ADDR_SHIFT, 742 ECC_SRAM_ADDR >> 3); 743 744 /* Enable ECC status in SRAM */ 745 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); 746 } 747 748 /* second phase scan */ 749 err = nand_scan_tail(mtd); 750 if (err) 751 return err; 752 753 err = nand_register(devnum, mtd); 754 if (err) 755 return err; 756 757 return 0; 758 759 error: 760 return err; 761 } 762 763 void board_nand_init(void) 764 { 765 int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE); 766 if (err) 767 printf("VF610 NAND init failed (err %d)\n", err); 768 } 769