1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/mtd/nand/raw/pxa3xx_nand.c 4 * 5 * Copyright © 2005 Intel Corporation 6 * Copyright © 2006 Marvell International Ltd. 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <nand.h> 13 #include <linux/errno.h> 14 #include <asm/io.h> 15 #include <asm/arch/cpu.h> 16 #include <linux/mtd/mtd.h> 17 #include <linux/mtd/rawnand.h> 18 #include <linux/types.h> 19 20 #include "pxa3xx_nand.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #define TIMEOUT_DRAIN_FIFO 5 /* in ms */ 25 #define CHIP_DELAY_TIMEOUT 200 26 #define NAND_STOP_DELAY 40 27 28 /* 29 * Define a buffer size for the initial command that detects the flash device: 30 * STATUS, READID and PARAM. 31 * ONFI param page is 256 bytes, and there are three redundant copies 32 * to be read. JEDEC param page is 512 bytes, and there are also three 33 * redundant copies to be read. 34 * Hence this buffer should be at least 512 x 3. Let's pick 2048. 35 */ 36 #define INIT_BUFFER_SIZE 2048 37 38 /* registers and bit definitions */ 39 #define NDCR (0x00) /* Control register */ 40 #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ 41 #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */ 42 #define NDSR (0x14) /* Status Register */ 43 #define NDPCR (0x18) /* Page Count Register */ 44 #define NDBDR0 (0x1C) /* Bad Block Register 0 */ 45 #define NDBDR1 (0x20) /* Bad Block Register 1 */ 46 #define NDECCCTRL (0x28) /* ECC control */ 47 #define NDDB (0x40) /* Data Buffer */ 48 #define NDCB0 (0x48) /* Command Buffer0 */ 49 #define NDCB1 (0x4C) /* Command Buffer1 */ 50 #define NDCB2 (0x50) /* Command Buffer2 */ 51 52 #define NDCR_SPARE_EN (0x1 << 31) 53 #define NDCR_ECC_EN (0x1 << 30) 54 #define NDCR_DMA_EN (0x1 << 29) 55 #define NDCR_ND_RUN (0x1 << 28) 56 #define NDCR_DWIDTH_C (0x1 << 27) 57 #define NDCR_DWIDTH_M (0x1 << 26) 58 #define NDCR_PAGE_SZ (0x1 << 24) 59 #define NDCR_NCSX (0x1 << 23) 60 #define NDCR_ND_MODE (0x3 << 21) 61 #define NDCR_NAND_MODE (0x0) 62 #define NDCR_CLR_PG_CNT (0x1 << 20) 63 #define NFCV1_NDCR_ARB_CNTL (0x1 << 19) 64 #define NDCR_RD_ID_CNT_MASK (0x7 << 16) 65 #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) 66 67 #define NDCR_RA_START (0x1 << 15) 68 #define NDCR_PG_PER_BLK (0x1 << 14) 69 #define NDCR_ND_ARB_EN (0x1 << 12) 70 #define NDCR_INT_MASK (0xFFF) 71 72 #define NDSR_MASK (0xfff) 73 #define NDSR_ERR_CNT_OFF (16) 74 #define NDSR_ERR_CNT_MASK (0x1f) 75 #define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK) 76 #define NDSR_RDY (0x1 << 12) 77 #define NDSR_FLASH_RDY (0x1 << 11) 78 #define NDSR_CS0_PAGED (0x1 << 10) 79 #define NDSR_CS1_PAGED (0x1 << 9) 80 #define NDSR_CS0_CMDD (0x1 << 8) 81 #define NDSR_CS1_CMDD (0x1 << 7) 82 #define NDSR_CS0_BBD (0x1 << 6) 83 #define NDSR_CS1_BBD (0x1 << 5) 84 #define NDSR_UNCORERR (0x1 << 4) 85 #define NDSR_CORERR (0x1 << 3) 86 #define NDSR_WRDREQ (0x1 << 2) 87 #define NDSR_RDDREQ (0x1 << 1) 88 #define NDSR_WRCMDREQ (0x1) 89 90 #define NDCB0_LEN_OVRD (0x1 << 28) 91 #define NDCB0_ST_ROW_EN (0x1 << 26) 92 #define NDCB0_AUTO_RS (0x1 << 25) 93 #define NDCB0_CSEL (0x1 << 24) 94 #define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29) 95 #define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK) 96 #define NDCB0_CMD_TYPE_MASK (0x7 << 21) 97 #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) 98 #define NDCB0_NC (0x1 << 20) 99 #define NDCB0_DBC (0x1 << 19) 100 #define NDCB0_ADDR_CYC_MASK (0x7 << 16) 101 #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) 102 #define NDCB0_CMD2_MASK (0xff << 8) 103 #define NDCB0_CMD1_MASK (0xff) 104 #define NDCB0_ADDR_CYC_SHIFT (16) 105 106 #define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */ 107 #define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */ 108 #define EXT_CMD_TYPE_READ 4 /* Read */ 109 #define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */ 110 #define EXT_CMD_TYPE_FINAL 3 /* Final command */ 111 #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */ 112 #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */ 113 114 /* 115 * This should be large enough to read 'ONFI' and 'JEDEC'. 116 * Let's use 7 bytes, which is the maximum ID count supported 117 * by the controller (see NDCR_RD_ID_CNT_MASK). 118 */ 119 #define READ_ID_BYTES 7 120 121 /* macros for registers read/write */ 122 #define nand_writel(info, off, val) \ 123 writel((val), (info)->mmio_base + (off)) 124 125 #define nand_readl(info, off) \ 126 readl((info)->mmio_base + (off)) 127 128 /* error code and state */ 129 enum { 130 ERR_NONE = 0, 131 ERR_DMABUSERR = -1, 132 ERR_SENDCMD = -2, 133 ERR_UNCORERR = -3, 134 ERR_BBERR = -4, 135 ERR_CORERR = -5, 136 }; 137 138 enum { 139 STATE_IDLE = 0, 140 STATE_PREPARED, 141 STATE_CMD_HANDLE, 142 STATE_DMA_READING, 143 STATE_DMA_WRITING, 144 STATE_DMA_DONE, 145 STATE_PIO_READING, 146 STATE_PIO_WRITING, 147 STATE_CMD_DONE, 148 STATE_READY, 149 }; 150 151 enum pxa3xx_nand_variant { 152 PXA3XX_NAND_VARIANT_PXA, 153 PXA3XX_NAND_VARIANT_ARMADA370, 154 }; 155 156 struct pxa3xx_nand_host { 157 struct nand_chip chip; 158 void *info_data; 159 160 /* page size of attached chip */ 161 int use_ecc; 162 int cs; 163 164 /* calculated from pxa3xx_nand_flash data */ 165 unsigned int col_addr_cycles; 166 unsigned int row_addr_cycles; 167 }; 168 169 struct pxa3xx_nand_info { 170 struct nand_hw_control controller; 171 struct pxa3xx_nand_platform_data *pdata; 172 173 struct clk *clk; 174 void __iomem *mmio_base; 175 unsigned long mmio_phys; 176 int cmd_complete, dev_ready; 177 178 unsigned int buf_start; 179 unsigned int buf_count; 180 unsigned int buf_size; 181 unsigned int data_buff_pos; 182 unsigned int oob_buff_pos; 183 184 unsigned char *data_buff; 185 unsigned char *oob_buff; 186 187 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT]; 188 unsigned int state; 189 190 /* 191 * This driver supports NFCv1 (as found in PXA SoC) 192 * and NFCv2 (as found in Armada 370/XP SoC). 193 */ 194 enum pxa3xx_nand_variant variant; 195 196 int cs; 197 int use_ecc; /* use HW ECC ? */ 198 int ecc_bch; /* using BCH ECC? */ 199 int use_spare; /* use spare ? */ 200 int need_wait; 201 202 /* Amount of real data per full chunk */ 203 unsigned int chunk_size; 204 205 /* Amount of spare data per full chunk */ 206 unsigned int spare_size; 207 208 /* Number of full chunks (i.e chunk_size + spare_size) */ 209 unsigned int nfullchunks; 210 211 /* 212 * Total number of chunks. If equal to nfullchunks, then there 213 * are only full chunks. Otherwise, there is one last chunk of 214 * size (last_chunk_size + last_spare_size) 215 */ 216 unsigned int ntotalchunks; 217 218 /* Amount of real data in the last chunk */ 219 unsigned int last_chunk_size; 220 221 /* Amount of spare data in the last chunk */ 222 unsigned int last_spare_size; 223 224 unsigned int ecc_size; 225 unsigned int ecc_err_cnt; 226 unsigned int max_bitflips; 227 int retcode; 228 229 /* 230 * Variables only valid during command 231 * execution. step_chunk_size and step_spare_size is the 232 * amount of real data and spare data in the current 233 * chunk. cur_chunk is the current chunk being 234 * read/programmed. 235 */ 236 unsigned int step_chunk_size; 237 unsigned int step_spare_size; 238 unsigned int cur_chunk; 239 240 /* cached register value */ 241 uint32_t reg_ndcr; 242 uint32_t ndtr0cs0; 243 uint32_t ndtr1cs0; 244 245 /* generated NDCBx register values */ 246 uint32_t ndcb0; 247 uint32_t ndcb1; 248 uint32_t ndcb2; 249 uint32_t ndcb3; 250 }; 251 252 static struct pxa3xx_nand_timing timing[] = { 253 /* 254 * tCH Enable signal hold time 255 * tCS Enable signal setup time 256 * tWH ND_nWE high duration 257 * tWP ND_nWE pulse time 258 * tRH ND_nRE high duration 259 * tRP ND_nRE pulse width 260 * tR ND_nWE high to ND_nRE low for read 261 * tWHR ND_nWE high to ND_nRE low for status read 262 * tAR ND_ALE low to ND_nRE low delay 263 */ 264 /*ch cs wh wp rh rp r whr ar */ 265 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, 266 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, 267 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, 268 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, 269 { 5, 20, 10, 12, 10, 12, 25000, 60, 10, }, 270 }; 271 272 static struct pxa3xx_nand_flash builtin_flash_types[] = { 273 /* 274 * chip_id 275 * flash_width Width of Flash memory (DWIDTH_M) 276 * dfc_width Width of flash controller(DWIDTH_C) 277 * *timing 278 * http://www.linux-mtd.infradead.org/nand-data/nanddata.html 279 */ 280 { 0x46ec, 16, 16, &timing[1] }, 281 { 0xdaec, 8, 8, &timing[1] }, 282 { 0xd7ec, 8, 8, &timing[1] }, 283 { 0xa12c, 8, 8, &timing[2] }, 284 { 0xb12c, 16, 16, &timing[2] }, 285 { 0xdc2c, 8, 8, &timing[2] }, 286 { 0xcc2c, 16, 16, &timing[2] }, 287 { 0xba20, 16, 16, &timing[3] }, 288 { 0xda98, 8, 8, &timing[4] }, 289 }; 290 291 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT 292 static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' }; 293 static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' }; 294 295 static struct nand_bbt_descr bbt_main_descr = { 296 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 297 | NAND_BBT_2BIT | NAND_BBT_VERSION, 298 .offs = 8, 299 .len = 6, 300 .veroffs = 14, 301 .maxblocks = 8, /* Last 8 blocks in each chip */ 302 .pattern = bbt_pattern 303 }; 304 305 static struct nand_bbt_descr bbt_mirror_descr = { 306 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 307 | NAND_BBT_2BIT | NAND_BBT_VERSION, 308 .offs = 8, 309 .len = 6, 310 .veroffs = 14, 311 .maxblocks = 8, /* Last 8 blocks in each chip */ 312 .pattern = bbt_mirror_pattern 313 }; 314 #endif 315 316 static struct nand_ecclayout ecc_layout_2KB_bch4bit = { 317 .eccbytes = 32, 318 .eccpos = { 319 32, 33, 34, 35, 36, 37, 38, 39, 320 40, 41, 42, 43, 44, 45, 46, 47, 321 48, 49, 50, 51, 52, 53, 54, 55, 322 56, 57, 58, 59, 60, 61, 62, 63}, 323 .oobfree = { {2, 30} } 324 }; 325 326 static struct nand_ecclayout ecc_layout_2KB_bch8bit = { 327 .eccbytes = 64, 328 .eccpos = { 329 64, 65, 66, 67, 68, 69, 70, 71, 330 72, 73, 74, 75, 76, 77, 78, 79, 331 80, 81, 82, 83, 84, 85, 86, 87, 332 88, 89, 90, 91, 92, 93, 94, 95, 333 96, 97, 98, 99, 100, 101, 102, 103, 334 104, 105, 106, 107, 108, 109, 110, 111, 335 112, 113, 114, 115, 116, 117, 118, 119, 336 120, 121, 122, 123, 124, 125, 126, 127}, 337 .oobfree = { {1, 4}, {6, 26} } 338 }; 339 340 static struct nand_ecclayout ecc_layout_4KB_bch4bit = { 341 .eccbytes = 64, 342 .eccpos = { 343 32, 33, 34, 35, 36, 37, 38, 39, 344 40, 41, 42, 43, 44, 45, 46, 47, 345 48, 49, 50, 51, 52, 53, 54, 55, 346 56, 57, 58, 59, 60, 61, 62, 63, 347 96, 97, 98, 99, 100, 101, 102, 103, 348 104, 105, 106, 107, 108, 109, 110, 111, 349 112, 113, 114, 115, 116, 117, 118, 119, 350 120, 121, 122, 123, 124, 125, 126, 127}, 351 /* Bootrom looks in bytes 0 & 5 for bad blocks */ 352 .oobfree = { {6, 26}, { 64, 32} } 353 }; 354 355 static struct nand_ecclayout ecc_layout_8KB_bch4bit = { 356 .eccbytes = 128, 357 .eccpos = { 358 32, 33, 34, 35, 36, 37, 38, 39, 359 40, 41, 42, 43, 44, 45, 46, 47, 360 48, 49, 50, 51, 52, 53, 54, 55, 361 56, 57, 58, 59, 60, 61, 62, 63, 362 363 96, 97, 98, 99, 100, 101, 102, 103, 364 104, 105, 106, 107, 108, 109, 110, 111, 365 112, 113, 114, 115, 116, 117, 118, 119, 366 120, 121, 122, 123, 124, 125, 126, 127, 367 368 160, 161, 162, 163, 164, 165, 166, 167, 369 168, 169, 170, 171, 172, 173, 174, 175, 370 176, 177, 178, 179, 180, 181, 182, 183, 371 184, 185, 186, 187, 188, 189, 190, 191, 372 373 224, 225, 226, 227, 228, 229, 230, 231, 374 232, 233, 234, 235, 236, 237, 238, 239, 375 240, 241, 242, 243, 244, 245, 246, 247, 376 248, 249, 250, 251, 252, 253, 254, 255}, 377 378 /* Bootrom looks in bytes 0 & 5 for bad blocks */ 379 .oobfree = { {1, 4}, {6, 26}, { 64, 32}, {128, 32}, {192, 32} } 380 }; 381 382 static struct nand_ecclayout ecc_layout_4KB_bch8bit = { 383 .eccbytes = 128, 384 .eccpos = { 385 32, 33, 34, 35, 36, 37, 38, 39, 386 40, 41, 42, 43, 44, 45, 46, 47, 387 48, 49, 50, 51, 52, 53, 54, 55, 388 56, 57, 58, 59, 60, 61, 62, 63}, 389 .oobfree = { } 390 }; 391 392 static struct nand_ecclayout ecc_layout_8KB_bch8bit = { 393 .eccbytes = 256, 394 .eccpos = {}, 395 /* HW ECC handles all ECC data and all spare area is free for OOB */ 396 .oobfree = {{0, 160} } 397 }; 398 399 #define NDTR0_tCH(c) (min((c), 7) << 19) 400 #define NDTR0_tCS(c) (min((c), 7) << 16) 401 #define NDTR0_tWH(c) (min((c), 7) << 11) 402 #define NDTR0_tWP(c) (min((c), 7) << 8) 403 #define NDTR0_tRH(c) (min((c), 7) << 3) 404 #define NDTR0_tRP(c) (min((c), 7) << 0) 405 406 #define NDTR1_tR(c) (min((c), 65535) << 16) 407 #define NDTR1_tWHR(c) (min((c), 15) << 4) 408 #define NDTR1_tAR(c) (min((c), 15) << 0) 409 410 /* convert nano-seconds to nand flash controller clock cycles */ 411 #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) 412 413 static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void) 414 { 415 /* We only support the Armada 370/XP/38x for now */ 416 return PXA3XX_NAND_VARIANT_ARMADA370; 417 } 418 419 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, 420 const struct pxa3xx_nand_timing *t) 421 { 422 struct pxa3xx_nand_info *info = host->info_data; 423 unsigned long nand_clk = mvebu_get_nand_clock(); 424 uint32_t ndtr0, ndtr1; 425 426 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | 427 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | 428 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | 429 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | 430 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | 431 NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); 432 433 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | 434 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | 435 NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); 436 437 info->ndtr0cs0 = ndtr0; 438 info->ndtr1cs0 = ndtr1; 439 nand_writel(info, NDTR0CS0, ndtr0); 440 nand_writel(info, NDTR1CS0, ndtr1); 441 } 442 443 static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host, 444 const struct nand_sdr_timings *t) 445 { 446 struct pxa3xx_nand_info *info = host->info_data; 447 struct nand_chip *chip = &host->chip; 448 unsigned long nand_clk = mvebu_get_nand_clock(); 449 uint32_t ndtr0, ndtr1; 450 451 u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000); 452 u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000); 453 u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000); 454 u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000); 455 u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000); 456 u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000); 457 u32 tR = chip->chip_delay * 1000; 458 u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000); 459 u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000); 460 461 /* fallback to a default value if tR = 0 */ 462 if (!tR) 463 tR = 20000; 464 465 ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) | 466 NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) | 467 NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) | 468 NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) | 469 NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) | 470 NDTR0_tRP(ns2cycle(tRP_min, nand_clk)); 471 472 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | 473 NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) | 474 NDTR1_tAR(ns2cycle(tAR_min, nand_clk)); 475 476 info->ndtr0cs0 = ndtr0; 477 info->ndtr1cs0 = ndtr1; 478 nand_writel(info, NDTR0CS0, ndtr0); 479 nand_writel(info, NDTR1CS0, ndtr1); 480 } 481 482 static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host) 483 { 484 const struct nand_sdr_timings *timings; 485 struct nand_chip *chip = &host->chip; 486 struct pxa3xx_nand_info *info = host->info_data; 487 const struct pxa3xx_nand_flash *f = NULL; 488 struct mtd_info *mtd = nand_to_mtd(&host->chip); 489 int mode, id, ntypes, i; 490 491 mode = onfi_get_async_timing_mode(chip); 492 if (mode == ONFI_TIMING_MODE_UNKNOWN) { 493 ntypes = ARRAY_SIZE(builtin_flash_types); 494 495 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 496 497 id = chip->read_byte(mtd); 498 id |= chip->read_byte(mtd) << 0x8; 499 500 for (i = 0; i < ntypes; i++) { 501 f = &builtin_flash_types[i]; 502 503 if (f->chip_id == id) 504 break; 505 } 506 507 if (i == ntypes) { 508 dev_err(&info->pdev->dev, "Error: timings not found\n"); 509 return -EINVAL; 510 } 511 512 pxa3xx_nand_set_timing(host, f->timing); 513 514 if (f->flash_width == 16) { 515 info->reg_ndcr |= NDCR_DWIDTH_M; 516 chip->options |= NAND_BUSWIDTH_16; 517 } 518 519 info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; 520 } else { 521 mode = fls(mode) - 1; 522 if (mode < 0) 523 mode = 0; 524 525 timings = onfi_async_timing_mode_to_sdr_timings(mode); 526 if (IS_ERR(timings)) 527 return PTR_ERR(timings); 528 529 pxa3xx_nand_set_sdr_timing(host, timings); 530 } 531 532 return 0; 533 } 534 535 /** 536 * NOTE: it is a must to set ND_RUN first, then write 537 * command buffer, otherwise, it does not work. 538 * We enable all the interrupt at the same time, and 539 * let pxa3xx_nand_irq to handle all logic. 540 */ 541 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) 542 { 543 uint32_t ndcr; 544 545 ndcr = info->reg_ndcr; 546 547 if (info->use_ecc) { 548 ndcr |= NDCR_ECC_EN; 549 if (info->ecc_bch) 550 nand_writel(info, NDECCCTRL, 0x1); 551 } else { 552 ndcr &= ~NDCR_ECC_EN; 553 if (info->ecc_bch) 554 nand_writel(info, NDECCCTRL, 0x0); 555 } 556 557 ndcr &= ~NDCR_DMA_EN; 558 559 if (info->use_spare) 560 ndcr |= NDCR_SPARE_EN; 561 else 562 ndcr &= ~NDCR_SPARE_EN; 563 564 ndcr |= NDCR_ND_RUN; 565 566 /* clear status bits and run */ 567 nand_writel(info, NDSR, NDSR_MASK); 568 nand_writel(info, NDCR, 0); 569 nand_writel(info, NDCR, ndcr); 570 } 571 572 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) 573 { 574 uint32_t ndcr; 575 576 ndcr = nand_readl(info, NDCR); 577 nand_writel(info, NDCR, ndcr | int_mask); 578 } 579 580 static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) 581 { 582 if (info->ecc_bch) { 583 u32 ts; 584 585 /* 586 * According to the datasheet, when reading from NDDB 587 * with BCH enabled, after each 32 bytes reads, we 588 * have to make sure that the NDSR.RDDREQ bit is set. 589 * 590 * Drain the FIFO 8 32 bits reads at a time, and skip 591 * the polling on the last read. 592 */ 593 while (len > 8) { 594 readsl(info->mmio_base + NDDB, data, 8); 595 596 ts = get_timer(0); 597 while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) { 598 if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) { 599 dev_err(&info->pdev->dev, 600 "Timeout on RDDREQ while draining the FIFO\n"); 601 return; 602 } 603 } 604 605 data += 32; 606 len -= 8; 607 } 608 } 609 610 readsl(info->mmio_base + NDDB, data, len); 611 } 612 613 static void handle_data_pio(struct pxa3xx_nand_info *info) 614 { 615 switch (info->state) { 616 case STATE_PIO_WRITING: 617 if (info->step_chunk_size) 618 writesl(info->mmio_base + NDDB, 619 info->data_buff + info->data_buff_pos, 620 DIV_ROUND_UP(info->step_chunk_size, 4)); 621 622 if (info->step_spare_size) 623 writesl(info->mmio_base + NDDB, 624 info->oob_buff + info->oob_buff_pos, 625 DIV_ROUND_UP(info->step_spare_size, 4)); 626 break; 627 case STATE_PIO_READING: 628 if (info->step_chunk_size) 629 drain_fifo(info, 630 info->data_buff + info->data_buff_pos, 631 DIV_ROUND_UP(info->step_chunk_size, 4)); 632 633 if (info->step_spare_size) 634 drain_fifo(info, 635 info->oob_buff + info->oob_buff_pos, 636 DIV_ROUND_UP(info->step_spare_size, 4)); 637 break; 638 default: 639 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, 640 info->state); 641 BUG(); 642 } 643 644 /* Update buffer pointers for multi-page read/write */ 645 info->data_buff_pos += info->step_chunk_size; 646 info->oob_buff_pos += info->step_spare_size; 647 } 648 649 static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info) 650 { 651 handle_data_pio(info); 652 653 info->state = STATE_CMD_DONE; 654 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); 655 } 656 657 static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info) 658 { 659 unsigned int status, is_completed = 0, is_ready = 0; 660 unsigned int ready, cmd_done; 661 irqreturn_t ret = IRQ_HANDLED; 662 663 if (info->cs == 0) { 664 ready = NDSR_FLASH_RDY; 665 cmd_done = NDSR_CS0_CMDD; 666 } else { 667 ready = NDSR_RDY; 668 cmd_done = NDSR_CS1_CMDD; 669 } 670 671 /* TODO - find out why we need the delay during write operation. */ 672 ndelay(1); 673 674 status = nand_readl(info, NDSR); 675 676 if (status & NDSR_UNCORERR) 677 info->retcode = ERR_UNCORERR; 678 if (status & NDSR_CORERR) { 679 info->retcode = ERR_CORERR; 680 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 && 681 info->ecc_bch) 682 info->ecc_err_cnt = NDSR_ERR_CNT(status); 683 else 684 info->ecc_err_cnt = 1; 685 686 /* 687 * Each chunk composing a page is corrected independently, 688 * and we need to store maximum number of corrected bitflips 689 * to return it to the MTD layer in ecc.read_page(). 690 */ 691 info->max_bitflips = max_t(unsigned int, 692 info->max_bitflips, 693 info->ecc_err_cnt); 694 } 695 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) { 696 info->state = (status & NDSR_RDDREQ) ? 697 STATE_PIO_READING : STATE_PIO_WRITING; 698 /* Call the IRQ thread in U-Boot directly */ 699 pxa3xx_nand_irq_thread(info); 700 return 0; 701 } 702 if (status & cmd_done) { 703 info->state = STATE_CMD_DONE; 704 is_completed = 1; 705 } 706 if (status & ready) { 707 info->state = STATE_READY; 708 is_ready = 1; 709 } 710 711 /* 712 * Clear all status bit before issuing the next command, which 713 * can and will alter the status bits and will deserve a new 714 * interrupt on its own. This lets the controller exit the IRQ 715 */ 716 nand_writel(info, NDSR, status); 717 718 if (status & NDSR_WRCMDREQ) { 719 status &= ~NDSR_WRCMDREQ; 720 info->state = STATE_CMD_HANDLE; 721 722 /* 723 * Command buffer registers NDCB{0-2} (and optionally NDCB3) 724 * must be loaded by writing directly either 12 or 16 725 * bytes directly to NDCB0, four bytes at a time. 726 * 727 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored 728 * but each NDCBx register can be read. 729 */ 730 nand_writel(info, NDCB0, info->ndcb0); 731 nand_writel(info, NDCB0, info->ndcb1); 732 nand_writel(info, NDCB0, info->ndcb2); 733 734 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */ 735 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) 736 nand_writel(info, NDCB0, info->ndcb3); 737 } 738 739 if (is_completed) 740 info->cmd_complete = 1; 741 if (is_ready) 742 info->dev_ready = 1; 743 744 return ret; 745 } 746 747 static inline int is_buf_blank(uint8_t *buf, size_t len) 748 { 749 for (; len > 0; len--) 750 if (*buf++ != 0xff) 751 return 0; 752 return 1; 753 } 754 755 static void set_command_address(struct pxa3xx_nand_info *info, 756 unsigned int page_size, uint16_t column, int page_addr) 757 { 758 /* small page addr setting */ 759 if (page_size < info->chunk_size) { 760 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) 761 | (column & 0xFF); 762 763 info->ndcb2 = 0; 764 } else { 765 info->ndcb1 = ((page_addr & 0xFFFF) << 16) 766 | (column & 0xFFFF); 767 768 if (page_addr & 0xFF0000) 769 info->ndcb2 = (page_addr & 0xFF0000) >> 16; 770 else 771 info->ndcb2 = 0; 772 } 773 } 774 775 static void prepare_start_command(struct pxa3xx_nand_info *info, int command) 776 { 777 struct pxa3xx_nand_host *host = info->host[info->cs]; 778 struct mtd_info *mtd = nand_to_mtd(&host->chip); 779 780 /* reset data and oob column point to handle data */ 781 info->buf_start = 0; 782 info->buf_count = 0; 783 info->data_buff_pos = 0; 784 info->oob_buff_pos = 0; 785 info->step_chunk_size = 0; 786 info->step_spare_size = 0; 787 info->cur_chunk = 0; 788 info->use_ecc = 0; 789 info->use_spare = 1; 790 info->retcode = ERR_NONE; 791 info->ecc_err_cnt = 0; 792 info->ndcb3 = 0; 793 info->need_wait = 0; 794 795 switch (command) { 796 case NAND_CMD_READ0: 797 case NAND_CMD_READOOB: 798 case NAND_CMD_PAGEPROG: 799 info->use_ecc = 1; 800 break; 801 case NAND_CMD_PARAM: 802 info->use_spare = 0; 803 break; 804 default: 805 info->ndcb1 = 0; 806 info->ndcb2 = 0; 807 break; 808 } 809 810 /* 811 * If we are about to issue a read command, or about to set 812 * the write address, then clean the data buffer. 813 */ 814 if (command == NAND_CMD_READ0 || 815 command == NAND_CMD_READOOB || 816 command == NAND_CMD_SEQIN) { 817 info->buf_count = mtd->writesize + mtd->oobsize; 818 memset(info->data_buff, 0xFF, info->buf_count); 819 } 820 } 821 822 static int prepare_set_command(struct pxa3xx_nand_info *info, int command, 823 int ext_cmd_type, uint16_t column, int page_addr) 824 { 825 int addr_cycle, exec_cmd; 826 struct pxa3xx_nand_host *host; 827 struct mtd_info *mtd; 828 829 host = info->host[info->cs]; 830 mtd = nand_to_mtd(&host->chip); 831 addr_cycle = 0; 832 exec_cmd = 1; 833 834 if (info->cs != 0) 835 info->ndcb0 = NDCB0_CSEL; 836 else 837 info->ndcb0 = 0; 838 839 if (command == NAND_CMD_SEQIN) 840 exec_cmd = 0; 841 842 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles 843 + host->col_addr_cycles); 844 845 switch (command) { 846 case NAND_CMD_READOOB: 847 case NAND_CMD_READ0: 848 info->buf_start = column; 849 info->ndcb0 |= NDCB0_CMD_TYPE(0) 850 | addr_cycle 851 | NAND_CMD_READ0; 852 853 if (command == NAND_CMD_READOOB) 854 info->buf_start += mtd->writesize; 855 856 if (info->cur_chunk < info->nfullchunks) { 857 info->step_chunk_size = info->chunk_size; 858 info->step_spare_size = info->spare_size; 859 } else { 860 info->step_chunk_size = info->last_chunk_size; 861 info->step_spare_size = info->last_spare_size; 862 } 863 864 /* 865 * Multiple page read needs an 'extended command type' field, 866 * which is either naked-read or last-read according to the 867 * state. 868 */ 869 if (mtd->writesize == info->chunk_size) { 870 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); 871 } else if (mtd->writesize > info->chunk_size) { 872 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) 873 | NDCB0_LEN_OVRD 874 | NDCB0_EXT_CMD_TYPE(ext_cmd_type); 875 info->ndcb3 = info->step_chunk_size + 876 info->step_spare_size; 877 } 878 879 set_command_address(info, mtd->writesize, column, page_addr); 880 break; 881 882 case NAND_CMD_SEQIN: 883 884 info->buf_start = column; 885 set_command_address(info, mtd->writesize, 0, page_addr); 886 887 /* 888 * Multiple page programming needs to execute the initial 889 * SEQIN command that sets the page address. 890 */ 891 if (mtd->writesize > info->chunk_size) { 892 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) 893 | NDCB0_EXT_CMD_TYPE(ext_cmd_type) 894 | addr_cycle 895 | command; 896 exec_cmd = 1; 897 } 898 break; 899 900 case NAND_CMD_PAGEPROG: 901 if (is_buf_blank(info->data_buff, 902 (mtd->writesize + mtd->oobsize))) { 903 exec_cmd = 0; 904 break; 905 } 906 907 if (info->cur_chunk < info->nfullchunks) { 908 info->step_chunk_size = info->chunk_size; 909 info->step_spare_size = info->spare_size; 910 } else { 911 info->step_chunk_size = info->last_chunk_size; 912 info->step_spare_size = info->last_spare_size; 913 } 914 915 /* Second command setting for large pages */ 916 if (mtd->writesize > info->chunk_size) { 917 /* 918 * Multiple page write uses the 'extended command' 919 * field. This can be used to issue a command dispatch 920 * or a naked-write depending on the current stage. 921 */ 922 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) 923 | NDCB0_LEN_OVRD 924 | NDCB0_EXT_CMD_TYPE(ext_cmd_type); 925 info->ndcb3 = info->step_chunk_size + 926 info->step_spare_size; 927 928 /* 929 * This is the command dispatch that completes a chunked 930 * page program operation. 931 */ 932 if (info->cur_chunk == info->ntotalchunks) { 933 info->ndcb0 = NDCB0_CMD_TYPE(0x1) 934 | NDCB0_EXT_CMD_TYPE(ext_cmd_type) 935 | command; 936 info->ndcb1 = 0; 937 info->ndcb2 = 0; 938 info->ndcb3 = 0; 939 } 940 } else { 941 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) 942 | NDCB0_AUTO_RS 943 | NDCB0_ST_ROW_EN 944 | NDCB0_DBC 945 | (NAND_CMD_PAGEPROG << 8) 946 | NAND_CMD_SEQIN 947 | addr_cycle; 948 } 949 break; 950 951 case NAND_CMD_PARAM: 952 info->buf_count = INIT_BUFFER_SIZE; 953 info->ndcb0 |= NDCB0_CMD_TYPE(0) 954 | NDCB0_ADDR_CYC(1) 955 | NDCB0_LEN_OVRD 956 | command; 957 info->ndcb1 = (column & 0xFF); 958 info->ndcb3 = INIT_BUFFER_SIZE; 959 info->step_chunk_size = INIT_BUFFER_SIZE; 960 break; 961 962 case NAND_CMD_READID: 963 info->buf_count = READ_ID_BYTES; 964 info->ndcb0 |= NDCB0_CMD_TYPE(3) 965 | NDCB0_ADDR_CYC(1) 966 | command; 967 info->ndcb1 = (column & 0xFF); 968 969 info->step_chunk_size = 8; 970 break; 971 case NAND_CMD_STATUS: 972 info->buf_count = 1; 973 info->ndcb0 |= NDCB0_CMD_TYPE(4) 974 | NDCB0_ADDR_CYC(1) 975 | command; 976 977 info->step_chunk_size = 8; 978 break; 979 980 case NAND_CMD_ERASE1: 981 info->ndcb0 |= NDCB0_CMD_TYPE(2) 982 | NDCB0_AUTO_RS 983 | NDCB0_ADDR_CYC(3) 984 | NDCB0_DBC 985 | (NAND_CMD_ERASE2 << 8) 986 | NAND_CMD_ERASE1; 987 info->ndcb1 = page_addr; 988 info->ndcb2 = 0; 989 990 break; 991 case NAND_CMD_RESET: 992 info->ndcb0 |= NDCB0_CMD_TYPE(5) 993 | command; 994 995 break; 996 997 case NAND_CMD_ERASE2: 998 exec_cmd = 0; 999 break; 1000 1001 default: 1002 exec_cmd = 0; 1003 dev_err(&info->pdev->dev, "non-supported command %x\n", 1004 command); 1005 break; 1006 } 1007 1008 return exec_cmd; 1009 } 1010 1011 static void nand_cmdfunc(struct mtd_info *mtd, unsigned command, 1012 int column, int page_addr) 1013 { 1014 struct nand_chip *chip = mtd_to_nand(mtd); 1015 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1016 struct pxa3xx_nand_info *info = host->info_data; 1017 int exec_cmd; 1018 1019 /* 1020 * if this is a x16 device ,then convert the input 1021 * "byte" address into a "word" address appropriate 1022 * for indexing a word-oriented device 1023 */ 1024 if (info->reg_ndcr & NDCR_DWIDTH_M) 1025 column /= 2; 1026 1027 /* 1028 * There may be different NAND chip hooked to 1029 * different chip select, so check whether 1030 * chip select has been changed, if yes, reset the timing 1031 */ 1032 if (info->cs != host->cs) { 1033 info->cs = host->cs; 1034 nand_writel(info, NDTR0CS0, info->ndtr0cs0); 1035 nand_writel(info, NDTR1CS0, info->ndtr1cs0); 1036 } 1037 1038 prepare_start_command(info, command); 1039 1040 info->state = STATE_PREPARED; 1041 exec_cmd = prepare_set_command(info, command, 0, column, page_addr); 1042 1043 if (exec_cmd) { 1044 u32 ts; 1045 1046 info->cmd_complete = 0; 1047 info->dev_ready = 0; 1048 info->need_wait = 1; 1049 pxa3xx_nand_start(info); 1050 1051 ts = get_timer(0); 1052 while (1) { 1053 u32 status; 1054 1055 status = nand_readl(info, NDSR); 1056 if (status) 1057 pxa3xx_nand_irq(info); 1058 1059 if (info->cmd_complete) 1060 break; 1061 1062 if (get_timer(ts) > CHIP_DELAY_TIMEOUT) { 1063 dev_err(&info->pdev->dev, "Wait timeout!!!\n"); 1064 return; 1065 } 1066 } 1067 } 1068 info->state = STATE_IDLE; 1069 } 1070 1071 static void nand_cmdfunc_extended(struct mtd_info *mtd, 1072 const unsigned command, 1073 int column, int page_addr) 1074 { 1075 struct nand_chip *chip = mtd_to_nand(mtd); 1076 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1077 struct pxa3xx_nand_info *info = host->info_data; 1078 int exec_cmd, ext_cmd_type; 1079 1080 /* 1081 * if this is a x16 device then convert the input 1082 * "byte" address into a "word" address appropriate 1083 * for indexing a word-oriented device 1084 */ 1085 if (info->reg_ndcr & NDCR_DWIDTH_M) 1086 column /= 2; 1087 1088 /* 1089 * There may be different NAND chip hooked to 1090 * different chip select, so check whether 1091 * chip select has been changed, if yes, reset the timing 1092 */ 1093 if (info->cs != host->cs) { 1094 info->cs = host->cs; 1095 nand_writel(info, NDTR0CS0, info->ndtr0cs0); 1096 nand_writel(info, NDTR1CS0, info->ndtr1cs0); 1097 } 1098 1099 /* Select the extended command for the first command */ 1100 switch (command) { 1101 case NAND_CMD_READ0: 1102 case NAND_CMD_READOOB: 1103 ext_cmd_type = EXT_CMD_TYPE_MONO; 1104 break; 1105 case NAND_CMD_SEQIN: 1106 ext_cmd_type = EXT_CMD_TYPE_DISPATCH; 1107 break; 1108 case NAND_CMD_PAGEPROG: 1109 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW; 1110 break; 1111 default: 1112 ext_cmd_type = 0; 1113 break; 1114 } 1115 1116 prepare_start_command(info, command); 1117 1118 /* 1119 * Prepare the "is ready" completion before starting a command 1120 * transaction sequence. If the command is not executed the 1121 * completion will be completed, see below. 1122 * 1123 * We can do that inside the loop because the command variable 1124 * is invariant and thus so is the exec_cmd. 1125 */ 1126 info->need_wait = 1; 1127 info->dev_ready = 0; 1128 1129 do { 1130 u32 ts; 1131 1132 info->state = STATE_PREPARED; 1133 exec_cmd = prepare_set_command(info, command, ext_cmd_type, 1134 column, page_addr); 1135 if (!exec_cmd) { 1136 info->need_wait = 0; 1137 info->dev_ready = 1; 1138 break; 1139 } 1140 1141 info->cmd_complete = 0; 1142 pxa3xx_nand_start(info); 1143 1144 ts = get_timer(0); 1145 while (1) { 1146 u32 status; 1147 1148 status = nand_readl(info, NDSR); 1149 if (status) 1150 pxa3xx_nand_irq(info); 1151 1152 if (info->cmd_complete) 1153 break; 1154 1155 if (get_timer(ts) > CHIP_DELAY_TIMEOUT) { 1156 dev_err(&info->pdev->dev, "Wait timeout!!!\n"); 1157 return; 1158 } 1159 } 1160 1161 /* Only a few commands need several steps */ 1162 if (command != NAND_CMD_PAGEPROG && 1163 command != NAND_CMD_READ0 && 1164 command != NAND_CMD_READOOB) 1165 break; 1166 1167 info->cur_chunk++; 1168 1169 /* Check if the sequence is complete */ 1170 if (info->cur_chunk == info->ntotalchunks && 1171 command != NAND_CMD_PAGEPROG) 1172 break; 1173 1174 /* 1175 * After a splitted program command sequence has issued 1176 * the command dispatch, the command sequence is complete. 1177 */ 1178 if (info->cur_chunk == (info->ntotalchunks + 1) && 1179 command == NAND_CMD_PAGEPROG && 1180 ext_cmd_type == EXT_CMD_TYPE_DISPATCH) 1181 break; 1182 1183 if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) { 1184 /* Last read: issue a 'last naked read' */ 1185 if (info->cur_chunk == info->ntotalchunks - 1) 1186 ext_cmd_type = EXT_CMD_TYPE_LAST_RW; 1187 else 1188 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW; 1189 1190 /* 1191 * If a splitted program command has no more data to transfer, 1192 * the command dispatch must be issued to complete. 1193 */ 1194 } else if (command == NAND_CMD_PAGEPROG && 1195 info->cur_chunk == info->ntotalchunks) { 1196 ext_cmd_type = EXT_CMD_TYPE_DISPATCH; 1197 } 1198 } while (1); 1199 1200 info->state = STATE_IDLE; 1201 } 1202 1203 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, 1204 struct nand_chip *chip, const uint8_t *buf, int oob_required, 1205 int page) 1206 { 1207 chip->write_buf(mtd, buf, mtd->writesize); 1208 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 1209 1210 return 0; 1211 } 1212 1213 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, 1214 struct nand_chip *chip, uint8_t *buf, int oob_required, 1215 int page) 1216 { 1217 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1218 struct pxa3xx_nand_info *info = host->info_data; 1219 1220 chip->read_buf(mtd, buf, mtd->writesize); 1221 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1222 1223 if (info->retcode == ERR_CORERR && info->use_ecc) { 1224 mtd->ecc_stats.corrected += info->ecc_err_cnt; 1225 1226 } else if (info->retcode == ERR_UNCORERR) { 1227 /* 1228 * for blank page (all 0xff), HW will calculate its ECC as 1229 * 0, which is different from the ECC information within 1230 * OOB, ignore such uncorrectable errors 1231 */ 1232 if (is_buf_blank(buf, mtd->writesize)) 1233 info->retcode = ERR_NONE; 1234 else 1235 mtd->ecc_stats.failed++; 1236 } 1237 1238 return info->max_bitflips; 1239 } 1240 1241 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) 1242 { 1243 struct nand_chip *chip = mtd_to_nand(mtd); 1244 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1245 struct pxa3xx_nand_info *info = host->info_data; 1246 char retval = 0xFF; 1247 1248 if (info->buf_start < info->buf_count) 1249 /* Has just send a new command? */ 1250 retval = info->data_buff[info->buf_start++]; 1251 1252 return retval; 1253 } 1254 1255 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) 1256 { 1257 struct nand_chip *chip = mtd_to_nand(mtd); 1258 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1259 struct pxa3xx_nand_info *info = host->info_data; 1260 u16 retval = 0xFFFF; 1261 1262 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { 1263 retval = *((u16 *)(info->data_buff+info->buf_start)); 1264 info->buf_start += 2; 1265 } 1266 return retval; 1267 } 1268 1269 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 1270 { 1271 struct nand_chip *chip = mtd_to_nand(mtd); 1272 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1273 struct pxa3xx_nand_info *info = host->info_data; 1274 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); 1275 1276 memcpy(buf, info->data_buff + info->buf_start, real_len); 1277 info->buf_start += real_len; 1278 } 1279 1280 static void pxa3xx_nand_write_buf(struct mtd_info *mtd, 1281 const uint8_t *buf, int len) 1282 { 1283 struct nand_chip *chip = mtd_to_nand(mtd); 1284 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1285 struct pxa3xx_nand_info *info = host->info_data; 1286 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); 1287 1288 memcpy(info->data_buff + info->buf_start, buf, real_len); 1289 info->buf_start += real_len; 1290 } 1291 1292 static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) 1293 { 1294 return; 1295 } 1296 1297 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) 1298 { 1299 struct nand_chip *chip = mtd_to_nand(mtd); 1300 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1301 struct pxa3xx_nand_info *info = host->info_data; 1302 1303 if (info->need_wait) { 1304 u32 ts; 1305 1306 info->need_wait = 0; 1307 1308 ts = get_timer(0); 1309 while (1) { 1310 u32 status; 1311 1312 status = nand_readl(info, NDSR); 1313 if (status) 1314 pxa3xx_nand_irq(info); 1315 1316 if (info->dev_ready) 1317 break; 1318 1319 if (get_timer(ts) > CHIP_DELAY_TIMEOUT) { 1320 dev_err(&info->pdev->dev, "Ready timeout!!!\n"); 1321 return NAND_STATUS_FAIL; 1322 } 1323 } 1324 } 1325 1326 /* pxa3xx_nand_send_command has waited for command complete */ 1327 if (this->state == FL_WRITING || this->state == FL_ERASING) { 1328 if (info->retcode == ERR_NONE) 1329 return 0; 1330 else 1331 return NAND_STATUS_FAIL; 1332 } 1333 1334 return NAND_STATUS_READY; 1335 } 1336 1337 static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info) 1338 { 1339 struct pxa3xx_nand_platform_data *pdata = info->pdata; 1340 1341 /* Configure default flash values */ 1342 info->reg_ndcr = 0x0; /* enable all interrupts */ 1343 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; 1344 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); 1345 info->reg_ndcr |= NDCR_SPARE_EN; 1346 1347 return 0; 1348 } 1349 1350 static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info) 1351 { 1352 struct pxa3xx_nand_host *host = info->host[info->cs]; 1353 struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip); 1354 struct nand_chip *chip = mtd_to_nand(mtd); 1355 1356 info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; 1357 info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0; 1358 info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0; 1359 } 1360 1361 static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) 1362 { 1363 struct pxa3xx_nand_platform_data *pdata = info->pdata; 1364 uint32_t ndcr = nand_readl(info, NDCR); 1365 1366 /* Set an initial chunk size */ 1367 info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512; 1368 info->reg_ndcr = ndcr & 1369 ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL); 1370 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; 1371 info->ndtr0cs0 = nand_readl(info, NDTR0CS0); 1372 info->ndtr1cs0 = nand_readl(info, NDTR1CS0); 1373 } 1374 1375 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) 1376 { 1377 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); 1378 if (info->data_buff == NULL) 1379 return -ENOMEM; 1380 return 0; 1381 } 1382 1383 static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host) 1384 { 1385 struct pxa3xx_nand_info *info = host->info_data; 1386 struct pxa3xx_nand_platform_data *pdata = info->pdata; 1387 struct mtd_info *mtd; 1388 struct nand_chip *chip; 1389 const struct nand_sdr_timings *timings; 1390 int ret; 1391 1392 mtd = nand_to_mtd(&info->host[info->cs]->chip); 1393 chip = mtd_to_nand(mtd); 1394 1395 /* configure default flash values */ 1396 info->reg_ndcr = 0x0; /* enable all interrupts */ 1397 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; 1398 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); 1399 info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */ 1400 1401 /* use the common timing to make a try */ 1402 timings = onfi_async_timing_mode_to_sdr_timings(0); 1403 if (IS_ERR(timings)) 1404 return PTR_ERR(timings); 1405 1406 pxa3xx_nand_set_sdr_timing(host, timings); 1407 1408 chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0); 1409 ret = chip->waitfunc(mtd, chip); 1410 if (ret & NAND_STATUS_FAIL) 1411 return -ENODEV; 1412 1413 return 0; 1414 } 1415 1416 static int pxa_ecc_init(struct pxa3xx_nand_info *info, 1417 struct nand_ecc_ctrl *ecc, 1418 int strength, int ecc_stepsize, int page_size) 1419 { 1420 if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) { 1421 info->nfullchunks = 1; 1422 info->ntotalchunks = 1; 1423 info->chunk_size = 2048; 1424 info->spare_size = 40; 1425 info->ecc_size = 24; 1426 ecc->mode = NAND_ECC_HW; 1427 ecc->size = 512; 1428 ecc->strength = 1; 1429 1430 } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) { 1431 info->nfullchunks = 1; 1432 info->ntotalchunks = 1; 1433 info->chunk_size = 512; 1434 info->spare_size = 8; 1435 info->ecc_size = 8; 1436 ecc->mode = NAND_ECC_HW; 1437 ecc->size = 512; 1438 ecc->strength = 1; 1439 1440 /* 1441 * Required ECC: 4-bit correction per 512 bytes 1442 * Select: 16-bit correction per 2048 bytes 1443 */ 1444 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) { 1445 info->ecc_bch = 1; 1446 info->nfullchunks = 1; 1447 info->ntotalchunks = 1; 1448 info->chunk_size = 2048; 1449 info->spare_size = 32; 1450 info->ecc_size = 32; 1451 ecc->mode = NAND_ECC_HW; 1452 ecc->size = info->chunk_size; 1453 ecc->layout = &ecc_layout_2KB_bch4bit; 1454 ecc->strength = 16; 1455 1456 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) { 1457 info->ecc_bch = 1; 1458 info->nfullchunks = 2; 1459 info->ntotalchunks = 2; 1460 info->chunk_size = 2048; 1461 info->spare_size = 32; 1462 info->ecc_size = 32; 1463 ecc->mode = NAND_ECC_HW; 1464 ecc->size = info->chunk_size; 1465 ecc->layout = &ecc_layout_4KB_bch4bit; 1466 ecc->strength = 16; 1467 1468 } else if (strength == 4 && ecc_stepsize == 512 && page_size == 8192) { 1469 info->ecc_bch = 1; 1470 info->nfullchunks = 4; 1471 info->ntotalchunks = 4; 1472 info->chunk_size = 2048; 1473 info->spare_size = 32; 1474 info->ecc_size = 32; 1475 ecc->mode = NAND_ECC_HW; 1476 ecc->size = info->chunk_size; 1477 ecc->layout = &ecc_layout_8KB_bch4bit; 1478 ecc->strength = 16; 1479 1480 /* 1481 * Required ECC: 8-bit correction per 512 bytes 1482 * Select: 16-bit correction per 1024 bytes 1483 */ 1484 } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) { 1485 info->ecc_bch = 1; 1486 info->nfullchunks = 1; 1487 info->ntotalchunks = 2; 1488 info->chunk_size = 1024; 1489 info->spare_size = 0; 1490 info->last_chunk_size = 1024; 1491 info->last_spare_size = 64; 1492 info->ecc_size = 32; 1493 ecc->mode = NAND_ECC_HW; 1494 ecc->size = info->chunk_size; 1495 ecc->layout = &ecc_layout_2KB_bch8bit; 1496 ecc->strength = 16; 1497 1498 } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) { 1499 info->ecc_bch = 1; 1500 info->nfullchunks = 4; 1501 info->ntotalchunks = 5; 1502 info->chunk_size = 1024; 1503 info->spare_size = 0; 1504 info->last_chunk_size = 0; 1505 info->last_spare_size = 64; 1506 info->ecc_size = 32; 1507 ecc->mode = NAND_ECC_HW; 1508 ecc->size = info->chunk_size; 1509 ecc->layout = &ecc_layout_4KB_bch8bit; 1510 ecc->strength = 16; 1511 1512 } else if (strength == 8 && ecc_stepsize == 512 && page_size == 8192) { 1513 info->ecc_bch = 1; 1514 info->nfullchunks = 8; 1515 info->ntotalchunks = 9; 1516 info->chunk_size = 1024; 1517 info->spare_size = 0; 1518 info->last_chunk_size = 0; 1519 info->last_spare_size = 160; 1520 info->ecc_size = 32; 1521 ecc->mode = NAND_ECC_HW; 1522 ecc->size = info->chunk_size; 1523 ecc->layout = &ecc_layout_8KB_bch8bit; 1524 ecc->strength = 16; 1525 1526 } else { 1527 dev_err(&info->pdev->dev, 1528 "ECC strength %d at page size %d is not supported\n", 1529 strength, page_size); 1530 return -ENODEV; 1531 } 1532 1533 return 0; 1534 } 1535 1536 static int pxa3xx_nand_scan(struct mtd_info *mtd) 1537 { 1538 struct nand_chip *chip = mtd_to_nand(mtd); 1539 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1540 struct pxa3xx_nand_info *info = host->info_data; 1541 struct pxa3xx_nand_platform_data *pdata = info->pdata; 1542 int ret; 1543 uint16_t ecc_strength, ecc_step; 1544 1545 if (pdata->keep_config) { 1546 pxa3xx_nand_detect_config(info); 1547 } else { 1548 ret = pxa3xx_nand_config_ident(info); 1549 if (ret) 1550 return ret; 1551 ret = pxa3xx_nand_sensing(host); 1552 if (ret) { 1553 dev_info(&info->pdev->dev, 1554 "There is no chip on cs %d!\n", 1555 info->cs); 1556 return ret; 1557 } 1558 } 1559 1560 /* Device detection must be done with ECC disabled */ 1561 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) 1562 nand_writel(info, NDECCCTRL, 0x0); 1563 1564 if (nand_scan_ident(mtd, 1, NULL)) 1565 return -ENODEV; 1566 1567 if (!pdata->keep_config) { 1568 ret = pxa3xx_nand_init_timings(host); 1569 if (ret) { 1570 dev_err(&info->pdev->dev, 1571 "Failed to set timings: %d\n", ret); 1572 return ret; 1573 } 1574 } 1575 1576 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT 1577 /* 1578 * We'll use a bad block table stored in-flash and don't 1579 * allow writing the bad block marker to the flash. 1580 */ 1581 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB_BBM; 1582 chip->bbt_td = &bbt_main_descr; 1583 chip->bbt_md = &bbt_mirror_descr; 1584 #endif 1585 1586 if (pdata->ecc_strength && pdata->ecc_step_size) { 1587 ecc_strength = pdata->ecc_strength; 1588 ecc_step = pdata->ecc_step_size; 1589 } else { 1590 ecc_strength = chip->ecc_strength_ds; 1591 ecc_step = chip->ecc_step_ds; 1592 } 1593 1594 /* Set default ECC strength requirements on non-ONFI devices */ 1595 if (ecc_strength < 1 && ecc_step < 1) { 1596 ecc_strength = 1; 1597 ecc_step = 512; 1598 } 1599 1600 ret = pxa_ecc_init(info, &chip->ecc, ecc_strength, 1601 ecc_step, mtd->writesize); 1602 if (ret) 1603 return ret; 1604 1605 /* 1606 * If the page size is bigger than the FIFO size, let's check 1607 * we are given the right variant and then switch to the extended 1608 * (aka split) command handling, 1609 */ 1610 if (mtd->writesize > info->chunk_size) { 1611 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) { 1612 chip->cmdfunc = nand_cmdfunc_extended; 1613 } else { 1614 dev_err(&info->pdev->dev, 1615 "unsupported page size on this variant\n"); 1616 return -ENODEV; 1617 } 1618 } 1619 1620 /* calculate addressing information */ 1621 if (mtd->writesize >= 2048) 1622 host->col_addr_cycles = 2; 1623 else 1624 host->col_addr_cycles = 1; 1625 1626 /* release the initial buffer */ 1627 kfree(info->data_buff); 1628 1629 /* allocate the real data + oob buffer */ 1630 info->buf_size = mtd->writesize + mtd->oobsize; 1631 ret = pxa3xx_nand_init_buff(info); 1632 if (ret) 1633 return ret; 1634 info->oob_buff = info->data_buff + mtd->writesize; 1635 1636 if ((mtd->size >> chip->page_shift) > 65536) 1637 host->row_addr_cycles = 3; 1638 else 1639 host->row_addr_cycles = 2; 1640 1641 if (!pdata->keep_config) 1642 pxa3xx_nand_config_tail(info); 1643 1644 return nand_scan_tail(mtd); 1645 } 1646 1647 static int alloc_nand_resource(struct pxa3xx_nand_info *info) 1648 { 1649 struct pxa3xx_nand_platform_data *pdata; 1650 struct pxa3xx_nand_host *host; 1651 struct nand_chip *chip = NULL; 1652 struct mtd_info *mtd; 1653 int ret, cs; 1654 1655 pdata = info->pdata; 1656 if (pdata->num_cs <= 0) 1657 return -ENODEV; 1658 1659 info->variant = pxa3xx_nand_get_variant(); 1660 for (cs = 0; cs < pdata->num_cs; cs++) { 1661 chip = (struct nand_chip *) 1662 ((u8 *)&info[1] + sizeof(*host) * cs); 1663 mtd = nand_to_mtd(chip); 1664 host = (struct pxa3xx_nand_host *)chip; 1665 info->host[cs] = host; 1666 host->cs = cs; 1667 host->info_data = info; 1668 mtd->owner = THIS_MODULE; 1669 1670 nand_set_controller_data(chip, host); 1671 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; 1672 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; 1673 chip->controller = &info->controller; 1674 chip->waitfunc = pxa3xx_nand_waitfunc; 1675 chip->select_chip = pxa3xx_nand_select_chip; 1676 chip->read_word = pxa3xx_nand_read_word; 1677 chip->read_byte = pxa3xx_nand_read_byte; 1678 chip->read_buf = pxa3xx_nand_read_buf; 1679 chip->write_buf = pxa3xx_nand_write_buf; 1680 chip->options |= NAND_NO_SUBPAGE_WRITE; 1681 chip->cmdfunc = nand_cmdfunc; 1682 } 1683 1684 /* Allocate a buffer to allow flash detection */ 1685 info->buf_size = INIT_BUFFER_SIZE; 1686 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); 1687 if (info->data_buff == NULL) { 1688 ret = -ENOMEM; 1689 goto fail_disable_clk; 1690 } 1691 1692 /* initialize all interrupts to be disabled */ 1693 disable_int(info, NDSR_MASK); 1694 1695 return 0; 1696 1697 kfree(info->data_buff); 1698 fail_disable_clk: 1699 return ret; 1700 } 1701 1702 static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info) 1703 { 1704 struct pxa3xx_nand_platform_data *pdata; 1705 const void *blob = gd->fdt_blob; 1706 int node = -1; 1707 1708 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 1709 if (!pdata) 1710 return -ENOMEM; 1711 1712 /* Get address decoding nodes from the FDT blob */ 1713 do { 1714 node = fdt_node_offset_by_compatible(blob, node, 1715 "marvell,mvebu-pxa3xx-nand"); 1716 if (node < 0) 1717 break; 1718 1719 /* Bypass disabeld nodes */ 1720 if (!fdtdec_get_is_enabled(blob, node)) 1721 continue; 1722 1723 /* Get the first enabled NAND controler base address */ 1724 info->mmio_base = 1725 (void __iomem *)fdtdec_get_addr_size_auto_noparent( 1726 blob, node, "reg", 0, NULL, true); 1727 1728 pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1); 1729 if (pdata->num_cs != 1) { 1730 pr_err("pxa3xx driver supports single CS only\n"); 1731 break; 1732 } 1733 1734 if (fdtdec_get_bool(blob, node, "nand-enable-arbiter")) 1735 pdata->enable_arbiter = 1; 1736 1737 if (fdtdec_get_bool(blob, node, "nand-keep-config")) 1738 pdata->keep_config = 1; 1739 1740 /* 1741 * ECC parameters. 1742 * If these are not set, they will be selected according 1743 * to the detected flash type. 1744 */ 1745 /* ECC strength */ 1746 pdata->ecc_strength = fdtdec_get_int(blob, node, 1747 "nand-ecc-strength", 0); 1748 1749 /* ECC step size */ 1750 pdata->ecc_step_size = fdtdec_get_int(blob, node, 1751 "nand-ecc-step-size", 0); 1752 1753 info->pdata = pdata; 1754 1755 /* Currently support only a single NAND controller */ 1756 return 0; 1757 1758 } while (node >= 0); 1759 1760 return -EINVAL; 1761 } 1762 1763 static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info) 1764 { 1765 struct pxa3xx_nand_platform_data *pdata; 1766 int ret, cs, probe_success; 1767 1768 ret = pxa3xx_nand_probe_dt(info); 1769 if (ret) 1770 return ret; 1771 1772 pdata = info->pdata; 1773 1774 ret = alloc_nand_resource(info); 1775 if (ret) { 1776 dev_err(&pdev->dev, "alloc nand resource failed\n"); 1777 return ret; 1778 } 1779 1780 probe_success = 0; 1781 for (cs = 0; cs < pdata->num_cs; cs++) { 1782 struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip); 1783 1784 /* 1785 * The mtd name matches the one used in 'mtdparts' kernel 1786 * parameter. This name cannot be changed or otherwise 1787 * user's mtd partitions configuration would get broken. 1788 */ 1789 mtd->name = "pxa3xx_nand-0"; 1790 info->cs = cs; 1791 ret = pxa3xx_nand_scan(mtd); 1792 if (ret) { 1793 dev_info(&pdev->dev, "failed to scan nand at cs %d\n", 1794 cs); 1795 continue; 1796 } 1797 1798 if (nand_register(cs, mtd)) 1799 continue; 1800 1801 probe_success = 1; 1802 } 1803 1804 if (!probe_success) 1805 return -ENODEV; 1806 1807 return 0; 1808 } 1809 1810 /* 1811 * Main initialization routine 1812 */ 1813 void board_nand_init(void) 1814 { 1815 struct pxa3xx_nand_info *info; 1816 struct pxa3xx_nand_host *host; 1817 int ret; 1818 1819 info = kzalloc(sizeof(*info) + 1820 sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE, 1821 GFP_KERNEL); 1822 if (!info) 1823 return; 1824 1825 ret = pxa3xx_nand_probe(info); 1826 if (ret) 1827 return; 1828 } 1829