1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * LPC32xx MLC NAND flash controller driver
4  *
5  * (C) Copyright 2014 3ADEV <http://3adev.com>
6  * Written by Albert ARIBAUD <albert.aribaud@3adev.fr>
7  *
8  * NOTE:
9  *
10  * The MLC NAND flash controller provides hardware Reed-Solomon ECC
11  * covering in- and out-of-band data together. Therefore, in- and out-
12  * of-band data must be written together in order to have a valid ECC.
13  *
14  * Consequently, pages with meaningful in-band data are written with
15  * blank (all-ones) out-of-band data and a valid ECC, and any later
16  * out-of-band data write will void the ECC.
17  *
18  * Therefore, code which reads such late-written out-of-band data
19  * should not rely on the ECC validity.
20  */
21 
22 #include <common.h>
23 #include <nand.h>
24 #include <linux/errno.h>
25 #include <asm/io.h>
26 #include <nand.h>
27 #include <asm/arch/clk.h>
28 #include <asm/arch/sys_proto.h>
29 
30 /*
31  * MLC NAND controller registers.
32  */
33 struct lpc32xx_nand_mlc_registers {
34 	u8 buff[32768]; /* controller's serial data buffer */
35 	u8 data[32768]; /* NAND's raw data buffer */
36 	u32 cmd;
37 	u32 addr;
38 	u32 ecc_enc_reg;
39 	u32 ecc_dec_reg;
40 	u32 ecc_auto_enc_reg;
41 	u32 ecc_auto_dec_reg;
42 	u32 rpr;
43 	u32 wpr;
44 	u32 rubp;
45 	u32 robp;
46 	u32 sw_wp_add_low;
47 	u32 sw_wp_add_hig;
48 	u32 icr;
49 	u32 time_reg;
50 	u32 irq_mr;
51 	u32 irq_sr;
52 	u32 lock_pr;
53 	u32 isr;
54 	u32 ceh;
55 };
56 
57 /* LOCK_PR register defines */
58 #define LOCK_PR_UNLOCK_KEY 0x0000A25E  /* Magic unlock value */
59 
60 /* ICR defines */
61 #define ICR_LARGE_BLOCKS 0x00000004	/* configure for 2KB blocks */
62 #define ICR_ADDR4        0x00000002	/* configure for 4-word addrs */
63 
64 /* CEH defines */
65 #define CEH_NORMAL_CE  0x00000001	/* do not force CE ON */
66 
67 /* ISR register defines */
68 #define ISR_NAND_READY        0x00000001
69 #define ISR_CONTROLLER_READY  0x00000002
70 #define ISR_ECC_READY         0x00000004
71 #define ISR_DECODER_ERRORS(s) ((((s) >> 4) & 3)+1)
72 #define ISR_DECODER_FAILURE   0x00000040
73 #define ISR_DECODER_ERROR     0x00000008
74 
75 /* time-out for NAND chip / controller loops, in us */
76 #define LPC32X_NAND_TIMEOUT 5000
77 
78 /*
79  * There is a single instance of the NAND MLC controller
80  */
81 
82 static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
83 	= (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
84 
85 #if !defined(CONFIG_SYS_MAX_NAND_CHIPS)
86 #define CONFIG_SYS_MAX_NAND_CHIPS	1
87 #endif
88 
89 #define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
90 
91 /**
92  * OOB data in each small page are 6 'free' then 10 ECC bytes.
93  * To make things easier, when reading large pages, the four pages'
94  * 'free' OOB bytes are grouped in the first 24 bytes of the OOB buffer,
95  * while the the four ECC bytes are groupe in its last 40 bytes.
96  *
97  * The struct below represents how free vs ecc oob bytes are stored
98  * in the buffer.
99  *
100  * Note: the OOB bytes contain the bad block marker at offsets 0 and 1.
101  */
102 
103 struct lpc32xx_oob {
104 	struct {
105 		uint8_t free_oob_bytes[6];
106 	} free[4];
107 	struct {
108 		uint8_t ecc_oob_bytes[10];
109 	} ecc[4];
110 };
111 
112 /*
113  * Initialize the controller
114  */
115 
116 static void lpc32xx_nand_init(void)
117 {
118 	unsigned int clk;
119 
120 	/* Configure controller for no software write protection, x8 bus
121 	   width, large block device, and 4 address words */
122 
123 	/* unlock controller registers with magic key */
124 	writel(LOCK_PR_UNLOCK_KEY,
125 	       &lpc32xx_nand_mlc_registers->lock_pr);
126 
127 	/* enable large blocks and large NANDs */
128 	writel(ICR_LARGE_BLOCKS | ICR_ADDR4,
129 	       &lpc32xx_nand_mlc_registers->icr);
130 
131 	/* Make sure MLC interrupts are disabled */
132 	writel(0, &lpc32xx_nand_mlc_registers->irq_mr);
133 
134 	/* Normal chip enable operation */
135 	writel(CEH_NORMAL_CE,
136 	       &lpc32xx_nand_mlc_registers->ceh);
137 
138 	/* Setup NAND timing */
139 	clk = get_hclk_clk_rate();
140 
141 	writel(
142 		clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) |
143 		clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) |
144 		clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA,    0x07, 16) |
145 		clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH,    0x0F, 12) |
146 		clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW,     0x0F, 8) |
147 		clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH,    0x0F, 4) |
148 		clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW,     0x0F, 0),
149 		&lpc32xx_nand_mlc_registers->time_reg);
150 }
151 
152 #if !defined(CONFIG_SPL_BUILD)
153 
154 /**
155  * lpc32xx_cmd_ctrl - write command to either cmd or data register
156  */
157 
158 static void lpc32xx_cmd_ctrl(struct mtd_info *mtd, int cmd,
159 				   unsigned int ctrl)
160 {
161 	if (cmd == NAND_CMD_NONE)
162 		return;
163 
164 	if (ctrl & NAND_CLE)
165 		writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->cmd);
166 	else if (ctrl & NAND_ALE)
167 		writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->addr);
168 }
169 
170 /**
171  * lpc32xx_read_byte - read a byte from the NAND
172  * @mtd:	MTD device structure
173  */
174 
175 static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
176 {
177 	return readb(&lpc32xx_nand_mlc_registers->data);
178 }
179 
180 /**
181  * lpc32xx_dev_ready - test if NAND device (actually controller) is ready
182  * @mtd:	MTD device structure
183  * @mode:	mode to set the ECC HW to.
184  */
185 
186 static int lpc32xx_dev_ready(struct mtd_info *mtd)
187 {
188 	/* means *controller* ready for us */
189 	int status = readl(&lpc32xx_nand_mlc_registers->isr);
190 	return status & ISR_CONTROLLER_READY;
191 }
192 
193 /**
194  * ECC layout -- this is needed whatever ECC mode we are using.
195  * In a 2KB (4*512B) page, R/S codes occupy 40 (4*10) bytes.
196  * To make U-Boot's life easier, we pack 'useable' OOB at the
197  * front and R/S ECC at the back.
198  */
199 
200 static struct nand_ecclayout lpc32xx_largepage_ecclayout = {
201 	.eccbytes = 40,
202 	.eccpos = {24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
203 		   34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
204 		   44, 45, 46, 47, 48, 48, 50, 51, 52, 53,
205 		   54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
206 		   },
207 	.oobfree = {
208 		/* bytes 0 and 1 are used for the bad block marker */
209 		{
210 			.offset = 2,
211 			.length = 22
212 		},
213 	}
214 };
215 
216 /**
217  * lpc32xx_read_page_hwecc - read in- and out-of-band data with ECC
218  * @mtd: mtd info structure
219  * @chip: nand chip info structure
220  * @buf: buffer to store read data
221  * @oob_required: caller requires OOB data read to chip->oob_poi
222  * @page: page number to read
223  *
224  * Use large block Auto Decode Read Mode(1) as described in User Manual
225  * section 8.6.2.1.
226  *
227  * The initial Read Mode and Read Start commands are sent by the caller.
228  *
229  * ECC will be false if out-of-band data has been updated since in-band
230  * data was initially written.
231  */
232 
233 static int lpc32xx_read_page_hwecc(struct mtd_info *mtd,
234 	struct nand_chip *chip, uint8_t *buf, int oob_required,
235 	int page)
236 {
237 	unsigned int i, status, timeout, err, max_bitflips = 0;
238 	struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
239 
240 	/* go through all four small pages */
241 	for (i = 0; i < 4; i++) {
242 		/* start auto decode (reads 528 NAND bytes) */
243 		writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
244 		/* wait for controller to return to ready state */
245 		for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
246 			status = readl(&lpc32xx_nand_mlc_registers->isr);
247 			if (status & ISR_CONTROLLER_READY)
248 				break;
249 			udelay(1);
250 		}
251 		/* if decoder failed, return failure */
252 		if (status & ISR_DECODER_FAILURE)
253 			return -1;
254 		/* keep count of maximum bitflips performed */
255 		if (status & ISR_DECODER_ERROR) {
256 			err = ISR_DECODER_ERRORS(status);
257 			if (err > max_bitflips)
258 				max_bitflips = err;
259 		}
260 		/* copy first 512 bytes into buffer */
261 		memcpy(buf+512*i, lpc32xx_nand_mlc_registers->buff, 512);
262 		/* copy next 6 bytes at front of OOB buffer */
263 		memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
264 		/* copy last 10 bytes (R/S ECC) at back of OOB buffer */
265 		memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
266 	}
267 	return max_bitflips;
268 }
269 
270 /**
271  * lpc32xx_read_page_raw - read raw (in-band, out-of-band and ECC) data
272  * @mtd: mtd info structure
273  * @chip: nand chip info structure
274  * @buf: buffer to store read data
275  * @oob_required: caller requires OOB data read to chip->oob_poi
276  * @page: page number to read
277  *
278  * Read NAND directly; can read pages with invalid ECC.
279  */
280 
281 static int lpc32xx_read_page_raw(struct mtd_info *mtd,
282 	struct nand_chip *chip, uint8_t *buf, int oob_required,
283 	int page)
284 {
285 	unsigned int i, status, timeout;
286 	struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
287 
288 	/* when we get here we've already had the Read Mode(1) */
289 
290 	/* go through all four small pages */
291 	for (i = 0; i < 4; i++) {
292 		/* wait for NAND to return to ready state */
293 		for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
294 			status = readl(&lpc32xx_nand_mlc_registers->isr);
295 			if (status & ISR_NAND_READY)
296 				break;
297 			udelay(1);
298 		}
299 		/* if NAND stalled, return failure */
300 		if (!(status & ISR_NAND_READY))
301 			return -1;
302 		/* copy first 512 bytes into buffer */
303 		memcpy(buf+512*i, lpc32xx_nand_mlc_registers->data, 512);
304 		/* copy next 6 bytes at front of OOB buffer */
305 		memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->data, 6);
306 		/* copy last 10 bytes (R/S ECC) at back of OOB buffer */
307 		memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->data, 10);
308 	}
309 	return 0;
310 }
311 
312 /**
313  * lpc32xx_read_oob - read out-of-band data
314  * @mtd: mtd info structure
315  * @chip: nand chip info structure
316  * @page: page number to read
317  *
318  * Read out-of-band data. User Manual section 8.6.4 suggests using Read
319  * Mode(3) which the controller will turn into a Read Mode(1) internally
320  * but nand_base.c will turn Mode(3) into Mode(0), so let's use Mode(0)
321  * directly.
322  *
323  * ECC covers in- and out-of-band data and was written when out-of-band
324  * data was blank. Therefore, if the out-of-band being read here is not
325  * blank, then the ECC will be false and the read will return bitflips,
326  * even in case of ECC failure where we will return 5 bitflips. The
327  * caller should be prepared to handle this.
328  */
329 
330 static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
331 	int page)
332 {
333 	unsigned int i, status, timeout, err, max_bitflips = 0;
334 	struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
335 
336 	/* No command was sent before calling read_oob() so send one */
337 
338 	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
339 
340 	/* go through all four small pages */
341 	for (i = 0; i < 4; i++) {
342 		/* start auto decode (reads 528 NAND bytes) */
343 		writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
344 		/* wait for controller to return to ready state */
345 		for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
346 			status = readl(&lpc32xx_nand_mlc_registers->isr);
347 			if (status & ISR_CONTROLLER_READY)
348 				break;
349 			udelay(1);
350 		}
351 		/* if decoder failure, count 'one too many' bitflips */
352 		if (status & ISR_DECODER_FAILURE)
353 			max_bitflips = 5;
354 		/* keep count of maximum bitflips performed */
355 		if (status & ISR_DECODER_ERROR) {
356 			err = ISR_DECODER_ERRORS(status);
357 			if (err > max_bitflips)
358 				max_bitflips = err;
359 		}
360 		/* set read pointer to OOB area */
361 		writel(0, &lpc32xx_nand_mlc_registers->robp);
362 		/* copy next 6 bytes at front of OOB buffer */
363 		memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
364 		/* copy next 10 bytes (R/S ECC) at back of OOB buffer */
365 		memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
366 	}
367 	return max_bitflips;
368 }
369 
370 /**
371  * lpc32xx_write_page_hwecc - write in- and out-of-band data with ECC
372  * @mtd: mtd info structure
373  * @chip: nand chip info structure
374  * @buf: data buffer
375  * @oob_required: must write chip->oob_poi to OOB
376  *
377  * Use large block Auto Encode as per User Manual section 8.6.4.
378  *
379  * The initial Write Serial Input and final Auto Program commands are
380  * sent by the caller.
381  */
382 
383 static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
384 	struct nand_chip *chip, const uint8_t *buf, int oob_required,
385 	int page)
386 {
387 	unsigned int i, status, timeout;
388 	struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
389 
390 	/* when we get here we've already had the SEQIN */
391 	for (i = 0; i < 4; i++) {
392 		/* start encode (expects 518 writes to buff) */
393 		writel(0, &lpc32xx_nand_mlc_registers->ecc_enc_reg);
394 		/* copy first 512 bytes from buffer */
395 		memcpy(&lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
396 		/* copy next 6 bytes from OOB buffer -- excluding ECC */
397 		memcpy(&lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
398 		/* wait for ECC to return to ready state */
399 		for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
400 			status = readl(&lpc32xx_nand_mlc_registers->isr);
401 			if (status & ISR_ECC_READY)
402 				break;
403 			udelay(1);
404 		}
405 		/* if ECC stalled, return failure */
406 		if (!(status & ISR_ECC_READY))
407 			return -1;
408 		/* Trigger auto encode (writes 528 bytes to NAND) */
409 		writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_enc_reg);
410 		/* wait for controller to return to ready state */
411 		for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
412 			status = readl(&lpc32xx_nand_mlc_registers->isr);
413 			if (status & ISR_CONTROLLER_READY)
414 				break;
415 			udelay(1);
416 		}
417 		/* if controller stalled, return error */
418 		if (!(status & ISR_CONTROLLER_READY))
419 			return -1;
420 	}
421 	return 0;
422 }
423 
424 /**
425  * lpc32xx_write_page_raw - write raw (in-band, out-of-band and ECC) data
426  * @mtd: mtd info structure
427  * @chip: nand chip info structure
428  * @buf: buffer to store read data
429  * @oob_required: caller requires OOB data read to chip->oob_poi
430  * @page: page number to read
431  *
432  * Use large block write but without encode.
433  *
434  * The initial Write Serial Input and final Auto Program commands are
435  * sent by the caller.
436  *
437  * This function will write the full out-of-band data, including the
438  * ECC area. Therefore, it can write pages with valid *or* invalid ECC.
439  */
440 
441 static int lpc32xx_write_page_raw(struct mtd_info *mtd,
442 	struct nand_chip *chip, const uint8_t *buf, int oob_required,
443 	int page)
444 {
445 	unsigned int i;
446 	struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
447 
448 	/* when we get here we've already had the Read Mode(1) */
449 	for (i = 0; i < 4; i++) {
450 		/* copy first 512 bytes from buffer */
451 		memcpy(lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
452 		/* copy next 6 bytes into OOB buffer -- excluding ECC */
453 		memcpy(lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
454 		/* copy next 10 bytes into OOB buffer -- that is 'ECC' */
455 		memcpy(lpc32xx_nand_mlc_registers->buff, &oob->ecc[i], 10);
456 	}
457 	return 0;
458 }
459 
460 /**
461  * lpc32xx_write_oob - write out-of-band data
462  * @mtd: mtd info structure
463  * @chip: nand chip info structure
464  * @page: page number to read
465  *
466  * Since ECC covers in- and out-of-band data, writing out-of-band data
467  * with ECC will render the page ECC wrong -- or, if the page was blank,
468  * then it will produce a good ECC but a later in-band data write will
469  * render it wrong.
470  *
471  * Therefore, do not compute or write any ECC, and always return success.
472  *
473  * This implies that we do four writes, since non-ECC out-of-band data
474  * are not contiguous in a large page.
475  */
476 
477 static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
478 	int page)
479 {
480 	/* update oob on all 4 subpages in sequence */
481 	unsigned int i, status, timeout;
482 	struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
483 
484 	for (i = 0; i < 4; i++) {
485 		/* start data input */
486 		chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x200+0x210*i, page);
487 		/* copy 6 non-ECC out-of-band bytes directly into NAND */
488 		memcpy(lpc32xx_nand_mlc_registers->data, &oob->free[i], 6);
489 		/* program page */
490 		chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
491 		/* wait for NAND to return to ready state */
492 		for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
493 			status = readl(&lpc32xx_nand_mlc_registers->isr);
494 			if (status & ISR_NAND_READY)
495 				break;
496 			udelay(1);
497 		}
498 		/* if NAND stalled, return error */
499 		if (!(status & ISR_NAND_READY))
500 			return -1;
501 	}
502 	return 0;
503 }
504 
505 /**
506  * lpc32xx_waitfunc - wait until a command is done
507  * @mtd: MTD device structure
508  * @chip: NAND chip structure
509  *
510  * Wait for controller and FLASH to both be ready.
511  */
512 
513 static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
514 {
515 	int status;
516 	unsigned int timeout;
517 	/* wait until both controller and NAND are ready */
518 	for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
519 		status = readl(&lpc32xx_nand_mlc_registers->isr);
520 		if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
521 		    == (ISR_CONTROLLER_READY || ISR_NAND_READY))
522 			break;
523 		udelay(1);
524 	}
525 	/* if controller or NAND stalled, return error */
526 	if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
527 	    != (ISR_CONTROLLER_READY || ISR_NAND_READY))
528 		return -1;
529 	/* write NAND status command */
530 	writel(NAND_CMD_STATUS, &lpc32xx_nand_mlc_registers->cmd);
531 	/* read back status and return it */
532 	return readb(&lpc32xx_nand_mlc_registers->data);
533 }
534 
535 /*
536  * We are self-initializing, so we need our own chip struct
537  */
538 
539 static struct nand_chip lpc32xx_chip;
540 
541 /*
542  * Initialize the controller
543  */
544 
545 void board_nand_init(void)
546 {
547 	struct mtd_info *mtd = nand_to_mtd(&lpc32xx_chip);
548 	int ret;
549 
550 	/* Set all BOARDSPECIFIC (actually core-specific) fields  */
551 
552 	lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
553 	lpc32xx_chip.IO_ADDR_W = &lpc32xx_nand_mlc_registers->buff;
554 	lpc32xx_chip.cmd_ctrl = lpc32xx_cmd_ctrl;
555 	/* do not set init_size: nand_base.c will read sizes from chip */
556 	lpc32xx_chip.dev_ready = lpc32xx_dev_ready;
557 	/* do not set setup_read_retry: this is NAND-chip-specific */
558 	/* do not set chip_delay: we have dev_ready defined. */
559 	lpc32xx_chip.options |= NAND_NO_SUBPAGE_WRITE;
560 
561 	/* Set needed ECC fields */
562 
563 	lpc32xx_chip.ecc.mode = NAND_ECC_HW;
564 	lpc32xx_chip.ecc.layout = &lpc32xx_largepage_ecclayout;
565 	lpc32xx_chip.ecc.size = 512;
566 	lpc32xx_chip.ecc.bytes = 10;
567 	lpc32xx_chip.ecc.strength = 4;
568 	lpc32xx_chip.ecc.read_page = lpc32xx_read_page_hwecc;
569 	lpc32xx_chip.ecc.read_page_raw = lpc32xx_read_page_raw;
570 	lpc32xx_chip.ecc.write_page = lpc32xx_write_page_hwecc;
571 	lpc32xx_chip.ecc.write_page_raw = lpc32xx_write_page_raw;
572 	lpc32xx_chip.ecc.read_oob = lpc32xx_read_oob;
573 	lpc32xx_chip.ecc.write_oob = lpc32xx_write_oob;
574 	lpc32xx_chip.waitfunc = lpc32xx_waitfunc;
575 
576 	lpc32xx_chip.read_byte = lpc32xx_read_byte; /* FIXME: NEEDED? */
577 
578 	/* BBT options: read from last two pages */
579 	lpc32xx_chip.bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_LASTBLOCK
580 		| NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE
581 		| NAND_BBT_WRITE;
582 
583 	/* Initialize NAND interface */
584 	lpc32xx_nand_init();
585 
586 	/* identify chip */
587 	ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL);
588 	if (ret) {
589 		pr_err("nand_scan_ident returned %i", ret);
590 		return;
591 	}
592 
593 	/* finish scanning the chip */
594 	ret = nand_scan_tail(mtd);
595 	if (ret) {
596 		pr_err("nand_scan_tail returned %i", ret);
597 		return;
598 	}
599 
600 	/* chip is good, register it */
601 	ret = nand_register(0, mtd);
602 	if (ret)
603 		pr_err("nand_register returned %i", ret);
604 }
605 
606 #else /* defined(CONFIG_SPL_BUILD) */
607 
608 void nand_init(void)
609 {
610 	/* enable NAND controller */
611 	lpc32xx_mlc_nand_init();
612 	/* initialize NAND controller */
613 	lpc32xx_nand_init();
614 }
615 
616 void nand_deselect(void)
617 {
618 	/* nothing to do, but SPL requires this function */
619 }
620 
621 static int read_single_page(uint8_t *dest, int page,
622 	struct lpc32xx_oob *oob)
623 {
624 	int status, i, timeout, err, max_bitflips = 0;
625 
626 	/* enter read mode */
627 	writel(NAND_CMD_READ0, &lpc32xx_nand_mlc_registers->cmd);
628 	/* send column (lsb then MSB) and page (lsb to MSB) */
629 	writel(0, &lpc32xx_nand_mlc_registers->addr);
630 	writel(0, &lpc32xx_nand_mlc_registers->addr);
631 	writel(page & 0xff, &lpc32xx_nand_mlc_registers->addr);
632 	writel((page>>8) & 0xff, &lpc32xx_nand_mlc_registers->addr);
633 	writel((page>>16) & 0xff, &lpc32xx_nand_mlc_registers->addr);
634 	/* start reading */
635 	writel(NAND_CMD_READSTART, &lpc32xx_nand_mlc_registers->cmd);
636 
637 	/* large page auto decode read */
638 	for (i = 0; i < 4; i++) {
639 		/* start auto decode (reads 528 NAND bytes) */
640 		writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
641 		/* wait for controller to return to ready state */
642 		for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
643 			status = readl(&lpc32xx_nand_mlc_registers->isr);
644 			if (status & ISR_CONTROLLER_READY)
645 				break;
646 			udelay(1);
647 		}
648 		/* if controller stalled, return error */
649 		if (!(status & ISR_CONTROLLER_READY))
650 			return -1;
651 		/* if decoder failure, return error */
652 		if (status & ISR_DECODER_FAILURE)
653 			return -1;
654 		/* keep count of maximum bitflips performed */
655 		if (status & ISR_DECODER_ERROR) {
656 			err = ISR_DECODER_ERRORS(status);
657 			if (err > max_bitflips)
658 				max_bitflips = err;
659 		}
660 		/* copy first 512 bytes into buffer */
661 		memcpy(dest+i*512, lpc32xx_nand_mlc_registers->buff, 512);
662 		/* copy next 6 bytes bytes into OOB buffer */
663 		memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
664 	}
665 	return max_bitflips;
666 }
667 
668 /*
669  * Load U-Boot signed image.
670  * This loads an image from NAND, skipping bad blocks.
671  * A block is declared bad if at least one of its readable pages has
672  * a bad block marker in its OOB at position 0.
673  * If all pages ion a block are unreadable, the block is considered
674  * bad (i.e., assumed not to be part of the image) and skipped.
675  *
676  * IMPORTANT NOTE:
677  *
678  * If the first block of the image is fully unreadable, it will be
679  * ignored and skipped as if it had been marked bad. If it was not
680  * actually marked bad at the time of writing the image, the resulting
681  * image loaded will lack a header and magic number. It could thus be
682  * considered as a raw, headerless, image and SPL might erroneously
683  * jump into it.
684  *
685  * In order to avoid this risk, LPC32XX-based boards which use this
686  * driver MUST define CONFIG_SPL_PANIC_ON_RAW_IMAGE.
687  */
688 
689 #define BYTES_PER_PAGE 2048
690 #define PAGES_PER_BLOCK 64
691 #define BYTES_PER_BLOCK (BYTES_PER_PAGE * PAGES_PER_BLOCK)
692 #define PAGES_PER_CHIP_MAX 524288
693 
694 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
695 {
696 	int bytes_left = size;
697 	int pages_left = DIV_ROUND_UP(size, BYTES_PER_PAGE);
698 	int blocks_left = DIV_ROUND_UP(size, BYTES_PER_BLOCK);
699 	int block = 0;
700 	int page = offs / BYTES_PER_PAGE;
701 	/* perform reads block by block */
702 	while (blocks_left) {
703 		/* compute first page number to read */
704 		void *block_page_dst = dst;
705 		/* read at most one block, possibly less */
706 		int block_bytes_left = bytes_left;
707 		if (block_bytes_left > BYTES_PER_BLOCK)
708 			block_bytes_left = BYTES_PER_BLOCK;
709 		/* keep track of good, failed, and "bad" pages */
710 		int block_pages_good = 0;
711 		int block_pages_bad = 0;
712 		int block_pages_err = 0;
713 		/* we shall read a full block of pages, maybe less */
714 		int block_pages_left = pages_left;
715 		if (block_pages_left > PAGES_PER_BLOCK)
716 			block_pages_left = PAGES_PER_BLOCK;
717 		int block_pages = block_pages_left;
718 		int block_page = page;
719 		/* while pages are left and the block is not known as bad */
720 		while ((block_pages > 0) && (block_pages_bad == 0)) {
721 			/* we will read OOB, too, for bad block markers */
722 			struct lpc32xx_oob oob;
723 			/* read page */
724 			int res = read_single_page(block_page_dst, block_page,
725 						   &oob);
726 			/* count readable pages */
727 			if (res >= 0) {
728 				/* this page is good */
729 				block_pages_good++;
730 				/* this page is bad */
731 				if ((oob.free[0].free_oob_bytes[0] != 0xff)
732 				    | (oob.free[0].free_oob_bytes[1] != 0xff))
733 					block_pages_bad++;
734 			} else
735 				/* count errors */
736 				block_pages_err++;
737 			/* we're done with this page */
738 			block_page++;
739 			block_page_dst += BYTES_PER_PAGE;
740 			if (block_pages)
741 				block_pages--;
742 		}
743 		/* a fully unreadable block is considered bad */
744 		if (block_pages_good == 0)
745 			block_pages_bad = block_pages_err;
746 		/* errors are fatal only in good blocks */
747 		if ((block_pages_err > 0) && (block_pages_bad == 0))
748 			return -1;
749 		/* we keep reads only of good blocks */
750 		if (block_pages_bad == 0) {
751 			dst += block_bytes_left;
752 			bytes_left -= block_bytes_left;
753 			pages_left -= block_pages_left;
754 			blocks_left--;
755 		}
756 		/* good or bad, we're done with this block */
757 		block++;
758 		page += PAGES_PER_BLOCK;
759 	}
760 
761 	/* report success */
762 	return 0;
763 }
764 
765 #endif /* CONFIG_SPL_BUILD */
766