1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * LPC32xx MLC NAND flash controller driver 4 * 5 * (C) Copyright 2014 3ADEV <http://3adev.com> 6 * Written by Albert ARIBAUD <albert.aribaud@3adev.fr> 7 * 8 * NOTE: 9 * 10 * The MLC NAND flash controller provides hardware Reed-Solomon ECC 11 * covering in- and out-of-band data together. Therefore, in- and out- 12 * of-band data must be written together in order to have a valid ECC. 13 * 14 * Consequently, pages with meaningful in-band data are written with 15 * blank (all-ones) out-of-band data and a valid ECC, and any later 16 * out-of-band data write will void the ECC. 17 * 18 * Therefore, code which reads such late-written out-of-band data 19 * should not rely on the ECC validity. 20 */ 21 22 #include <common.h> 23 #include <nand.h> 24 #include <linux/errno.h> 25 #include <asm/io.h> 26 #include <nand.h> 27 #include <asm/arch/clk.h> 28 #include <asm/arch/sys_proto.h> 29 30 /* 31 * MLC NAND controller registers. 32 */ 33 struct lpc32xx_nand_mlc_registers { 34 u8 buff[32768]; /* controller's serial data buffer */ 35 u8 data[32768]; /* NAND's raw data buffer */ 36 u32 cmd; 37 u32 addr; 38 u32 ecc_enc_reg; 39 u32 ecc_dec_reg; 40 u32 ecc_auto_enc_reg; 41 u32 ecc_auto_dec_reg; 42 u32 rpr; 43 u32 wpr; 44 u32 rubp; 45 u32 robp; 46 u32 sw_wp_add_low; 47 u32 sw_wp_add_hig; 48 u32 icr; 49 u32 time_reg; 50 u32 irq_mr; 51 u32 irq_sr; 52 u32 lock_pr; 53 u32 isr; 54 u32 ceh; 55 }; 56 57 /* LOCK_PR register defines */ 58 #define LOCK_PR_UNLOCK_KEY 0x0000A25E /* Magic unlock value */ 59 60 /* ICR defines */ 61 #define ICR_LARGE_BLOCKS 0x00000004 /* configure for 2KB blocks */ 62 #define ICR_ADDR4 0x00000002 /* configure for 4-word addrs */ 63 64 /* CEH defines */ 65 #define CEH_NORMAL_CE 0x00000001 /* do not force CE ON */ 66 67 /* ISR register defines */ 68 #define ISR_NAND_READY 0x00000001 69 #define ISR_CONTROLLER_READY 0x00000002 70 #define ISR_ECC_READY 0x00000004 71 #define ISR_DECODER_ERRORS(s) ((((s) >> 4) & 3)+1) 72 #define ISR_DECODER_FAILURE 0x00000040 73 #define ISR_DECODER_ERROR 0x00000008 74 75 /* time-out for NAND chip / controller loops, in us */ 76 #define LPC32X_NAND_TIMEOUT 5000 77 78 /* 79 * There is a single instance of the NAND MLC controller 80 */ 81 82 static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers 83 = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE; 84 85 #define clkdiv(v, w, o) (((1+(clk/v)) & w) << o) 86 87 /** 88 * OOB data in each small page are 6 'free' then 10 ECC bytes. 89 * To make things easier, when reading large pages, the four pages' 90 * 'free' OOB bytes are grouped in the first 24 bytes of the OOB buffer, 91 * while the the four ECC bytes are groupe in its last 40 bytes. 92 * 93 * The struct below represents how free vs ecc oob bytes are stored 94 * in the buffer. 95 * 96 * Note: the OOB bytes contain the bad block marker at offsets 0 and 1. 97 */ 98 99 struct lpc32xx_oob { 100 struct { 101 uint8_t free_oob_bytes[6]; 102 } free[4]; 103 struct { 104 uint8_t ecc_oob_bytes[10]; 105 } ecc[4]; 106 }; 107 108 /* 109 * Initialize the controller 110 */ 111 112 static void lpc32xx_nand_init(void) 113 { 114 unsigned int clk; 115 116 /* Configure controller for no software write protection, x8 bus 117 width, large block device, and 4 address words */ 118 119 /* unlock controller registers with magic key */ 120 writel(LOCK_PR_UNLOCK_KEY, 121 &lpc32xx_nand_mlc_registers->lock_pr); 122 123 /* enable large blocks and large NANDs */ 124 writel(ICR_LARGE_BLOCKS | ICR_ADDR4, 125 &lpc32xx_nand_mlc_registers->icr); 126 127 /* Make sure MLC interrupts are disabled */ 128 writel(0, &lpc32xx_nand_mlc_registers->irq_mr); 129 130 /* Normal chip enable operation */ 131 writel(CEH_NORMAL_CE, 132 &lpc32xx_nand_mlc_registers->ceh); 133 134 /* Setup NAND timing */ 135 clk = get_hclk_clk_rate(); 136 137 writel( 138 clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | 139 clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | 140 clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | 141 clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | 142 clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | 143 clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | 144 clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), 145 &lpc32xx_nand_mlc_registers->time_reg); 146 } 147 148 #if !defined(CONFIG_SPL_BUILD) 149 150 /** 151 * lpc32xx_cmd_ctrl - write command to either cmd or data register 152 */ 153 154 static void lpc32xx_cmd_ctrl(struct mtd_info *mtd, int cmd, 155 unsigned int ctrl) 156 { 157 if (cmd == NAND_CMD_NONE) 158 return; 159 160 if (ctrl & NAND_CLE) 161 writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->cmd); 162 else if (ctrl & NAND_ALE) 163 writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->addr); 164 } 165 166 /** 167 * lpc32xx_read_byte - read a byte from the NAND 168 * @mtd: MTD device structure 169 */ 170 171 static uint8_t lpc32xx_read_byte(struct mtd_info *mtd) 172 { 173 return readb(&lpc32xx_nand_mlc_registers->data); 174 } 175 176 /** 177 * lpc32xx_dev_ready - test if NAND device (actually controller) is ready 178 * @mtd: MTD device structure 179 * @mode: mode to set the ECC HW to. 180 */ 181 182 static int lpc32xx_dev_ready(struct mtd_info *mtd) 183 { 184 /* means *controller* ready for us */ 185 int status = readl(&lpc32xx_nand_mlc_registers->isr); 186 return status & ISR_CONTROLLER_READY; 187 } 188 189 /** 190 * ECC layout -- this is needed whatever ECC mode we are using. 191 * In a 2KB (4*512B) page, R/S codes occupy 40 (4*10) bytes. 192 * To make U-Boot's life easier, we pack 'useable' OOB at the 193 * front and R/S ECC at the back. 194 */ 195 196 static struct nand_ecclayout lpc32xx_largepage_ecclayout = { 197 .eccbytes = 40, 198 .eccpos = {24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 199 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 200 44, 45, 46, 47, 48, 48, 50, 51, 52, 53, 201 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 202 }, 203 .oobfree = { 204 /* bytes 0 and 1 are used for the bad block marker */ 205 { 206 .offset = 2, 207 .length = 22 208 }, 209 } 210 }; 211 212 /** 213 * lpc32xx_read_page_hwecc - read in- and out-of-band data with ECC 214 * @mtd: mtd info structure 215 * @chip: nand chip info structure 216 * @buf: buffer to store read data 217 * @oob_required: caller requires OOB data read to chip->oob_poi 218 * @page: page number to read 219 * 220 * Use large block Auto Decode Read Mode(1) as described in User Manual 221 * section 8.6.2.1. 222 * 223 * The initial Read Mode and Read Start commands are sent by the caller. 224 * 225 * ECC will be false if out-of-band data has been updated since in-band 226 * data was initially written. 227 */ 228 229 static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, 230 struct nand_chip *chip, uint8_t *buf, int oob_required, 231 int page) 232 { 233 unsigned int i, status, timeout, err, max_bitflips = 0; 234 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; 235 236 /* go through all four small pages */ 237 for (i = 0; i < 4; i++) { 238 /* start auto decode (reads 528 NAND bytes) */ 239 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg); 240 /* wait for controller to return to ready state */ 241 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { 242 status = readl(&lpc32xx_nand_mlc_registers->isr); 243 if (status & ISR_CONTROLLER_READY) 244 break; 245 udelay(1); 246 } 247 /* if decoder failed, return failure */ 248 if (status & ISR_DECODER_FAILURE) 249 return -1; 250 /* keep count of maximum bitflips performed */ 251 if (status & ISR_DECODER_ERROR) { 252 err = ISR_DECODER_ERRORS(status); 253 if (err > max_bitflips) 254 max_bitflips = err; 255 } 256 /* copy first 512 bytes into buffer */ 257 memcpy(buf+512*i, lpc32xx_nand_mlc_registers->buff, 512); 258 /* copy next 6 bytes at front of OOB buffer */ 259 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6); 260 /* copy last 10 bytes (R/S ECC) at back of OOB buffer */ 261 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10); 262 } 263 return max_bitflips; 264 } 265 266 /** 267 * lpc32xx_read_page_raw - read raw (in-band, out-of-band and ECC) data 268 * @mtd: mtd info structure 269 * @chip: nand chip info structure 270 * @buf: buffer to store read data 271 * @oob_required: caller requires OOB data read to chip->oob_poi 272 * @page: page number to read 273 * 274 * Read NAND directly; can read pages with invalid ECC. 275 */ 276 277 static int lpc32xx_read_page_raw(struct mtd_info *mtd, 278 struct nand_chip *chip, uint8_t *buf, int oob_required, 279 int page) 280 { 281 unsigned int i, status, timeout; 282 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; 283 284 /* when we get here we've already had the Read Mode(1) */ 285 286 /* go through all four small pages */ 287 for (i = 0; i < 4; i++) { 288 /* wait for NAND to return to ready state */ 289 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { 290 status = readl(&lpc32xx_nand_mlc_registers->isr); 291 if (status & ISR_NAND_READY) 292 break; 293 udelay(1); 294 } 295 /* if NAND stalled, return failure */ 296 if (!(status & ISR_NAND_READY)) 297 return -1; 298 /* copy first 512 bytes into buffer */ 299 memcpy(buf+512*i, lpc32xx_nand_mlc_registers->data, 512); 300 /* copy next 6 bytes at front of OOB buffer */ 301 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->data, 6); 302 /* copy last 10 bytes (R/S ECC) at back of OOB buffer */ 303 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->data, 10); 304 } 305 return 0; 306 } 307 308 /** 309 * lpc32xx_read_oob - read out-of-band data 310 * @mtd: mtd info structure 311 * @chip: nand chip info structure 312 * @page: page number to read 313 * 314 * Read out-of-band data. User Manual section 8.6.4 suggests using Read 315 * Mode(3) which the controller will turn into a Read Mode(1) internally 316 * but nand_base.c will turn Mode(3) into Mode(0), so let's use Mode(0) 317 * directly. 318 * 319 * ECC covers in- and out-of-band data and was written when out-of-band 320 * data was blank. Therefore, if the out-of-band being read here is not 321 * blank, then the ECC will be false and the read will return bitflips, 322 * even in case of ECC failure where we will return 5 bitflips. The 323 * caller should be prepared to handle this. 324 */ 325 326 static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 327 int page) 328 { 329 unsigned int i, status, timeout, err, max_bitflips = 0; 330 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; 331 332 /* No command was sent before calling read_oob() so send one */ 333 334 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); 335 336 /* go through all four small pages */ 337 for (i = 0; i < 4; i++) { 338 /* start auto decode (reads 528 NAND bytes) */ 339 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg); 340 /* wait for controller to return to ready state */ 341 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { 342 status = readl(&lpc32xx_nand_mlc_registers->isr); 343 if (status & ISR_CONTROLLER_READY) 344 break; 345 udelay(1); 346 } 347 /* if decoder failure, count 'one too many' bitflips */ 348 if (status & ISR_DECODER_FAILURE) 349 max_bitflips = 5; 350 /* keep count of maximum bitflips performed */ 351 if (status & ISR_DECODER_ERROR) { 352 err = ISR_DECODER_ERRORS(status); 353 if (err > max_bitflips) 354 max_bitflips = err; 355 } 356 /* set read pointer to OOB area */ 357 writel(0, &lpc32xx_nand_mlc_registers->robp); 358 /* copy next 6 bytes at front of OOB buffer */ 359 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6); 360 /* copy next 10 bytes (R/S ECC) at back of OOB buffer */ 361 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10); 362 } 363 return max_bitflips; 364 } 365 366 /** 367 * lpc32xx_write_page_hwecc - write in- and out-of-band data with ECC 368 * @mtd: mtd info structure 369 * @chip: nand chip info structure 370 * @buf: data buffer 371 * @oob_required: must write chip->oob_poi to OOB 372 * 373 * Use large block Auto Encode as per User Manual section 8.6.4. 374 * 375 * The initial Write Serial Input and final Auto Program commands are 376 * sent by the caller. 377 */ 378 379 static int lpc32xx_write_page_hwecc(struct mtd_info *mtd, 380 struct nand_chip *chip, const uint8_t *buf, int oob_required, 381 int page) 382 { 383 unsigned int i, status, timeout; 384 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; 385 386 /* when we get here we've already had the SEQIN */ 387 for (i = 0; i < 4; i++) { 388 /* start encode (expects 518 writes to buff) */ 389 writel(0, &lpc32xx_nand_mlc_registers->ecc_enc_reg); 390 /* copy first 512 bytes from buffer */ 391 memcpy(&lpc32xx_nand_mlc_registers->buff, buf+512*i, 512); 392 /* copy next 6 bytes from OOB buffer -- excluding ECC */ 393 memcpy(&lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6); 394 /* wait for ECC to return to ready state */ 395 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { 396 status = readl(&lpc32xx_nand_mlc_registers->isr); 397 if (status & ISR_ECC_READY) 398 break; 399 udelay(1); 400 } 401 /* if ECC stalled, return failure */ 402 if (!(status & ISR_ECC_READY)) 403 return -1; 404 /* Trigger auto encode (writes 528 bytes to NAND) */ 405 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_enc_reg); 406 /* wait for controller to return to ready state */ 407 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { 408 status = readl(&lpc32xx_nand_mlc_registers->isr); 409 if (status & ISR_CONTROLLER_READY) 410 break; 411 udelay(1); 412 } 413 /* if controller stalled, return error */ 414 if (!(status & ISR_CONTROLLER_READY)) 415 return -1; 416 } 417 return 0; 418 } 419 420 /** 421 * lpc32xx_write_page_raw - write raw (in-band, out-of-band and ECC) data 422 * @mtd: mtd info structure 423 * @chip: nand chip info structure 424 * @buf: buffer to store read data 425 * @oob_required: caller requires OOB data read to chip->oob_poi 426 * @page: page number to read 427 * 428 * Use large block write but without encode. 429 * 430 * The initial Write Serial Input and final Auto Program commands are 431 * sent by the caller. 432 * 433 * This function will write the full out-of-band data, including the 434 * ECC area. Therefore, it can write pages with valid *or* invalid ECC. 435 */ 436 437 static int lpc32xx_write_page_raw(struct mtd_info *mtd, 438 struct nand_chip *chip, const uint8_t *buf, int oob_required, 439 int page) 440 { 441 unsigned int i; 442 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; 443 444 /* when we get here we've already had the Read Mode(1) */ 445 for (i = 0; i < 4; i++) { 446 /* copy first 512 bytes from buffer */ 447 memcpy(lpc32xx_nand_mlc_registers->buff, buf+512*i, 512); 448 /* copy next 6 bytes into OOB buffer -- excluding ECC */ 449 memcpy(lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6); 450 /* copy next 10 bytes into OOB buffer -- that is 'ECC' */ 451 memcpy(lpc32xx_nand_mlc_registers->buff, &oob->ecc[i], 10); 452 } 453 return 0; 454 } 455 456 /** 457 * lpc32xx_write_oob - write out-of-band data 458 * @mtd: mtd info structure 459 * @chip: nand chip info structure 460 * @page: page number to read 461 * 462 * Since ECC covers in- and out-of-band data, writing out-of-band data 463 * with ECC will render the page ECC wrong -- or, if the page was blank, 464 * then it will produce a good ECC but a later in-band data write will 465 * render it wrong. 466 * 467 * Therefore, do not compute or write any ECC, and always return success. 468 * 469 * This implies that we do four writes, since non-ECC out-of-band data 470 * are not contiguous in a large page. 471 */ 472 473 static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 474 int page) 475 { 476 /* update oob on all 4 subpages in sequence */ 477 unsigned int i, status, timeout; 478 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi; 479 480 for (i = 0; i < 4; i++) { 481 /* start data input */ 482 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x200+0x210*i, page); 483 /* copy 6 non-ECC out-of-band bytes directly into NAND */ 484 memcpy(lpc32xx_nand_mlc_registers->data, &oob->free[i], 6); 485 /* program page */ 486 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 487 /* wait for NAND to return to ready state */ 488 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { 489 status = readl(&lpc32xx_nand_mlc_registers->isr); 490 if (status & ISR_NAND_READY) 491 break; 492 udelay(1); 493 } 494 /* if NAND stalled, return error */ 495 if (!(status & ISR_NAND_READY)) 496 return -1; 497 } 498 return 0; 499 } 500 501 /** 502 * lpc32xx_waitfunc - wait until a command is done 503 * @mtd: MTD device structure 504 * @chip: NAND chip structure 505 * 506 * Wait for controller and FLASH to both be ready. 507 */ 508 509 static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) 510 { 511 int status; 512 unsigned int timeout; 513 /* wait until both controller and NAND are ready */ 514 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { 515 status = readl(&lpc32xx_nand_mlc_registers->isr); 516 if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY)) 517 == (ISR_CONTROLLER_READY || ISR_NAND_READY)) 518 break; 519 udelay(1); 520 } 521 /* if controller or NAND stalled, return error */ 522 if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY)) 523 != (ISR_CONTROLLER_READY || ISR_NAND_READY)) 524 return -1; 525 /* write NAND status command */ 526 writel(NAND_CMD_STATUS, &lpc32xx_nand_mlc_registers->cmd); 527 /* read back status and return it */ 528 return readb(&lpc32xx_nand_mlc_registers->data); 529 } 530 531 /* 532 * We are self-initializing, so we need our own chip struct 533 */ 534 535 static struct nand_chip lpc32xx_chip; 536 537 /* 538 * Initialize the controller 539 */ 540 541 void board_nand_init(void) 542 { 543 struct mtd_info *mtd = nand_to_mtd(&lpc32xx_chip); 544 int ret; 545 546 /* Set all BOARDSPECIFIC (actually core-specific) fields */ 547 548 lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff; 549 lpc32xx_chip.IO_ADDR_W = &lpc32xx_nand_mlc_registers->buff; 550 lpc32xx_chip.cmd_ctrl = lpc32xx_cmd_ctrl; 551 /* do not set init_size: nand_base.c will read sizes from chip */ 552 lpc32xx_chip.dev_ready = lpc32xx_dev_ready; 553 /* do not set setup_read_retry: this is NAND-chip-specific */ 554 /* do not set chip_delay: we have dev_ready defined. */ 555 lpc32xx_chip.options |= NAND_NO_SUBPAGE_WRITE; 556 557 /* Set needed ECC fields */ 558 559 lpc32xx_chip.ecc.mode = NAND_ECC_HW; 560 lpc32xx_chip.ecc.layout = &lpc32xx_largepage_ecclayout; 561 lpc32xx_chip.ecc.size = 512; 562 lpc32xx_chip.ecc.bytes = 10; 563 lpc32xx_chip.ecc.strength = 4; 564 lpc32xx_chip.ecc.read_page = lpc32xx_read_page_hwecc; 565 lpc32xx_chip.ecc.read_page_raw = lpc32xx_read_page_raw; 566 lpc32xx_chip.ecc.write_page = lpc32xx_write_page_hwecc; 567 lpc32xx_chip.ecc.write_page_raw = lpc32xx_write_page_raw; 568 lpc32xx_chip.ecc.read_oob = lpc32xx_read_oob; 569 lpc32xx_chip.ecc.write_oob = lpc32xx_write_oob; 570 lpc32xx_chip.waitfunc = lpc32xx_waitfunc; 571 572 lpc32xx_chip.read_byte = lpc32xx_read_byte; /* FIXME: NEEDED? */ 573 574 /* BBT options: read from last two pages */ 575 lpc32xx_chip.bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_LASTBLOCK 576 | NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE 577 | NAND_BBT_WRITE; 578 579 /* Initialize NAND interface */ 580 lpc32xx_nand_init(); 581 582 /* identify chip */ 583 ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL); 584 if (ret) { 585 pr_err("nand_scan_ident returned %i", ret); 586 return; 587 } 588 589 /* finish scanning the chip */ 590 ret = nand_scan_tail(mtd); 591 if (ret) { 592 pr_err("nand_scan_tail returned %i", ret); 593 return; 594 } 595 596 /* chip is good, register it */ 597 ret = nand_register(0, mtd); 598 if (ret) 599 pr_err("nand_register returned %i", ret); 600 } 601 602 #else /* defined(CONFIG_SPL_BUILD) */ 603 604 void nand_init(void) 605 { 606 /* enable NAND controller */ 607 lpc32xx_mlc_nand_init(); 608 /* initialize NAND controller */ 609 lpc32xx_nand_init(); 610 } 611 612 void nand_deselect(void) 613 { 614 /* nothing to do, but SPL requires this function */ 615 } 616 617 static int read_single_page(uint8_t *dest, int page, 618 struct lpc32xx_oob *oob) 619 { 620 int status, i, timeout, err, max_bitflips = 0; 621 622 /* enter read mode */ 623 writel(NAND_CMD_READ0, &lpc32xx_nand_mlc_registers->cmd); 624 /* send column (lsb then MSB) and page (lsb to MSB) */ 625 writel(0, &lpc32xx_nand_mlc_registers->addr); 626 writel(0, &lpc32xx_nand_mlc_registers->addr); 627 writel(page & 0xff, &lpc32xx_nand_mlc_registers->addr); 628 writel((page>>8) & 0xff, &lpc32xx_nand_mlc_registers->addr); 629 writel((page>>16) & 0xff, &lpc32xx_nand_mlc_registers->addr); 630 /* start reading */ 631 writel(NAND_CMD_READSTART, &lpc32xx_nand_mlc_registers->cmd); 632 633 /* large page auto decode read */ 634 for (i = 0; i < 4; i++) { 635 /* start auto decode (reads 528 NAND bytes) */ 636 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg); 637 /* wait for controller to return to ready state */ 638 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) { 639 status = readl(&lpc32xx_nand_mlc_registers->isr); 640 if (status & ISR_CONTROLLER_READY) 641 break; 642 udelay(1); 643 } 644 /* if controller stalled, return error */ 645 if (!(status & ISR_CONTROLLER_READY)) 646 return -1; 647 /* if decoder failure, return error */ 648 if (status & ISR_DECODER_FAILURE) 649 return -1; 650 /* keep count of maximum bitflips performed */ 651 if (status & ISR_DECODER_ERROR) { 652 err = ISR_DECODER_ERRORS(status); 653 if (err > max_bitflips) 654 max_bitflips = err; 655 } 656 /* copy first 512 bytes into buffer */ 657 memcpy(dest+i*512, lpc32xx_nand_mlc_registers->buff, 512); 658 /* copy next 6 bytes bytes into OOB buffer */ 659 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6); 660 } 661 return max_bitflips; 662 } 663 664 /* 665 * Load U-Boot signed image. 666 * This loads an image from NAND, skipping bad blocks. 667 * A block is declared bad if at least one of its readable pages has 668 * a bad block marker in its OOB at position 0. 669 * If all pages ion a block are unreadable, the block is considered 670 * bad (i.e., assumed not to be part of the image) and skipped. 671 * 672 * IMPORTANT NOTE: 673 * 674 * If the first block of the image is fully unreadable, it will be 675 * ignored and skipped as if it had been marked bad. If it was not 676 * actually marked bad at the time of writing the image, the resulting 677 * image loaded will lack a header and magic number. It could thus be 678 * considered as a raw, headerless, image and SPL might erroneously 679 * jump into it. 680 * 681 * In order to avoid this risk, LPC32XX-based boards which use this 682 * driver MUST define CONFIG_SPL_PANIC_ON_RAW_IMAGE. 683 */ 684 685 #define BYTES_PER_PAGE 2048 686 #define PAGES_PER_BLOCK 64 687 #define BYTES_PER_BLOCK (BYTES_PER_PAGE * PAGES_PER_BLOCK) 688 #define PAGES_PER_CHIP_MAX 524288 689 690 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) 691 { 692 int bytes_left = size; 693 int pages_left = DIV_ROUND_UP(size, BYTES_PER_PAGE); 694 int blocks_left = DIV_ROUND_UP(size, BYTES_PER_BLOCK); 695 int block = 0; 696 int page = offs / BYTES_PER_PAGE; 697 /* perform reads block by block */ 698 while (blocks_left) { 699 /* compute first page number to read */ 700 void *block_page_dst = dst; 701 /* read at most one block, possibly less */ 702 int block_bytes_left = bytes_left; 703 if (block_bytes_left > BYTES_PER_BLOCK) 704 block_bytes_left = BYTES_PER_BLOCK; 705 /* keep track of good, failed, and "bad" pages */ 706 int block_pages_good = 0; 707 int block_pages_bad = 0; 708 int block_pages_err = 0; 709 /* we shall read a full block of pages, maybe less */ 710 int block_pages_left = pages_left; 711 if (block_pages_left > PAGES_PER_BLOCK) 712 block_pages_left = PAGES_PER_BLOCK; 713 int block_pages = block_pages_left; 714 int block_page = page; 715 /* while pages are left and the block is not known as bad */ 716 while ((block_pages > 0) && (block_pages_bad == 0)) { 717 /* we will read OOB, too, for bad block markers */ 718 struct lpc32xx_oob oob; 719 /* read page */ 720 int res = read_single_page(block_page_dst, block_page, 721 &oob); 722 /* count readable pages */ 723 if (res >= 0) { 724 /* this page is good */ 725 block_pages_good++; 726 /* this page is bad */ 727 if ((oob.free[0].free_oob_bytes[0] != 0xff) 728 | (oob.free[0].free_oob_bytes[1] != 0xff)) 729 block_pages_bad++; 730 } else 731 /* count errors */ 732 block_pages_err++; 733 /* we're done with this page */ 734 block_page++; 735 block_page_dst += BYTES_PER_PAGE; 736 if (block_pages) 737 block_pages--; 738 } 739 /* a fully unreadable block is considered bad */ 740 if (block_pages_good == 0) 741 block_pages_bad = block_pages_err; 742 /* errors are fatal only in good blocks */ 743 if ((block_pages_err > 0) && (block_pages_bad == 0)) 744 return -1; 745 /* we keep reads only of good blocks */ 746 if (block_pages_bad == 0) { 747 dst += block_bytes_left; 748 bytes_left -= block_bytes_left; 749 pages_left -= block_pages_left; 750 blocks_left--; 751 } 752 /* good or bad, we're done with this block */ 753 block++; 754 page += PAGES_PER_BLOCK; 755 } 756 757 /* report success */ 758 return 0; 759 } 760 761 #endif /* CONFIG_SPL_BUILD */ 762