1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * FSL UPM NAND driver 4 * 5 * Copyright (C) 2007 MontaVista Software, Inc. 6 * Anton Vorontsov <avorontsov@ru.mvista.com> 7 */ 8 9 #include <config.h> 10 #include <common.h> 11 #include <asm/io.h> 12 #include <linux/errno.h> 13 #include <linux/mtd/mtd.h> 14 #include <linux/mtd/fsl_upm.h> 15 #include <nand.h> 16 17 static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) 18 { 19 clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset); 20 (void)in_be32(upm->mxmr); 21 } 22 23 static void fsl_upm_end_pattern(struct fsl_upm *upm) 24 { 25 clrbits_be32(upm->mxmr, MxMR_OP_RUNP); 26 27 while (in_be32(upm->mxmr) & MxMR_OP_RUNP) 28 eieio(); 29 } 30 31 static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, 32 void __iomem *io_addr, u32 mar) 33 { 34 out_be32(upm->mar, mar); 35 (void)in_be32(upm->mar); 36 switch (width) { 37 case 8: 38 out_8(io_addr, 0x0); 39 break; 40 case 16: 41 out_be16(io_addr, 0x0); 42 break; 43 case 32: 44 out_be32(io_addr, 0x0); 45 break; 46 } 47 } 48 49 static void fun_wait(struct fsl_upm_nand *fun) 50 { 51 if (fun->dev_ready) { 52 while (!fun->dev_ready(fun->chip_nr)) 53 debug("unexpected busy state\n"); 54 } else { 55 /* 56 * If the R/B pin is not connected, 57 * a short delay is necessary. 58 */ 59 udelay(1); 60 } 61 } 62 63 #if CONFIG_SYS_NAND_MAX_CHIPS > 1 64 static void fun_select_chip(struct mtd_info *mtd, int chip_nr) 65 { 66 struct nand_chip *chip = mtd_to_nand(mtd); 67 struct fsl_upm_nand *fun = nand_get_controller_data(chip); 68 69 if (chip_nr >= 0) { 70 fun->chip_nr = chip_nr; 71 chip->IO_ADDR_R = chip->IO_ADDR_W = 72 fun->upm.io_addr + fun->chip_offset * chip_nr; 73 } else if (chip_nr == -1) { 74 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); 75 } 76 } 77 #endif 78 79 static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) 80 { 81 struct nand_chip *chip = mtd_to_nand(mtd); 82 struct fsl_upm_nand *fun = nand_get_controller_data(chip); 83 void __iomem *io_addr; 84 u32 mar; 85 86 if (!(ctrl & fun->last_ctrl)) { 87 fsl_upm_end_pattern(&fun->upm); 88 89 if (cmd == NAND_CMD_NONE) 90 return; 91 92 fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE); 93 } 94 95 if (ctrl & NAND_CTRL_CHANGE) { 96 if (ctrl & NAND_ALE) 97 fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); 98 else if (ctrl & NAND_CLE) 99 fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); 100 } 101 102 mar = cmd << (32 - fun->width); 103 io_addr = fun->upm.io_addr; 104 #if CONFIG_SYS_NAND_MAX_CHIPS > 1 105 if (fun->chip_nr > 0) { 106 io_addr += fun->chip_offset * fun->chip_nr; 107 if (fun->upm_mar_chip_offset) 108 mar |= fun->upm_mar_chip_offset * fun->chip_nr; 109 } 110 #endif 111 fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar); 112 113 /* 114 * Some boards/chips needs this. At least the MPC8360E-RDK 115 * needs it. Probably weird chip, because I don't see any 116 * need for this on MPC8555E + Samsung K9F1G08U0A. Usually 117 * here are 0-2 unexpected busy states per block read. 118 */ 119 if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN) 120 fun_wait(fun); 121 } 122 123 static u8 upm_nand_read_byte(struct mtd_info *mtd) 124 { 125 struct nand_chip *chip = mtd_to_nand(mtd); 126 127 return in_8(chip->IO_ADDR_R); 128 } 129 130 static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) 131 { 132 int i; 133 struct nand_chip *chip = mtd_to_nand(mtd); 134 struct fsl_upm_nand *fun = nand_get_controller_data(chip); 135 136 for (i = 0; i < len; i++) { 137 out_8(chip->IO_ADDR_W, buf[i]); 138 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE) 139 fun_wait(fun); 140 } 141 142 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER) 143 fun_wait(fun); 144 } 145 146 static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) 147 { 148 int i; 149 struct nand_chip *chip = mtd_to_nand(mtd); 150 151 for (i = 0; i < len; i++) 152 buf[i] = in_8(chip->IO_ADDR_R); 153 } 154 155 static int nand_dev_ready(struct mtd_info *mtd) 156 { 157 struct nand_chip *chip = mtd_to_nand(mtd); 158 struct fsl_upm_nand *fun = nand_get_controller_data(chip); 159 160 return fun->dev_ready(fun->chip_nr); 161 } 162 163 int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) 164 { 165 if (fun->width != 8 && fun->width != 16 && fun->width != 32) 166 return -ENOSYS; 167 168 fun->last_ctrl = NAND_CLE; 169 170 nand_set_controller_data(chip, fun); 171 chip->chip_delay = fun->chip_delay; 172 chip->ecc.mode = NAND_ECC_SOFT; 173 chip->cmd_ctrl = fun_cmd_ctrl; 174 #if CONFIG_SYS_NAND_MAX_CHIPS > 1 175 chip->select_chip = fun_select_chip; 176 #endif 177 chip->read_byte = upm_nand_read_byte; 178 chip->read_buf = upm_nand_read_buf; 179 chip->write_buf = upm_nand_write_buf; 180 if (fun->dev_ready) 181 chip->dev_ready = nand_dev_ready; 182 183 return 0; 184 } 185