1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014 Panasonic Corporation 4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com> 5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers. 6 */ 7 8 #include <dm.h> 9 #include <nand.h> 10 #include <linux/bitfield.h> 11 #include <linux/dma-direction.h> 12 #include <linux/errno.h> 13 #include <linux/io.h> 14 #include <linux/mtd/mtd.h> 15 #include <linux/mtd/rawnand.h> 16 17 #include "denali.h" 18 19 static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size, 20 enum dma_data_direction dir) 21 { 22 unsigned long addr = (unsigned long)ptr; 23 24 size = ALIGN(size, ARCH_DMA_MINALIGN); 25 26 if (dir == DMA_FROM_DEVICE) 27 invalidate_dcache_range(addr, addr + size); 28 else 29 flush_dcache_range(addr, addr + size); 30 31 return addr; 32 } 33 34 static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size, 35 enum dma_data_direction dir) 36 { 37 size = ALIGN(size, ARCH_DMA_MINALIGN); 38 39 if (dir != DMA_TO_DEVICE) 40 invalidate_dcache_range(addr, addr + size); 41 } 42 43 static int dma_mapping_error(void *dev, dma_addr_t addr) 44 { 45 return 0; 46 } 47 48 #define DENALI_NAND_NAME "denali-nand" 49 50 /* for Indexed Addressing */ 51 #define DENALI_INDEXED_CTRL 0x00 52 #define DENALI_INDEXED_DATA 0x10 53 54 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */ 55 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */ 56 #define DENALI_MAP10 (2 << 26) /* high-level control plane */ 57 #define DENALI_MAP11 (3 << 26) /* direct controller access */ 58 59 /* MAP11 access cycle type */ 60 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */ 61 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */ 62 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */ 63 64 /* MAP10 commands */ 65 #define DENALI_ERASE 0x01 66 67 #define DENALI_BANK(denali) ((denali)->active_bank << 24) 68 69 #define DENALI_INVALID_BANK -1 70 #define DENALI_NR_BANKS 4 71 72 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) 73 { 74 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand); 75 } 76 77 /* 78 * Direct Addressing - the slave address forms the control information (command 79 * type, bank, block, and page address). The slave data is the actual data to 80 * be transferred. This mode requires 28 bits of address region allocated. 81 */ 82 static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr) 83 { 84 return ioread32(denali->host + addr); 85 } 86 87 static void denali_direct_write(struct denali_nand_info *denali, u32 addr, 88 u32 data) 89 { 90 iowrite32(data, denali->host + addr); 91 } 92 93 /* 94 * Indexed Addressing - address translation module intervenes in passing the 95 * control information. This mode reduces the required address range. The 96 * control information and transferred data are latched by the registers in 97 * the translation module. 98 */ 99 static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr) 100 { 101 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); 102 return ioread32(denali->host + DENALI_INDEXED_DATA); 103 } 104 105 static void denali_indexed_write(struct denali_nand_info *denali, u32 addr, 106 u32 data) 107 { 108 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL); 109 iowrite32(data, denali->host + DENALI_INDEXED_DATA); 110 } 111 112 /* 113 * Use the configuration feature register to determine the maximum number of 114 * banks that the hardware supports. 115 */ 116 static void denali_detect_max_banks(struct denali_nand_info *denali) 117 { 118 uint32_t features = ioread32(denali->reg + FEATURES); 119 120 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features); 121 122 /* the encoding changed from rev 5.0 to 5.1 */ 123 if (denali->revision < 0x0501) 124 denali->max_banks <<= 1; 125 } 126 127 static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali) 128 { 129 int i; 130 131 for (i = 0; i < DENALI_NR_BANKS; i++) 132 iowrite32(U32_MAX, denali->reg + INTR_EN(i)); 133 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE); 134 } 135 136 static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali) 137 { 138 int i; 139 140 for (i = 0; i < DENALI_NR_BANKS; i++) 141 iowrite32(0, denali->reg + INTR_EN(i)); 142 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE); 143 } 144 145 static void denali_clear_irq(struct denali_nand_info *denali, 146 int bank, uint32_t irq_status) 147 { 148 /* write one to clear bits */ 149 iowrite32(irq_status, denali->reg + INTR_STATUS(bank)); 150 } 151 152 static void denali_clear_irq_all(struct denali_nand_info *denali) 153 { 154 int i; 155 156 for (i = 0; i < DENALI_NR_BANKS; i++) 157 denali_clear_irq(denali, i, U32_MAX); 158 } 159 160 static void __denali_check_irq(struct denali_nand_info *denali) 161 { 162 uint32_t irq_status; 163 int i; 164 165 for (i = 0; i < DENALI_NR_BANKS; i++) { 166 irq_status = ioread32(denali->reg + INTR_STATUS(i)); 167 denali_clear_irq(denali, i, irq_status); 168 169 if (i != denali->active_bank) 170 continue; 171 172 denali->irq_status |= irq_status; 173 } 174 } 175 176 static void denali_reset_irq(struct denali_nand_info *denali) 177 { 178 denali->irq_status = 0; 179 denali->irq_mask = 0; 180 } 181 182 static uint32_t denali_wait_for_irq(struct denali_nand_info *denali, 183 uint32_t irq_mask) 184 { 185 unsigned long time_left = 1000000; 186 187 while (time_left) { 188 __denali_check_irq(denali); 189 190 if (irq_mask & denali->irq_status) 191 return denali->irq_status; 192 udelay(1); 193 time_left--; 194 } 195 196 if (!time_left) { 197 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n", 198 irq_mask); 199 return 0; 200 } 201 202 return denali->irq_status; 203 } 204 205 static uint32_t denali_check_irq(struct denali_nand_info *denali) 206 { 207 __denali_check_irq(denali); 208 209 return denali->irq_status; 210 } 211 212 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 213 { 214 struct denali_nand_info *denali = mtd_to_denali(mtd); 215 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 216 int i; 217 218 for (i = 0; i < len; i++) 219 buf[i] = denali->host_read(denali, addr); 220 } 221 222 static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 223 { 224 struct denali_nand_info *denali = mtd_to_denali(mtd); 225 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 226 int i; 227 228 for (i = 0; i < len; i++) 229 denali->host_write(denali, addr, buf[i]); 230 } 231 232 static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) 233 { 234 struct denali_nand_info *denali = mtd_to_denali(mtd); 235 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 236 uint16_t *buf16 = (uint16_t *)buf; 237 int i; 238 239 for (i = 0; i < len / 2; i++) 240 buf16[i] = denali->host_read(denali, addr); 241 } 242 243 static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf, 244 int len) 245 { 246 struct denali_nand_info *denali = mtd_to_denali(mtd); 247 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali); 248 const uint16_t *buf16 = (const uint16_t *)buf; 249 int i; 250 251 for (i = 0; i < len / 2; i++) 252 denali->host_write(denali, addr, buf16[i]); 253 } 254 255 static uint8_t denali_read_byte(struct mtd_info *mtd) 256 { 257 uint8_t byte; 258 259 denali_read_buf(mtd, &byte, 1); 260 261 return byte; 262 } 263 264 static void denali_write_byte(struct mtd_info *mtd, uint8_t byte) 265 { 266 denali_write_buf(mtd, &byte, 1); 267 } 268 269 static uint16_t denali_read_word(struct mtd_info *mtd) 270 { 271 uint16_t word; 272 273 denali_read_buf16(mtd, (uint8_t *)&word, 2); 274 275 return word; 276 } 277 278 static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) 279 { 280 struct denali_nand_info *denali = mtd_to_denali(mtd); 281 uint32_t type; 282 283 if (ctrl & NAND_CLE) 284 type = DENALI_MAP11_CMD; 285 else if (ctrl & NAND_ALE) 286 type = DENALI_MAP11_ADDR; 287 else 288 return; 289 290 /* 291 * Some commands are followed by chip->dev_ready or chip->waitfunc. 292 * irq_status must be cleared here to catch the R/B# interrupt later. 293 */ 294 if (ctrl & NAND_CTRL_CHANGE) 295 denali_reset_irq(denali); 296 297 denali->host_write(denali, DENALI_BANK(denali) | type, dat); 298 } 299 300 static int denali_dev_ready(struct mtd_info *mtd) 301 { 302 struct denali_nand_info *denali = mtd_to_denali(mtd); 303 304 return !!(denali_check_irq(denali) & INTR__INT_ACT); 305 } 306 307 static int denali_check_erased_page(struct mtd_info *mtd, 308 struct nand_chip *chip, uint8_t *buf, 309 unsigned long uncor_ecc_flags, 310 unsigned int max_bitflips) 311 { 312 uint8_t *ecc_code = chip->buffers->ecccode; 313 int ecc_steps = chip->ecc.steps; 314 int ecc_size = chip->ecc.size; 315 int ecc_bytes = chip->ecc.bytes; 316 int i, ret, stat; 317 318 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0, 319 chip->ecc.total); 320 if (ret) 321 return ret; 322 323 for (i = 0; i < ecc_steps; i++) { 324 if (!(uncor_ecc_flags & BIT(i))) 325 continue; 326 327 stat = nand_check_erased_ecc_chunk(buf, ecc_size, 328 ecc_code, ecc_bytes, 329 NULL, 0, 330 chip->ecc.strength); 331 if (stat < 0) { 332 mtd->ecc_stats.failed++; 333 } else { 334 mtd->ecc_stats.corrected += stat; 335 max_bitflips = max_t(unsigned int, max_bitflips, stat); 336 } 337 338 buf += ecc_size; 339 ecc_code += ecc_bytes; 340 } 341 342 return max_bitflips; 343 } 344 345 static int denali_hw_ecc_fixup(struct mtd_info *mtd, 346 struct denali_nand_info *denali, 347 unsigned long *uncor_ecc_flags) 348 { 349 struct nand_chip *chip = mtd_to_nand(mtd); 350 int bank = denali->active_bank; 351 uint32_t ecc_cor; 352 unsigned int max_bitflips; 353 354 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank)); 355 ecc_cor >>= ECC_COR_INFO__SHIFT(bank); 356 357 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) { 358 /* 359 * This flag is set when uncorrectable error occurs at least in 360 * one ECC sector. We can not know "how many sectors", or 361 * "which sector(s)". We need erase-page check for all sectors. 362 */ 363 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0); 364 return 0; 365 } 366 367 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor); 368 369 /* 370 * The register holds the maximum of per-sector corrected bitflips. 371 * This is suitable for the return value of the ->read_page() callback. 372 * Unfortunately, we can not know the total number of corrected bits in 373 * the page. Increase the stats by max_bitflips. (compromised solution) 374 */ 375 mtd->ecc_stats.corrected += max_bitflips; 376 377 return max_bitflips; 378 } 379 380 static int denali_sw_ecc_fixup(struct mtd_info *mtd, 381 struct denali_nand_info *denali, 382 unsigned long *uncor_ecc_flags, uint8_t *buf) 383 { 384 unsigned int ecc_size = denali->nand.ecc.size; 385 unsigned int bitflips = 0; 386 unsigned int max_bitflips = 0; 387 uint32_t err_addr, err_cor_info; 388 unsigned int err_byte, err_sector, err_device; 389 uint8_t err_cor_value; 390 unsigned int prev_sector = 0; 391 uint32_t irq_status; 392 393 denali_reset_irq(denali); 394 395 do { 396 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS); 397 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr); 398 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr); 399 400 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO); 401 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE, 402 err_cor_info); 403 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE, 404 err_cor_info); 405 406 /* reset the bitflip counter when crossing ECC sector */ 407 if (err_sector != prev_sector) 408 bitflips = 0; 409 410 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) { 411 /* 412 * Check later if this is a real ECC error, or 413 * an erased sector. 414 */ 415 *uncor_ecc_flags |= BIT(err_sector); 416 } else if (err_byte < ecc_size) { 417 /* 418 * If err_byte is larger than ecc_size, means error 419 * happened in OOB, so we ignore it. It's no need for 420 * us to correct it err_device is represented the NAND 421 * error bits are happened in if there are more than 422 * one NAND connected. 423 */ 424 int offset; 425 unsigned int flips_in_byte; 426 427 offset = (err_sector * ecc_size + err_byte) * 428 denali->devs_per_cs + err_device; 429 430 /* correct the ECC error */ 431 flips_in_byte = hweight8(buf[offset] ^ err_cor_value); 432 buf[offset] ^= err_cor_value; 433 mtd->ecc_stats.corrected += flips_in_byte; 434 bitflips += flips_in_byte; 435 436 max_bitflips = max(max_bitflips, bitflips); 437 } 438 439 prev_sector = err_sector; 440 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR)); 441 442 /* 443 * Once handle all ECC errors, controller will trigger an 444 * ECC_TRANSACTION_DONE interrupt. 445 */ 446 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE); 447 if (!(irq_status & INTR__ECC_TRANSACTION_DONE)) 448 return -EIO; 449 450 return max_bitflips; 451 } 452 453 static void denali_setup_dma64(struct denali_nand_info *denali, 454 dma_addr_t dma_addr, int page, int write) 455 { 456 uint32_t mode; 457 const int page_count = 1; 458 459 mode = DENALI_MAP10 | DENALI_BANK(denali) | page; 460 461 /* DMA is a three step process */ 462 463 /* 464 * 1. setup transfer type, interrupt when complete, 465 * burst len = 64 bytes, the number of pages 466 */ 467 denali->host_write(denali, mode, 468 0x01002000 | (64 << 16) | (write << 8) | page_count); 469 470 /* 2. set memory low address */ 471 denali->host_write(denali, mode, lower_32_bits(dma_addr)); 472 473 /* 3. set memory high address */ 474 denali->host_write(denali, mode, upper_32_bits(dma_addr)); 475 } 476 477 static void denali_setup_dma32(struct denali_nand_info *denali, 478 dma_addr_t dma_addr, int page, int write) 479 { 480 uint32_t mode; 481 const int page_count = 1; 482 483 mode = DENALI_MAP10 | DENALI_BANK(denali); 484 485 /* DMA is a four step process */ 486 487 /* 1. setup transfer type and # of pages */ 488 denali->host_write(denali, mode | page, 489 0x2000 | (write << 8) | page_count); 490 491 /* 2. set memory high address bits 23:8 */ 492 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200); 493 494 /* 3. set memory low address bits 23:8 */ 495 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300); 496 497 /* 4. interrupt when complete, burst len = 64 bytes */ 498 denali->host_write(denali, mode | 0x14000, 0x2400); 499 } 500 501 static int denali_pio_read(struct denali_nand_info *denali, void *buf, 502 size_t size, int page, int raw) 503 { 504 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; 505 uint32_t *buf32 = (uint32_t *)buf; 506 uint32_t irq_status, ecc_err_mask; 507 int i; 508 509 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) 510 ecc_err_mask = INTR__ECC_UNCOR_ERR; 511 else 512 ecc_err_mask = INTR__ECC_ERR; 513 514 denali_reset_irq(denali); 515 516 for (i = 0; i < size / 4; i++) 517 *buf32++ = denali->host_read(denali, addr); 518 519 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC); 520 if (!(irq_status & INTR__PAGE_XFER_INC)) 521 return -EIO; 522 523 if (irq_status & INTR__ERASED_PAGE) 524 memset(buf, 0xff, size); 525 526 return irq_status & ecc_err_mask ? -EBADMSG : 0; 527 } 528 529 static int denali_pio_write(struct denali_nand_info *denali, 530 const void *buf, size_t size, int page, int raw) 531 { 532 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page; 533 const uint32_t *buf32 = (uint32_t *)buf; 534 uint32_t irq_status; 535 int i; 536 537 denali_reset_irq(denali); 538 539 for (i = 0; i < size / 4; i++) 540 denali->host_write(denali, addr, *buf32++); 541 542 irq_status = denali_wait_for_irq(denali, 543 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL); 544 if (!(irq_status & INTR__PROGRAM_COMP)) 545 return -EIO; 546 547 return 0; 548 } 549 550 static int denali_pio_xfer(struct denali_nand_info *denali, void *buf, 551 size_t size, int page, int raw, int write) 552 { 553 if (write) 554 return denali_pio_write(denali, buf, size, page, raw); 555 else 556 return denali_pio_read(denali, buf, size, page, raw); 557 } 558 559 static int denali_dma_xfer(struct denali_nand_info *denali, void *buf, 560 size_t size, int page, int raw, int write) 561 { 562 dma_addr_t dma_addr; 563 uint32_t irq_mask, irq_status, ecc_err_mask; 564 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 565 int ret = 0; 566 567 dma_addr = dma_map_single(denali->dev, buf, size, dir); 568 if (dma_mapping_error(denali->dev, dma_addr)) { 569 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n"); 570 return denali_pio_xfer(denali, buf, size, page, raw, write); 571 } 572 573 if (write) { 574 /* 575 * INTR__PROGRAM_COMP is never asserted for the DMA transfer. 576 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted 577 * when the page program is completed. 578 */ 579 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL; 580 ecc_err_mask = 0; 581 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) { 582 irq_mask = INTR__DMA_CMD_COMP; 583 ecc_err_mask = INTR__ECC_UNCOR_ERR; 584 } else { 585 irq_mask = INTR__DMA_CMD_COMP; 586 ecc_err_mask = INTR__ECC_ERR; 587 } 588 589 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE); 590 /* 591 * The ->setup_dma() hook kicks DMA by using the data/command 592 * interface, which belongs to a different AXI port from the 593 * register interface. Read back the register to avoid a race. 594 */ 595 ioread32(denali->reg + DMA_ENABLE); 596 597 denali_reset_irq(denali); 598 denali->setup_dma(denali, dma_addr, page, write); 599 600 irq_status = denali_wait_for_irq(denali, irq_mask); 601 if (!(irq_status & INTR__DMA_CMD_COMP)) 602 ret = -EIO; 603 else if (irq_status & ecc_err_mask) 604 ret = -EBADMSG; 605 606 iowrite32(0, denali->reg + DMA_ENABLE); 607 608 dma_unmap_single(denali->dev, dma_addr, size, dir); 609 610 if (irq_status & INTR__ERASED_PAGE) 611 memset(buf, 0xff, size); 612 613 return ret; 614 } 615 616 static int denali_data_xfer(struct denali_nand_info *denali, void *buf, 617 size_t size, int page, int raw, int write) 618 { 619 iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE); 620 iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0, 621 denali->reg + TRANSFER_SPARE_REG); 622 623 if (denali->dma_avail) 624 return denali_dma_xfer(denali, buf, size, page, raw, write); 625 else 626 return denali_pio_xfer(denali, buf, size, page, raw, write); 627 } 628 629 static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip, 630 int page, int write) 631 { 632 struct denali_nand_info *denali = mtd_to_denali(mtd); 633 unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0; 634 unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT; 635 int writesize = mtd->writesize; 636 int oobsize = mtd->oobsize; 637 uint8_t *bufpoi = chip->oob_poi; 638 int ecc_steps = chip->ecc.steps; 639 int ecc_size = chip->ecc.size; 640 int ecc_bytes = chip->ecc.bytes; 641 int oob_skip = denali->oob_skip_bytes; 642 size_t size = writesize + oobsize; 643 int i, pos, len; 644 645 /* BBM at the beginning of the OOB area */ 646 chip->cmdfunc(mtd, start_cmd, writesize, page); 647 if (write) 648 chip->write_buf(mtd, bufpoi, oob_skip); 649 else 650 chip->read_buf(mtd, bufpoi, oob_skip); 651 bufpoi += oob_skip; 652 653 /* OOB ECC */ 654 for (i = 0; i < ecc_steps; i++) { 655 pos = ecc_size + i * (ecc_size + ecc_bytes); 656 len = ecc_bytes; 657 658 if (pos >= writesize) 659 pos += oob_skip; 660 else if (pos + len > writesize) 661 len = writesize - pos; 662 663 chip->cmdfunc(mtd, rnd_cmd, pos, -1); 664 if (write) 665 chip->write_buf(mtd, bufpoi, len); 666 else 667 chip->read_buf(mtd, bufpoi, len); 668 bufpoi += len; 669 if (len < ecc_bytes) { 670 len = ecc_bytes - len; 671 chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1); 672 if (write) 673 chip->write_buf(mtd, bufpoi, len); 674 else 675 chip->read_buf(mtd, bufpoi, len); 676 bufpoi += len; 677 } 678 } 679 680 /* OOB free */ 681 len = oobsize - (bufpoi - chip->oob_poi); 682 chip->cmdfunc(mtd, rnd_cmd, size - len, -1); 683 if (write) 684 chip->write_buf(mtd, bufpoi, len); 685 else 686 chip->read_buf(mtd, bufpoi, len); 687 } 688 689 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 690 uint8_t *buf, int oob_required, int page) 691 { 692 struct denali_nand_info *denali = mtd_to_denali(mtd); 693 int writesize = mtd->writesize; 694 int oobsize = mtd->oobsize; 695 int ecc_steps = chip->ecc.steps; 696 int ecc_size = chip->ecc.size; 697 int ecc_bytes = chip->ecc.bytes; 698 void *tmp_buf = denali->buf; 699 int oob_skip = denali->oob_skip_bytes; 700 size_t size = writesize + oobsize; 701 int ret, i, pos, len; 702 703 ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0); 704 if (ret) 705 return ret; 706 707 /* Arrange the buffer for syndrome payload/ecc layout */ 708 if (buf) { 709 for (i = 0; i < ecc_steps; i++) { 710 pos = i * (ecc_size + ecc_bytes); 711 len = ecc_size; 712 713 if (pos >= writesize) 714 pos += oob_skip; 715 else if (pos + len > writesize) 716 len = writesize - pos; 717 718 memcpy(buf, tmp_buf + pos, len); 719 buf += len; 720 if (len < ecc_size) { 721 len = ecc_size - len; 722 memcpy(buf, tmp_buf + writesize + oob_skip, 723 len); 724 buf += len; 725 } 726 } 727 } 728 729 if (oob_required) { 730 uint8_t *oob = chip->oob_poi; 731 732 /* BBM at the beginning of the OOB area */ 733 memcpy(oob, tmp_buf + writesize, oob_skip); 734 oob += oob_skip; 735 736 /* OOB ECC */ 737 for (i = 0; i < ecc_steps; i++) { 738 pos = ecc_size + i * (ecc_size + ecc_bytes); 739 len = ecc_bytes; 740 741 if (pos >= writesize) 742 pos += oob_skip; 743 else if (pos + len > writesize) 744 len = writesize - pos; 745 746 memcpy(oob, tmp_buf + pos, len); 747 oob += len; 748 if (len < ecc_bytes) { 749 len = ecc_bytes - len; 750 memcpy(oob, tmp_buf + writesize + oob_skip, 751 len); 752 oob += len; 753 } 754 } 755 756 /* OOB free */ 757 len = oobsize - (oob - chip->oob_poi); 758 memcpy(oob, tmp_buf + size - len, len); 759 } 760 761 return 0; 762 } 763 764 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 765 int page) 766 { 767 denali_oob_xfer(mtd, chip, page, 0); 768 769 return 0; 770 } 771 772 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 773 int page) 774 { 775 struct denali_nand_info *denali = mtd_to_denali(mtd); 776 int status; 777 778 denali_reset_irq(denali); 779 780 denali_oob_xfer(mtd, chip, page, 1); 781 782 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 783 status = chip->waitfunc(mtd, chip); 784 785 return status & NAND_STATUS_FAIL ? -EIO : 0; 786 } 787 788 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip, 789 uint8_t *buf, int oob_required, int page) 790 { 791 struct denali_nand_info *denali = mtd_to_denali(mtd); 792 unsigned long uncor_ecc_flags = 0; 793 int stat = 0; 794 int ret; 795 796 ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0); 797 if (ret && ret != -EBADMSG) 798 return ret; 799 800 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) 801 stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags); 802 else if (ret == -EBADMSG) 803 stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf); 804 805 if (stat < 0) 806 return stat; 807 808 if (uncor_ecc_flags) { 809 ret = denali_read_oob(mtd, chip, page); 810 if (ret) 811 return ret; 812 813 stat = denali_check_erased_page(mtd, chip, buf, 814 uncor_ecc_flags, stat); 815 } 816 817 return stat; 818 } 819 820 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 821 const uint8_t *buf, int oob_required, int page) 822 { 823 struct denali_nand_info *denali = mtd_to_denali(mtd); 824 int writesize = mtd->writesize; 825 int oobsize = mtd->oobsize; 826 int ecc_steps = chip->ecc.steps; 827 int ecc_size = chip->ecc.size; 828 int ecc_bytes = chip->ecc.bytes; 829 void *tmp_buf = denali->buf; 830 int oob_skip = denali->oob_skip_bytes; 831 size_t size = writesize + oobsize; 832 int i, pos, len; 833 834 /* 835 * Fill the buffer with 0xff first except the full page transfer. 836 * This simplifies the logic. 837 */ 838 if (!buf || !oob_required) 839 memset(tmp_buf, 0xff, size); 840 841 /* Arrange the buffer for syndrome payload/ecc layout */ 842 if (buf) { 843 for (i = 0; i < ecc_steps; i++) { 844 pos = i * (ecc_size + ecc_bytes); 845 len = ecc_size; 846 847 if (pos >= writesize) 848 pos += oob_skip; 849 else if (pos + len > writesize) 850 len = writesize - pos; 851 852 memcpy(tmp_buf + pos, buf, len); 853 buf += len; 854 if (len < ecc_size) { 855 len = ecc_size - len; 856 memcpy(tmp_buf + writesize + oob_skip, buf, 857 len); 858 buf += len; 859 } 860 } 861 } 862 863 if (oob_required) { 864 const uint8_t *oob = chip->oob_poi; 865 866 /* BBM at the beginning of the OOB area */ 867 memcpy(tmp_buf + writesize, oob, oob_skip); 868 oob += oob_skip; 869 870 /* OOB ECC */ 871 for (i = 0; i < ecc_steps; i++) { 872 pos = ecc_size + i * (ecc_size + ecc_bytes); 873 len = ecc_bytes; 874 875 if (pos >= writesize) 876 pos += oob_skip; 877 else if (pos + len > writesize) 878 len = writesize - pos; 879 880 memcpy(tmp_buf + pos, oob, len); 881 oob += len; 882 if (len < ecc_bytes) { 883 len = ecc_bytes - len; 884 memcpy(tmp_buf + writesize + oob_skip, oob, 885 len); 886 oob += len; 887 } 888 } 889 890 /* OOB free */ 891 len = oobsize - (oob - chip->oob_poi); 892 memcpy(tmp_buf + size - len, oob, len); 893 } 894 895 return denali_data_xfer(denali, tmp_buf, size, page, 1, 1); 896 } 897 898 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip, 899 const uint8_t *buf, int oob_required, int page) 900 { 901 struct denali_nand_info *denali = mtd_to_denali(mtd); 902 903 return denali_data_xfer(denali, (void *)buf, mtd->writesize, 904 page, 0, 1); 905 } 906 907 static void denali_select_chip(struct mtd_info *mtd, int chip) 908 { 909 struct denali_nand_info *denali = mtd_to_denali(mtd); 910 911 denali->active_bank = chip; 912 } 913 914 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip) 915 { 916 struct denali_nand_info *denali = mtd_to_denali(mtd); 917 uint32_t irq_status; 918 919 /* R/B# pin transitioned from low to high? */ 920 irq_status = denali_wait_for_irq(denali, INTR__INT_ACT); 921 922 return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL; 923 } 924 925 static int denali_erase(struct mtd_info *mtd, int page) 926 { 927 struct denali_nand_info *denali = mtd_to_denali(mtd); 928 uint32_t irq_status; 929 930 denali_reset_irq(denali); 931 932 denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page, 933 DENALI_ERASE); 934 935 /* wait for erase to complete or failure to occur */ 936 irq_status = denali_wait_for_irq(denali, 937 INTR__ERASE_COMP | INTR__ERASE_FAIL); 938 939 return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL; 940 } 941 942 static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, 943 const struct nand_data_interface *conf) 944 { 945 struct denali_nand_info *denali = mtd_to_denali(mtd); 946 const struct nand_sdr_timings *timings; 947 unsigned long t_x, mult_x; 948 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data; 949 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup; 950 int addr_2_data_mask; 951 uint32_t tmp; 952 953 timings = nand_get_sdr_timings(conf); 954 if (IS_ERR(timings)) 955 return PTR_ERR(timings); 956 957 /* clk_x period in picoseconds */ 958 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate); 959 if (!t_x) 960 return -EINVAL; 961 962 /* 963 * The bus interface clock, clk_x, is phase aligned with the core clock. 964 * The clk_x is an integral multiple N of the core clk. The value N is 965 * configured at IP delivery time, and its available value is 4, 5, 6. 966 */ 967 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate); 968 if (mult_x < 4 || mult_x > 6) 969 return -EINVAL; 970 971 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) 972 return 0; 973 974 /* tREA -> ACC_CLKS */ 975 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x); 976 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE); 977 978 tmp = ioread32(denali->reg + ACC_CLKS); 979 tmp &= ~ACC_CLKS__VALUE; 980 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks); 981 iowrite32(tmp, denali->reg + ACC_CLKS); 982 983 /* tRWH -> RE_2_WE */ 984 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x); 985 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE); 986 987 tmp = ioread32(denali->reg + RE_2_WE); 988 tmp &= ~RE_2_WE__VALUE; 989 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we); 990 iowrite32(tmp, denali->reg + RE_2_WE); 991 992 /* tRHZ -> RE_2_RE */ 993 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x); 994 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE); 995 996 tmp = ioread32(denali->reg + RE_2_RE); 997 tmp &= ~RE_2_RE__VALUE; 998 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re); 999 iowrite32(tmp, denali->reg + RE_2_RE); 1000 1001 /* 1002 * tCCS, tWHR -> WE_2_RE 1003 * 1004 * With WE_2_RE properly set, the Denali controller automatically takes 1005 * care of the delay; the driver need not set NAND_WAIT_TCCS. 1006 */ 1007 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x); 1008 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); 1009 1010 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); 1011 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE; 1012 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re); 1013 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE); 1014 1015 /* tADL -> ADDR_2_DATA */ 1016 1017 /* for older versions, ADDR_2_DATA is only 6 bit wide */ 1018 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; 1019 if (denali->revision < 0x0501) 1020 addr_2_data_mask >>= 1; 1021 1022 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x); 1023 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask); 1024 1025 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA); 1026 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA; 1027 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data); 1028 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA); 1029 1030 /* tREH, tWH -> RDWR_EN_HI_CNT */ 1031 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min), 1032 t_x); 1033 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE); 1034 1035 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT); 1036 tmp &= ~RDWR_EN_HI_CNT__VALUE; 1037 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi); 1038 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT); 1039 1040 /* tRP, tWP -> RDWR_EN_LO_CNT */ 1041 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x); 1042 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min), 1043 t_x); 1044 rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x); 1045 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi); 1046 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE); 1047 1048 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT); 1049 tmp &= ~RDWR_EN_LO_CNT__VALUE; 1050 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo); 1051 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT); 1052 1053 /* tCS, tCEA -> CS_SETUP_CNT */ 1054 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo, 1055 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks, 1056 0); 1057 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE); 1058 1059 tmp = ioread32(denali->reg + CS_SETUP_CNT); 1060 tmp &= ~CS_SETUP_CNT__VALUE; 1061 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup); 1062 iowrite32(tmp, denali->reg + CS_SETUP_CNT); 1063 1064 return 0; 1065 } 1066 1067 static void denali_reset_banks(struct denali_nand_info *denali) 1068 { 1069 u32 irq_status; 1070 int i; 1071 1072 for (i = 0; i < denali->max_banks; i++) { 1073 denali->active_bank = i; 1074 1075 denali_reset_irq(denali); 1076 1077 iowrite32(DEVICE_RESET__BANK(i), 1078 denali->reg + DEVICE_RESET); 1079 1080 irq_status = denali_wait_for_irq(denali, 1081 INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT); 1082 if (!(irq_status & INTR__INT_ACT)) 1083 break; 1084 } 1085 1086 dev_dbg(denali->dev, "%d chips connected\n", i); 1087 denali->max_banks = i; 1088 } 1089 1090 static void denali_hw_init(struct denali_nand_info *denali) 1091 { 1092 /* 1093 * The REVISION register may not be reliable. Platforms are allowed to 1094 * override it. 1095 */ 1096 if (!denali->revision) 1097 denali->revision = swab16(ioread32(denali->reg + REVISION)); 1098 1099 /* 1100 * tell driver how many bit controller will skip before writing 1101 * ECC code in OOB. This is normally used for bad block marker 1102 */ 1103 denali->oob_skip_bytes = CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES; 1104 iowrite32(denali->oob_skip_bytes, denali->reg + SPARE_AREA_SKIP_BYTES); 1105 denali_detect_max_banks(denali); 1106 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED); 1107 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE); 1108 1109 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER); 1110 } 1111 1112 int denali_calc_ecc_bytes(int step_size, int strength) 1113 { 1114 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */ 1115 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2; 1116 } 1117 EXPORT_SYMBOL(denali_calc_ecc_bytes); 1118 1119 static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip, 1120 struct denali_nand_info *denali) 1121 { 1122 int oobavail = mtd->oobsize - denali->oob_skip_bytes; 1123 int ret; 1124 1125 /* 1126 * If .size and .strength are already set (usually by DT), 1127 * check if they are supported by this controller. 1128 */ 1129 if (chip->ecc.size && chip->ecc.strength) 1130 return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail); 1131 1132 /* 1133 * We want .size and .strength closest to the chip's requirement 1134 * unless NAND_ECC_MAXIMIZE is requested. 1135 */ 1136 if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) { 1137 ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail); 1138 if (!ret) 1139 return 0; 1140 } 1141 1142 /* Max ECC strength is the last thing we can do */ 1143 return nand_maximize_ecc(chip, denali->ecc_caps, oobavail); 1144 } 1145 1146 static struct nand_ecclayout nand_oob; 1147 1148 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section, 1149 struct mtd_oob_region *oobregion) 1150 { 1151 struct denali_nand_info *denali = mtd_to_denali(mtd); 1152 struct nand_chip *chip = mtd_to_nand(mtd); 1153 1154 if (section) 1155 return -ERANGE; 1156 1157 oobregion->offset = denali->oob_skip_bytes; 1158 oobregion->length = chip->ecc.total; 1159 1160 return 0; 1161 } 1162 1163 static int denali_ooblayout_free(struct mtd_info *mtd, int section, 1164 struct mtd_oob_region *oobregion) 1165 { 1166 struct denali_nand_info *denali = mtd_to_denali(mtd); 1167 struct nand_chip *chip = mtd_to_nand(mtd); 1168 1169 if (section) 1170 return -ERANGE; 1171 1172 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes; 1173 oobregion->length = mtd->oobsize - oobregion->offset; 1174 1175 return 0; 1176 } 1177 1178 static const struct mtd_ooblayout_ops denali_ooblayout_ops = { 1179 .ecc = denali_ooblayout_ecc, 1180 .free = denali_ooblayout_free, 1181 }; 1182 1183 static int denali_multidev_fixup(struct denali_nand_info *denali) 1184 { 1185 struct nand_chip *chip = &denali->nand; 1186 struct mtd_info *mtd = nand_to_mtd(chip); 1187 1188 /* 1189 * Support for multi device: 1190 * When the IP configuration is x16 capable and two x8 chips are 1191 * connected in parallel, DEVICES_CONNECTED should be set to 2. 1192 * In this case, the core framework knows nothing about this fact, 1193 * so we should tell it the _logical_ pagesize and anything necessary. 1194 */ 1195 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED); 1196 1197 /* 1198 * On some SoCs, DEVICES_CONNECTED is not auto-detected. 1199 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case. 1200 */ 1201 if (denali->devs_per_cs == 0) { 1202 denali->devs_per_cs = 1; 1203 iowrite32(1, denali->reg + DEVICES_CONNECTED); 1204 } 1205 1206 if (denali->devs_per_cs == 1) 1207 return 0; 1208 1209 if (denali->devs_per_cs != 2) { 1210 dev_err(denali->dev, "unsupported number of devices %d\n", 1211 denali->devs_per_cs); 1212 return -EINVAL; 1213 } 1214 1215 /* 2 chips in parallel */ 1216 mtd->size <<= 1; 1217 mtd->erasesize <<= 1; 1218 mtd->writesize <<= 1; 1219 mtd->oobsize <<= 1; 1220 chip->chipsize <<= 1; 1221 chip->page_shift += 1; 1222 chip->phys_erase_shift += 1; 1223 chip->bbt_erase_shift += 1; 1224 chip->chip_shift += 1; 1225 chip->pagemask <<= 1; 1226 chip->ecc.size <<= 1; 1227 chip->ecc.bytes <<= 1; 1228 chip->ecc.strength <<= 1; 1229 denali->oob_skip_bytes <<= 1; 1230 1231 return 0; 1232 } 1233 1234 int denali_init(struct denali_nand_info *denali) 1235 { 1236 struct nand_chip *chip = &denali->nand; 1237 struct mtd_info *mtd = nand_to_mtd(chip); 1238 u32 features = ioread32(denali->reg + FEATURES); 1239 int ret; 1240 1241 denali_hw_init(denali); 1242 1243 denali_clear_irq_all(denali); 1244 1245 denali_reset_banks(denali); 1246 1247 denali->active_bank = DENALI_INVALID_BANK; 1248 1249 chip->flash_node = dev_of_offset(denali->dev); 1250 /* Fallback to the default name if DT did not give "label" property */ 1251 if (!mtd->name) 1252 mtd->name = "denali-nand"; 1253 1254 chip->select_chip = denali_select_chip; 1255 chip->read_byte = denali_read_byte; 1256 chip->write_byte = denali_write_byte; 1257 chip->read_word = denali_read_word; 1258 chip->cmd_ctrl = denali_cmd_ctrl; 1259 chip->dev_ready = denali_dev_ready; 1260 chip->waitfunc = denali_waitfunc; 1261 1262 if (features & FEATURES__INDEX_ADDR) { 1263 denali->host_read = denali_indexed_read; 1264 denali->host_write = denali_indexed_write; 1265 } else { 1266 denali->host_read = denali_direct_read; 1267 denali->host_write = denali_direct_write; 1268 } 1269 1270 /* clk rate info is needed for setup_data_interface */ 1271 if (denali->clk_x_rate) 1272 chip->setup_data_interface = denali_setup_data_interface; 1273 1274 ret = nand_scan_ident(mtd, denali->max_banks, NULL); 1275 if (ret) 1276 return ret; 1277 1278 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA) 1279 denali->dma_avail = 1; 1280 1281 if (denali->dma_avail) { 1282 chip->buf_align = ARCH_DMA_MINALIGN; 1283 if (denali->caps & DENALI_CAP_DMA_64BIT) 1284 denali->setup_dma = denali_setup_dma64; 1285 else 1286 denali->setup_dma = denali_setup_dma32; 1287 } else { 1288 chip->buf_align = 4; 1289 } 1290 1291 chip->options |= NAND_USE_BOUNCE_BUFFER; 1292 chip->bbt_options |= NAND_BBT_USE_FLASH; 1293 chip->bbt_options |= NAND_BBT_NO_OOB; 1294 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; 1295 1296 /* no subpage writes on denali */ 1297 chip->options |= NAND_NO_SUBPAGE_WRITE; 1298 1299 ret = denali_ecc_setup(mtd, chip, denali); 1300 if (ret) { 1301 dev_err(denali->dev, "Failed to setup ECC settings.\n"); 1302 return ret; 1303 } 1304 1305 dev_dbg(denali->dev, 1306 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n", 1307 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); 1308 1309 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) | 1310 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), 1311 denali->reg + ECC_CORRECTION); 1312 iowrite32(mtd->erasesize / mtd->writesize, 1313 denali->reg + PAGES_PER_BLOCK); 1314 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0, 1315 denali->reg + DEVICE_WIDTH); 1316 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG, 1317 denali->reg + TWO_ROW_ADDR_CYCLES); 1318 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE); 1319 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE); 1320 1321 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); 1322 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); 1323 /* chip->ecc.steps is set by nand_scan_tail(); not available here */ 1324 iowrite32(mtd->writesize / chip->ecc.size, 1325 denali->reg + CFG_NUM_DATA_BLOCKS); 1326 1327 mtd_set_ooblayout(mtd, &denali_ooblayout_ops); 1328 1329 nand_oob.eccbytes = denali->nand.ecc.bytes; 1330 denali->nand.ecc.layout = &nand_oob; 1331 1332 if (chip->options & NAND_BUSWIDTH_16) { 1333 chip->read_buf = denali_read_buf16; 1334 chip->write_buf = denali_write_buf16; 1335 } else { 1336 chip->read_buf = denali_read_buf; 1337 chip->write_buf = denali_write_buf; 1338 } 1339 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS; 1340 chip->ecc.read_page = denali_read_page; 1341 chip->ecc.read_page_raw = denali_read_page_raw; 1342 chip->ecc.write_page = denali_write_page; 1343 chip->ecc.write_page_raw = denali_write_page_raw; 1344 chip->ecc.read_oob = denali_read_oob; 1345 chip->ecc.write_oob = denali_write_oob; 1346 chip->erase = denali_erase; 1347 1348 ret = denali_multidev_fixup(denali); 1349 if (ret) 1350 return ret; 1351 1352 /* 1353 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not 1354 * use devm_kmalloc() because the memory allocated by devm_ does not 1355 * guarantee DMA-safe alignment. 1356 */ 1357 denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL); 1358 if (!denali->buf) 1359 return -ENOMEM; 1360 1361 ret = nand_scan_tail(mtd); 1362 if (ret) 1363 goto free_buf; 1364 1365 ret = nand_register(0, mtd); 1366 if (ret) { 1367 dev_err(denali->dev, "Failed to register MTD: %d\n", ret); 1368 goto free_buf; 1369 } 1370 return 0; 1371 1372 free_buf: 1373 kfree(denali->buf); 1374 1375 return ret; 1376 } 1377