1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * NAND driver for TI DaVinci based boards.
4  *
5  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6  *
7  * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
8  */
9 
10 /*
11  *
12  * linux/drivers/mtd/nand/raw/nand_davinci.c
13  *
14  * NAND Flash Driver
15  *
16  * Copyright (C) 2006 Texas Instruments.
17  *
18  * ----------------------------------------------------------------------------
19  *
20  * ----------------------------------------------------------------------------
21  *
22  *  Overview:
23  *   This is a device driver for the NAND flash device found on the
24  *   DaVinci board which utilizes the Samsung k9k2g08 part.
25  *
26  Modifications:
27  ver. 1.0: Feb 2005, Vinod/Sudhakar
28  -
29  */
30 
31 #include <common.h>
32 #include <asm/io.h>
33 #include <nand.h>
34 #include <asm/ti-common/davinci_nand.h>
35 
36 /* Definitions for 4-bit hardware ECC */
37 #define NAND_TIMEOUT			10240
38 #define NAND_ECC_BUSY			0xC
39 #define NAND_4BITECC_MASK		0x03FF03FF
40 #define EMIF_NANDFSR_ECC_STATE_MASK  	0x00000F00
41 #define ECC_STATE_NO_ERR		0x0
42 #define ECC_STATE_TOO_MANY_ERRS		0x1
43 #define ECC_STATE_ERR_CORR_COMP_P	0x2
44 #define ECC_STATE_ERR_CORR_COMP_N	0x3
45 
46 /*
47  * Exploit the little endianness of the ARM to do multi-byte transfers
48  * per device read. This can perform over twice as quickly as individual
49  * byte transfers when buffer alignment is conducive.
50  *
51  * NOTE: This only works if the NAND is not connected to the 2 LSBs of
52  * the address bus. On Davinci EVM platforms this has always been true.
53  */
54 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
55 {
56 	struct nand_chip *chip = mtd_to_nand(mtd);
57 	const u32 *nand = chip->IO_ADDR_R;
58 
59 	/* Make sure that buf is 32 bit aligned */
60 	if (((int)buf & 0x3) != 0) {
61 		if (((int)buf & 0x1) != 0) {
62 			if (len) {
63 				*buf = readb(nand);
64 				buf += 1;
65 				len--;
66 			}
67 		}
68 
69 		if (((int)buf & 0x3) != 0) {
70 			if (len >= 2) {
71 				*(u16 *)buf = readw(nand);
72 				buf += 2;
73 				len -= 2;
74 			}
75 		}
76 	}
77 
78 	/* copy aligned data */
79 	while (len >= 4) {
80 		*(u32 *)buf = __raw_readl(nand);
81 		buf += 4;
82 		len -= 4;
83 	}
84 
85 	/* mop up any remaining bytes */
86 	if (len) {
87 		if (len >= 2) {
88 			*(u16 *)buf = readw(nand);
89 			buf += 2;
90 			len -= 2;
91 		}
92 
93 		if (len)
94 			*buf = readb(nand);
95 	}
96 }
97 
98 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
99 				   int len)
100 {
101 	struct nand_chip *chip = mtd_to_nand(mtd);
102 	const u32 *nand = chip->IO_ADDR_W;
103 
104 	/* Make sure that buf is 32 bit aligned */
105 	if (((int)buf & 0x3) != 0) {
106 		if (((int)buf & 0x1) != 0) {
107 			if (len) {
108 				writeb(*buf, nand);
109 				buf += 1;
110 				len--;
111 			}
112 		}
113 
114 		if (((int)buf & 0x3) != 0) {
115 			if (len >= 2) {
116 				writew(*(u16 *)buf, nand);
117 				buf += 2;
118 				len -= 2;
119 			}
120 		}
121 	}
122 
123 	/* copy aligned data */
124 	while (len >= 4) {
125 		__raw_writel(*(u32 *)buf, nand);
126 		buf += 4;
127 		len -= 4;
128 	}
129 
130 	/* mop up any remaining bytes */
131 	if (len) {
132 		if (len >= 2) {
133 			writew(*(u16 *)buf, nand);
134 			buf += 2;
135 			len -= 2;
136 		}
137 
138 		if (len)
139 			writeb(*buf, nand);
140 	}
141 }
142 
143 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
144 		unsigned int ctrl)
145 {
146 	struct		nand_chip *this = mtd_to_nand(mtd);
147 	u_int32_t	IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
148 
149 	if (ctrl & NAND_CTRL_CHANGE) {
150 		IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
151 
152 		if (ctrl & NAND_CLE)
153 			IO_ADDR_W |= MASK_CLE;
154 		if (ctrl & NAND_ALE)
155 			IO_ADDR_W |= MASK_ALE;
156 		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
157 	}
158 
159 	if (cmd != NAND_CMD_NONE)
160 		writeb(cmd, IO_ADDR_W);
161 }
162 
163 #ifdef CONFIG_SYS_NAND_HW_ECC
164 
165 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
166 {
167 	u_int32_t	ecc = 0;
168 
169 	ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
170 				CONFIG_SYS_NAND_CS - 2]));
171 
172 	return ecc;
173 }
174 
175 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
176 {
177 	u_int32_t	val;
178 
179 	/* reading the ECC result register resets the ECC calculation */
180 	nand_davinci_readecc(mtd);
181 
182 	val = __raw_readl(&davinci_emif_regs->nandfcr);
183 	val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
184 	val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
185 	__raw_writel(val, &davinci_emif_regs->nandfcr);
186 }
187 
188 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
189 		u_char *ecc_code)
190 {
191 	u_int32_t		tmp;
192 
193 	tmp = nand_davinci_readecc(mtd);
194 
195 	/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
196 	 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
197 	tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
198 
199 	/* Invert so that erased block ECC is correct */
200 	tmp = ~tmp;
201 
202 	*ecc_code++ = tmp;
203 	*ecc_code++ = tmp >>  8;
204 	*ecc_code++ = tmp >> 16;
205 
206 	/* NOTE:  the above code matches mainline Linux:
207 	 *	.PQR.stu ==> ~PQRstu
208 	 *
209 	 * MontaVista/TI kernels encode those bytes differently, use
210 	 * complicated (and allegedly sometimes-wrong) correction code,
211 	 * and usually shipped with U-Boot that uses software ECC:
212 	 *	.PQR.stu ==> PsQRtu
213 	 *
214 	 * If you need MV/TI compatible NAND I/O in U-Boot, it should
215 	 * be possible to (a) change the mangling above, (b) reverse
216 	 * that mangling in nand_davinci_correct_data() below.
217 	 */
218 
219 	return 0;
220 }
221 
222 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
223 		u_char *read_ecc, u_char *calc_ecc)
224 {
225 	struct nand_chip *this = mtd_to_nand(mtd);
226 	u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
227 					  (read_ecc[2] << 16);
228 	u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
229 					  (calc_ecc[2] << 16);
230 	u_int32_t diff = ecc_calc ^ ecc_nand;
231 
232 	if (diff) {
233 		if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
234 			/* Correctable error */
235 			if ((diff >> (12 + 3)) < this->ecc.size) {
236 				uint8_t find_bit = 1 << ((diff >> 12) & 7);
237 				uint32_t find_byte = diff >> (12 + 3);
238 
239 				dat[find_byte] ^= find_bit;
240 				pr_debug("Correcting single "
241 					 "bit ECC error at offset: %d, bit: "
242 					 "%d\n", find_byte, find_bit);
243 				return 1;
244 			} else {
245 				return -EBADMSG;
246 			}
247 		} else if (!(diff & (diff - 1))) {
248 			/* Single bit ECC error in the ECC itself,
249 			   nothing to fix */
250 			pr_debug("Single bit ECC error in " "ECC.\n");
251 			return 1;
252 		} else {
253 			/* Uncorrectable error */
254 			pr_debug("ECC UNCORRECTED_ERROR 1\n");
255 			return -EBADMSG;
256 		}
257 	}
258 	return 0;
259 }
260 #endif /* CONFIG_SYS_NAND_HW_ECC */
261 
262 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
263 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
264 #if defined(CONFIG_SYS_NAND_PAGE_2K)
265 	.eccbytes = 40,
266 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
267 	.eccpos = {
268 		6,   7,  8,  9, 10,	11, 12, 13, 14, 15,
269 		22, 23, 24, 25, 26,	27, 28, 29, 30, 31,
270 		38, 39, 40, 41, 42,	43, 44, 45, 46, 47,
271 		54, 55, 56, 57, 58,	59, 60, 61, 62, 63,
272 	},
273 	.oobfree = {
274 		{2, 4}, {16, 6}, {32, 6}, {48, 6},
275 	},
276 #else
277 	.eccpos = {
278 		24, 25, 26, 27, 28,
279 		29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
280 		39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
281 		49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
282 		59, 60, 61, 62, 63,
283 		},
284 	.oobfree = {
285 		{.offset = 2, .length = 22, },
286 	},
287 #endif	/* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
288 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
289 	.eccbytes = 80,
290 	.eccpos = {
291 		48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
292 		58, 59, 60, 61, 62, 63,	64, 65, 66, 67,
293 		68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
294 		78, 79,	80, 81, 82, 83,	84, 85, 86, 87,
295 		88, 89, 90, 91, 92, 93,	94, 95, 96, 97,
296 		98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
297 		108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
298 		118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
299 		},
300 	.oobfree = {
301 		{.offset = 2, .length = 46, },
302 	},
303 #endif
304 };
305 
306 #if defined CONFIG_KEYSTONE_RBL_NAND
307 static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
308 #if defined(CONFIG_SYS_NAND_PAGE_2K)
309 	.eccbytes = 40,
310 	.eccpos = {
311 		6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
312 		22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
313 		38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
314 		54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
315 	},
316 	.oobfree = {
317 		{.offset = 2, .length = 4, },
318 		{.offset = 16, .length = 6, },
319 		{.offset = 32, .length = 6, },
320 		{.offset = 48, .length = 6, },
321 	},
322 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
323 	.eccbytes = 80,
324 	.eccpos = {
325 		6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
326 		22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
327 		38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
328 		54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
329 		70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
330 		86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
331 		102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
332 		118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
333 	},
334 	.oobfree = {
335 		{.offset = 2, .length = 4, },
336 		{.offset = 16, .length = 6, },
337 		{.offset = 32, .length = 6, },
338 		{.offset = 48, .length = 6, },
339 		{.offset = 64, .length = 6, },
340 		{.offset = 80, .length = 6, },
341 		{.offset = 96, .length = 6, },
342 		{.offset = 112, .length = 6, },
343 	},
344 #endif
345 };
346 
347 #ifdef CONFIG_SYS_NAND_PAGE_2K
348 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE	CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
349 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
350 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE	CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
351 #endif
352 
353 /**
354  * nand_davinci_write_page - write one page
355  * @mtd: MTD device structure
356  * @chip: NAND chip descriptor
357  * @buf: the data to write
358  * @oob_required: must write chip->oob_poi to OOB
359  * @page: page number to write
360  * @raw: use _raw version of write_page
361  */
362 static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
363 				   uint32_t offset, int data_len,
364 				   const uint8_t *buf, int oob_required,
365 				   int page, int raw)
366 {
367 	int status;
368 	int ret = 0;
369 	struct nand_ecclayout *saved_ecc_layout;
370 
371 	/* save current ECC layout and assign Keystone RBL ECC layout */
372 	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
373 		saved_ecc_layout = chip->ecc.layout;
374 		chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
375 		mtd->oobavail = chip->ecc.layout->oobavail;
376 	}
377 
378 	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
379 
380 	if (unlikely(raw)) {
381 		status = chip->ecc.write_page_raw(mtd, chip, buf,
382 						  oob_required, page);
383 	} else {
384 		status = chip->ecc.write_page(mtd, chip, buf,
385 					      oob_required, page);
386 	}
387 
388 	if (status < 0) {
389 		ret = status;
390 		goto err;
391 	}
392 
393 	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
394 	status = chip->waitfunc(mtd, chip);
395 
396 	if (status & NAND_STATUS_FAIL) {
397 		ret = -EIO;
398 		goto err;
399 	}
400 
401 err:
402 	/* restore ECC layout */
403 	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
404 		chip->ecc.layout = saved_ecc_layout;
405 		mtd->oobavail = saved_ecc_layout->oobavail;
406 	}
407 
408 	return ret;
409 }
410 
411 /**
412  * nand_davinci_read_page_hwecc - hardware ECC based page read function
413  * @mtd: mtd info structure
414  * @chip: nand chip info structure
415  * @buf: buffer to store read data
416  * @oob_required: caller requires OOB data read to chip->oob_poi
417  * @page: page number to read
418  *
419  * Not for syndrome calculating ECC controllers which need a special oob layout.
420  */
421 static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
422 				uint8_t *buf, int oob_required, int page)
423 {
424 	int i, eccsize = chip->ecc.size;
425 	int eccbytes = chip->ecc.bytes;
426 	int eccsteps = chip->ecc.steps;
427 	uint32_t *eccpos;
428 	uint8_t *p = buf;
429 	uint8_t *ecc_code = chip->buffers->ecccode;
430 	uint8_t *ecc_calc = chip->buffers->ecccalc;
431 	struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
432 
433 	/* save current ECC layout and assign Keystone RBL ECC layout */
434 	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
435 		chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
436 		mtd->oobavail = chip->ecc.layout->oobavail;
437 	}
438 
439 	eccpos = chip->ecc.layout->eccpos;
440 
441 	/* Read the OOB area first */
442 	chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
443 	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
444 	chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
445 
446 	for (i = 0; i < chip->ecc.total; i++)
447 		ecc_code[i] = chip->oob_poi[eccpos[i]];
448 
449 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
450 		int stat;
451 
452 		chip->ecc.hwctl(mtd, NAND_ECC_READ);
453 		chip->read_buf(mtd, p, eccsize);
454 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
455 
456 		stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
457 		if (stat < 0)
458 			mtd->ecc_stats.failed++;
459 		else
460 			mtd->ecc_stats.corrected += stat;
461 	}
462 
463 	/* restore ECC layout */
464 	if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
465 		chip->ecc.layout = saved_ecc_layout;
466 		mtd->oobavail = saved_ecc_layout->oobavail;
467 	}
468 
469 	return 0;
470 }
471 #endif /* CONFIG_KEYSTONE_RBL_NAND */
472 
473 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
474 {
475 	u32 val;
476 
477 	switch (mode) {
478 	case NAND_ECC_WRITE:
479 	case NAND_ECC_READ:
480 		/*
481 		 * Start a new ECC calculation for reading or writing 512 bytes
482 		 * of data.
483 		 */
484 		val = __raw_readl(&davinci_emif_regs->nandfcr);
485 		val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
486 		val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
487 		val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
488 		val |= DAVINCI_NANDFCR_4BIT_ECC_START;
489 		__raw_writel(val, &davinci_emif_regs->nandfcr);
490 		break;
491 	case NAND_ECC_READSYN:
492 		val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
493 		break;
494 	default:
495 		break;
496 	}
497 }
498 
499 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
500 {
501 	int i;
502 
503 	for (i = 0; i < 4; i++) {
504 		ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
505 			NAND_4BITECC_MASK;
506 	}
507 
508 	return 0;
509 }
510 
511 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
512 					   const uint8_t *dat,
513 					   uint8_t *ecc_code)
514 {
515 	unsigned int hw_4ecc[4];
516 	unsigned int i;
517 
518 	nand_davinci_4bit_readecc(mtd, hw_4ecc);
519 
520 	/*Convert 10 bit ecc value to 8 bit */
521 	for (i = 0; i < 2; i++) {
522 		unsigned int hw_ecc_low = hw_4ecc[i * 2];
523 		unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
524 
525 		/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
526 		*ecc_code++ = hw_ecc_low & 0xFF;
527 
528 		/*
529 		 * Take 2 bits as LSB bits from val1 (count1=0) or val5
530 		 * (count1=1) and 6 bits from val2 (count1=0) or
531 		 * val5 (count1=1)
532 		 */
533 		*ecc_code++ =
534 		    ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
535 
536 		/*
537 		 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
538 		 * 4 bits from val3 (count1=0) or val6 (count1=1)
539 		 */
540 		*ecc_code++ =
541 		    ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
542 
543 		/*
544 		 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
545 		 * 2 bits from val4 (count1=0) or  val7 (count1=1)
546 		 */
547 		*ecc_code++ =
548 		    ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
549 
550 		/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
551 		*ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
552 	}
553 
554 	return 0;
555 }
556 
557 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
558 					  uint8_t *read_ecc, uint8_t *calc_ecc)
559 {
560 	int i;
561 	unsigned int hw_4ecc[4];
562 	unsigned int iserror;
563 	unsigned short *ecc16;
564 	unsigned int numerrors, erroraddress, errorvalue;
565 	u32 val;
566 
567 	/*
568 	 * Check for an ECC where all bytes are 0xFF.  If this is the case, we
569 	 * will assume we are looking at an erased page and we should ignore
570 	 * the ECC.
571 	 */
572 	for (i = 0; i < 10; i++) {
573 		if (read_ecc[i] != 0xFF)
574 			break;
575 	}
576 	if (i == 10)
577 		return 0;
578 
579 	/* Convert 8 bit in to 10 bit */
580 	ecc16 = (unsigned short *)&read_ecc[0];
581 
582 	/*
583 	 * Write the parity values in the NAND Flash 4-bit ECC Load register.
584 	 * Write each parity value one at a time starting from 4bit_ecc_val8
585 	 * to 4bit_ecc_val1.
586 	 */
587 
588 	/*Take 2 bits from 8th byte and 8 bits from 9th byte */
589 	__raw_writel(((ecc16[4]) >> 6) & 0x3FF,
590 			&davinci_emif_regs->nand4biteccload);
591 
592 	/* Take 4 bits from 7th byte and 6 bits from 8th byte */
593 	__raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
594 			&davinci_emif_regs->nand4biteccload);
595 
596 	/* Take 6 bits from 6th byte and 4 bits from 7th byte */
597 	__raw_writel((ecc16[3] >> 2) & 0x3FF,
598 			&davinci_emif_regs->nand4biteccload);
599 
600 	/* Take 8 bits from 5th byte and 2 bits from 6th byte */
601 	__raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
602 			&davinci_emif_regs->nand4biteccload);
603 
604 	/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
605 	__raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
606 			&davinci_emif_regs->nand4biteccload);
607 
608 	/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
609 	__raw_writel(((ecc16[1]) >> 4) & 0x3FF,
610 			&davinci_emif_regs->nand4biteccload);
611 
612 	/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
613 	__raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
614 			&davinci_emif_regs->nand4biteccload);
615 
616 	/* Take 10 bits from 0th and 1st bytes */
617 	__raw_writel((ecc16[0]) & 0x3FF,
618 			&davinci_emif_regs->nand4biteccload);
619 
620 	/*
621 	 * Perform a dummy read to the EMIF Revision Code and Status register.
622 	 * This is required to ensure time for syndrome calculation after
623 	 * writing the ECC values in previous step.
624 	 */
625 
626 	val = __raw_readl(&davinci_emif_regs->nandfsr);
627 
628 	/*
629 	 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
630 	 * A syndrome value of 0 means no bit errors. If the syndrome is
631 	 * non-zero then go further otherwise return.
632 	 */
633 	nand_davinci_4bit_readecc(mtd, hw_4ecc);
634 
635 	if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
636 		return 0;
637 
638 	/*
639 	 * Clear any previous address calculation by doing a dummy read of an
640 	 * error address register.
641 	 */
642 	val = __raw_readl(&davinci_emif_regs->nanderradd1);
643 
644 	/*
645 	 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
646 	 * register to 1.
647 	 */
648 	__raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
649 			&davinci_emif_regs->nandfcr);
650 
651 	/*
652 	 * Wait for the corr_state field (bits 8 to 11) in the
653 	 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
654 	 * Otherwise ECC calculation has not even begun and the next loop might
655 	 * fail because of a false positive!
656 	 */
657 	i = NAND_TIMEOUT;
658 	do {
659 		val = __raw_readl(&davinci_emif_regs->nandfsr);
660 		val &= 0xc00;
661 		i--;
662 	} while ((i > 0) && !val);
663 
664 	/*
665 	 * Wait for the corr_state field (bits 8 to 11) in the
666 	 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
667 	 */
668 	i = NAND_TIMEOUT;
669 	do {
670 		val = __raw_readl(&davinci_emif_regs->nandfsr);
671 		val &= 0xc00;
672 		i--;
673 	} while ((i > 0) && val);
674 
675 	iserror = __raw_readl(&davinci_emif_regs->nandfsr);
676 	iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
677 	iserror = iserror >> 8;
678 
679 	/*
680 	 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
681 	 * corrected (five or more errors).  The number of errors
682 	 * calculated (err_num field) differs from the number of errors
683 	 * searched.  ECC_STATE_ERR_CORR_COMP_P (0x2) means error
684 	 * correction complete (errors on bit 8 or 9).
685 	 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
686 	 * complete (error exists).
687 	 */
688 
689 	if (iserror == ECC_STATE_NO_ERR) {
690 		val = __raw_readl(&davinci_emif_regs->nanderrval1);
691 		return 0;
692 	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
693 		val = __raw_readl(&davinci_emif_regs->nanderrval1);
694 		return -EBADMSG;
695 	}
696 
697 	numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
698 			& 0x3) + 1;
699 
700 	/* Read the error address, error value and correct */
701 	for (i = 0; i < numerrors; i++) {
702 		if (i > 1) {
703 			erroraddress =
704 			    ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
705 			      (16 * (i & 1))) & 0x3FF);
706 			erroraddress = ((512 + 7) - erroraddress);
707 			errorvalue =
708 			    ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
709 			      (16 * (i & 1))) & 0xFF);
710 		} else {
711 			erroraddress =
712 			    ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
713 			      (16 * (i & 1))) & 0x3FF);
714 			erroraddress = ((512 + 7) - erroraddress);
715 			errorvalue =
716 			    ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
717 			      (16 * (i & 1))) & 0xFF);
718 		}
719 		/* xor the corrupt data with error value */
720 		if (erroraddress < 512)
721 			dat[erroraddress] ^= errorvalue;
722 	}
723 
724 	return numerrors;
725 }
726 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
727 
728 static int nand_davinci_dev_ready(struct mtd_info *mtd)
729 {
730 	return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
731 }
732 
733 static void nand_flash_init(void)
734 {
735 	/* This is for DM6446 EVM and *very* similar.  DO NOT GROW THIS!
736 	 * Instead, have your board_init() set EMIF timings, based on its
737 	 * knowledge of the clocks and what devices are hooked up ... and
738 	 * don't even do that unless no UBL handled it.
739 	 */
740 #ifdef CONFIG_SOC_DM644X
741 	u_int32_t	acfg1 = 0x3ffffffc;
742 
743 	/*------------------------------------------------------------------*
744 	 *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
745 	 *                                                                  *
746 	 *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
747 	 *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
748 	 *                                                                  *
749 	 *------------------------------------------------------------------*/
750 	 acfg1 = 0
751 		| (0 << 31)	/* selectStrobe */
752 		| (0 << 30)	/* extWait */
753 		| (1 << 26)	/* writeSetup	10 ns */
754 		| (3 << 20)	/* writeStrobe	40 ns */
755 		| (1 << 17)	/* writeHold	10 ns */
756 		| (1 << 13)	/* readSetup	10 ns */
757 		| (5 << 7)	/* readStrobe	60 ns */
758 		| (1 << 4)	/* readHold	10 ns */
759 		| (3 << 2)	/* turnAround	?? ns */
760 		| (0 << 0)	/* asyncSize	8-bit bus */
761 		;
762 
763 	__raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
764 
765 	/* NAND flash on CS2 */
766 	__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
767 #endif
768 }
769 
770 void davinci_nand_init(struct nand_chip *nand)
771 {
772 #if defined CONFIG_KEYSTONE_RBL_NAND
773 	int i;
774 	struct nand_ecclayout *layout;
775 
776 	layout = &nand_keystone_rbl_4bit_layout_oobfirst;
777 	layout->oobavail = 0;
778 	for (i = 0; layout->oobfree[i].length &&
779 	     i < ARRAY_SIZE(layout->oobfree); i++)
780 		layout->oobavail += layout->oobfree[i].length;
781 
782 	nand->write_page = nand_davinci_write_page;
783 	nand->ecc.read_page = nand_davinci_read_page_hwecc;
784 #endif
785 	nand->chip_delay  = 0;
786 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
787 	nand->bbt_options	  |= NAND_BBT_USE_FLASH;
788 #endif
789 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
790 	nand->options	  |= NAND_NO_SUBPAGE_WRITE;
791 #endif
792 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
793 	nand->options	  |= NAND_BUSWIDTH_16;
794 #endif
795 #ifdef CONFIG_SYS_NAND_HW_ECC
796 	nand->ecc.mode = NAND_ECC_HW;
797 	nand->ecc.size = 512;
798 	nand->ecc.bytes = 3;
799 	nand->ecc.strength = 1;
800 	nand->ecc.calculate = nand_davinci_calculate_ecc;
801 	nand->ecc.correct  = nand_davinci_correct_data;
802 	nand->ecc.hwctl  = nand_davinci_enable_hwecc;
803 #else
804 	nand->ecc.mode = NAND_ECC_SOFT;
805 #endif /* CONFIG_SYS_NAND_HW_ECC */
806 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
807 	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
808 	nand->ecc.size = 512;
809 	nand->ecc.bytes = 10;
810 	nand->ecc.strength = 4;
811 	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
812 	nand->ecc.correct = nand_davinci_4bit_correct_data;
813 	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
814 	nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
815 #endif
816 	/* Set address of hardware control function */
817 	nand->cmd_ctrl = nand_davinci_hwcontrol;
818 
819 	nand->read_buf = nand_davinci_read_buf;
820 	nand->write_buf = nand_davinci_write_buf;
821 
822 	nand->dev_ready = nand_davinci_dev_ready;
823 
824 	nand_flash_init();
825 }
826 
827 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
828 
829 int board_nand_init(struct nand_chip *chip)
830 {
831 	davinci_nand_init(chip);
832 	return 0;
833 }
834