xref: /openbmc/u-boot/drivers/mtd/nand/raw/Kconfig (revision e7ab6dfc)
1
2menuconfig NAND
3	bool "Raw NAND Device Support"
4if NAND
5
6config SYS_NAND_SELF_INIT
7	bool
8	help
9	  This option, if enabled, provides more flexible and linux-like
10	  NAND initialization process.
11
12config NAND_ATMEL
13	bool "Support Atmel NAND controller"
14	imply SYS_NAND_USE_FLASH_BBT
15	help
16	  Enable this driver for NAND flash platforms using an Atmel NAND
17	  controller.
18
19config NAND_DAVINCI
20	bool "Support TI Davinci NAND controller"
21	help
22	  Enable this driver for NAND flash controllers available in TI Davinci
23	  and Keystone2 platforms
24
25config NAND_DENALI
26	bool
27	select SYS_NAND_SELF_INIT
28	imply CMD_NAND
29
30config NAND_DENALI_DT
31	bool "Support Denali NAND controller as a DT device"
32	select NAND_DENALI
33	depends on OF_CONTROL && DM
34	help
35	  Enable the driver for NAND flash on platforms using a Denali NAND
36	  controller as a DT device.
37
38config NAND_DENALI_SPARE_AREA_SKIP_BYTES
39	int "Number of bytes skipped in OOB area"
40	depends on NAND_DENALI
41	range 0 63
42	help
43	  This option specifies the number of bytes to skip from the beginning
44	  of OOB area before last ECC sector data starts.  This is potentially
45	  used to preserve the bad block marker in the OOB area.
46
47config NAND_LPC32XX_SLC
48	bool "Support LPC32XX_SLC controller"
49	help
50	  Enable the LPC32XX SLC NAND controller.
51
52config NAND_OMAP_GPMC
53	bool "Support OMAP GPMC NAND controller"
54	depends on ARCH_OMAP2PLUS
55	help
56	  Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
57	  GPMC controller is used for parallel NAND flash devices, and can
58	  do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
59	  and BCH16 ECC algorithms.
60
61config NAND_OMAP_GPMC_PREFETCH
62	bool "Enable GPMC Prefetch"
63	depends on NAND_OMAP_GPMC
64	default y
65	help
66	  On OMAP platforms that use the GPMC controller
67	  (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
68	  uses the prefetch mode to speed up read operations.
69
70config NAND_OMAP_ELM
71	bool "Enable ELM driver for OMAPxx and AMxx platforms."
72	depends on NAND_OMAP_GPMC && !OMAP34XX
73	help
74	  ELM controller is used for ECC error detection (not ECC calculation)
75	  of BCH4, BCH8 and BCH16 ECC algorithms.
76	  Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
77	  thus such SoC platforms need to depend on software library for ECC error
78	  detection. However ECC calculation on such plaforms would still be
79	  done by GPMC controller.
80
81config NAND_VF610_NFC
82	bool "Support for Freescale NFC for VF610"
83	select SYS_NAND_SELF_INIT
84	imply CMD_NAND
85	help
86	  Enables support for NAND Flash Controller on some Freescale
87	  processors like the VF610, MCF54418 or Kinetis K70.
88	  The driver supports a maximum 2k page size. The driver
89	  currently does not support hardware ECC.
90
91if NAND_VF610_NFC
92
93config NAND_VF610_NFC_DT
94        bool "Support Vybrid's vf610 NAND controller as a DT device"
95        depends on OF_CONTROL && MTD
96        help
97          Enable the driver for Vybrid's vf610 NAND flash on platforms
98	  using device tree.
99
100choice
101	prompt "Hardware ECC strength"
102	depends on NAND_VF610_NFC
103	default SYS_NAND_VF610_NFC_45_ECC_BYTES
104	help
105	  Select the ECC strength used in the hardware BCH ECC block.
106
107config SYS_NAND_VF610_NFC_45_ECC_BYTES
108	bool "24-error correction (45 ECC bytes)"
109
110config SYS_NAND_VF610_NFC_60_ECC_BYTES
111	bool "32-error correction (60 ECC bytes)"
112
113endchoice
114
115endif
116
117config NAND_PXA3XX
118	bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
119	select SYS_NAND_SELF_INIT
120	imply CMD_NAND
121	help
122	  This enables the driver for the NAND flash device found on
123	  PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
124
125config NAND_SUNXI
126	bool "Support for NAND on Allwinner SoCs"
127	default ARCH_SUNXI
128	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
129	select SYS_NAND_SELF_INIT
130	select SYS_NAND_U_BOOT_LOCATIONS
131	select SPL_NAND_SUPPORT
132	imply CMD_NAND
133	---help---
134	Enable support for NAND. This option enables the standard and
135	SPL drivers.
136	The SPL driver only supports reading from the NAND using DMA
137	transfers.
138
139if NAND_SUNXI
140
141config NAND_SUNXI_SPL_ECC_STRENGTH
142	int "Allwinner NAND SPL ECC Strength"
143	default 64
144
145config NAND_SUNXI_SPL_ECC_SIZE
146	int "Allwinner NAND SPL ECC Step Size"
147	default 1024
148
149config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
150	int "Allwinner NAND SPL Usable Page Size"
151	default 1024
152
153endif
154
155config NAND_ARASAN
156	bool "Configure Arasan Nand"
157	select SYS_NAND_SELF_INIT
158	imply CMD_NAND
159	help
160	  This enables Nand driver support for Arasan nand flash
161	  controller. This uses the hardware ECC for read and
162	  write operations.
163
164config NAND_MXC
165	bool "MXC NAND support"
166	depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
167	imply CMD_NAND
168	help
169	  This enables the NAND driver for the NAND flash controller on the
170	  i.MX27 / i.MX31 / i.MX5 rocessors.
171
172config NAND_MXS
173	bool "MXS NAND support"
174	depends on MX23 || MX28 || MX6 || MX7
175	select SYS_NAND_SELF_INIT
176	imply CMD_NAND
177	select APBH_DMA
178	select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7
179	select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7
180	help
181	  This enables NAND driver for the NAND flash controller on the
182	  MXS processors.
183
184if NAND_MXS
185
186config NAND_MXS_DT
187	bool "Support MXS NAND controller as a DT device"
188	depends on OF_CONTROL && MTD
189	help
190	  Enable the driver for MXS NAND flash on platforms using
191	  device tree.
192
193config NAND_MXS_USE_MINIMUM_ECC
194	bool "Use minimum ECC strength supported by the controller"
195	default false
196
197endif
198
199config NAND_ZYNQ
200	bool "Support for Zynq Nand controller"
201	select SYS_NAND_SELF_INIT
202	imply CMD_NAND
203	help
204	  This enables Nand driver support for Nand flash controller
205	  found on Zynq SoC.
206
207config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
208	bool "Enable use of 1st stage bootloader timing for NAND"
209	depends on NAND_ZYNQ
210	help
211	  This flag prevent U-boot reconfigure NAND flash controller and reuse
212	  the NAND timing from 1st stage bootloader.
213
214comment "Generic NAND options"
215
216config SYS_NAND_BLOCK_SIZE
217	hex "NAND chip eraseblock size"
218	depends on ARCH_SUNXI
219	help
220	  Number of data bytes in one eraseblock for the NAND chip on the
221	  board. This is the multiple of NAND_PAGE_SIZE and the number of
222	  pages.
223
224config SYS_NAND_PAGE_SIZE
225	hex "NAND chip page size"
226	depends on ARCH_SUNXI
227	help
228	  Number of data bytes in one page for the NAND chip on the
229	  board, not including the OOB area.
230
231config SYS_NAND_OOBSIZE
232	hex "NAND chip OOB size"
233	depends on ARCH_SUNXI
234	help
235	  Number of bytes in the Out-Of-Band area for the NAND chip on
236	  the board.
237
238# Enhance depends when converting drivers to Kconfig which use this config
239# option (mxc_nand, ndfc, omap_gpmc).
240config SYS_NAND_BUSWIDTH_16BIT
241	bool "Use 16-bit NAND interface"
242	depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
243	help
244	  Indicates that NAND device has 16-bit wide data-bus. In absence of this
245	  config, bus-width of NAND device is assumed to be either 8-bit and later
246	  determined by reading ONFI params.
247	  Above config is useful when NAND device's bus-width information cannot
248	  be determined from on-chip ONFI params, like in following scenarios:
249	  - SPL boot does not support reading of ONFI parameters. This is done to
250	    keep SPL code foot-print small.
251	  - In current U-Boot flow using nand_init(), driver initialization
252	    happens in board_nand_init() which is called before any device probe
253	    (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
254	    not available while configuring controller. So a static CONFIG_NAND_xx
255	    is needed to know the device's bus-width in advance.
256
257if SPL
258
259config SYS_NAND_U_BOOT_LOCATIONS
260	bool "Define U-boot binaries locations in NAND"
261	help
262	Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
263	This option should not be enabled when compiling U-boot for boards
264	defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
265	file.
266
267config SYS_NAND_U_BOOT_OFFS
268	hex "Location in NAND to read U-Boot from"
269	default 0x800000 if NAND_SUNXI
270	depends on SYS_NAND_U_BOOT_LOCATIONS
271	help
272	Set the offset from the start of the nand where u-boot should be
273	loaded from.
274
275config SYS_NAND_U_BOOT_OFFS_REDUND
276	hex "Location in NAND to read U-Boot from"
277	default SYS_NAND_U_BOOT_OFFS
278	depends on SYS_NAND_U_BOOT_LOCATIONS
279	help
280	Set the offset from the start of the nand where the redundant u-boot
281	should be loaded from.
282
283config SPL_NAND_AM33XX_BCH
284	bool "Enables SPL-NAND driver which supports ELM based"
285	depends on NAND_OMAP_GPMC && !OMAP34XX
286	default y
287        help
288	  Hardware ECC correction. This is useful for platforms which have ELM
289	  hardware engine and use NAND boot mode.
290	  Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
291	  so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
292          SPL-NAND driver with software ECC correction support.
293
294config SPL_NAND_DENALI
295	bool "Support Denali NAND controller for SPL"
296	help
297	  This is a small implementation of the Denali NAND controller
298	  for use on SPL.
299
300config SPL_NAND_SIMPLE
301	bool "Use simple SPL NAND driver"
302	depends on !SPL_NAND_AM33XX_BCH
303	help
304	  Support for NAND boot using simple NAND drivers that
305	  expose the cmd_ctrl() interface.
306endif
307
308endif   # if NAND
309