1 2menuconfig NAND 3 bool "Raw NAND Device Support" 4if NAND 5 6config SYS_NAND_SELF_INIT 7 bool 8 help 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 11 12config NAND_ATMEL 13 bool "Support Atmel NAND controller" 14 imply SYS_NAND_USE_FLASH_BBT 15 help 16 Enable this driver for NAND flash platforms using an Atmel NAND 17 controller. 18 19config NAND_DAVINCI 20 bool "Support TI Davinci NAND controller" 21 help 22 Enable this driver for NAND flash controllers available in TI Davinci 23 and Keystone2 platforms 24 25config NAND_DENALI 26 bool 27 select SYS_NAND_SELF_INIT 28 imply CMD_NAND 29 30config NAND_DENALI_DT 31 bool "Support Denali NAND controller as a DT device" 32 select NAND_DENALI 33 depends on OF_CONTROL && DM 34 help 35 Enable the driver for NAND flash on platforms using a Denali NAND 36 controller as a DT device. 37 38config NAND_DENALI_SPARE_AREA_SKIP_BYTES 39 int "Number of bytes skipped in OOB area" 40 depends on NAND_DENALI 41 range 0 63 42 help 43 This option specifies the number of bytes to skip from the beginning 44 of OOB area before last ECC sector data starts. This is potentially 45 used to preserve the bad block marker in the OOB area. 46 47config NAND_LPC32XX_SLC 48 bool "Support LPC32XX_SLC controller" 49 help 50 Enable the LPC32XX SLC NAND controller. 51 52config NAND_OMAP_GPMC 53 bool "Support OMAP GPMC NAND controller" 54 depends on ARCH_OMAP2PLUS 55 help 56 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. 57 GPMC controller is used for parallel NAND flash devices, and can 58 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 59 and BCH16 ECC algorithms. 60 61config NAND_OMAP_GPMC_PREFETCH 62 bool "Enable GPMC Prefetch" 63 depends on NAND_OMAP_GPMC 64 default y 65 help 66 On OMAP platforms that use the GPMC controller 67 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that 68 uses the prefetch mode to speed up read operations. 69 70config NAND_OMAP_ELM 71 bool "Enable ELM driver for OMAPxx and AMxx platforms." 72 depends on NAND_OMAP_GPMC && !OMAP34XX 73 help 74 ELM controller is used for ECC error detection (not ECC calculation) 75 of BCH4, BCH8 and BCH16 ECC algorithms. 76 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 77 thus such SoC platforms need to depend on software library for ECC error 78 detection. However ECC calculation on such plaforms would still be 79 done by GPMC controller. 80 81config NAND_VF610_NFC 82 bool "Support for Freescale NFC for VF610" 83 select SYS_NAND_SELF_INIT 84 imply CMD_NAND 85 help 86 Enables support for NAND Flash Controller on some Freescale 87 processors like the VF610, MCF54418 or Kinetis K70. 88 The driver supports a maximum 2k page size. The driver 89 currently does not support hardware ECC. 90 91choice 92 prompt "Hardware ECC strength" 93 depends on NAND_VF610_NFC 94 default SYS_NAND_VF610_NFC_45_ECC_BYTES 95 help 96 Select the ECC strength used in the hardware BCH ECC block. 97 98config SYS_NAND_VF610_NFC_45_ECC_BYTES 99 bool "24-error correction (45 ECC bytes)" 100 101config SYS_NAND_VF610_NFC_60_ECC_BYTES 102 bool "32-error correction (60 ECC bytes)" 103 104endchoice 105 106config NAND_PXA3XX 107 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 108 select SYS_NAND_SELF_INIT 109 imply CMD_NAND 110 help 111 This enables the driver for the NAND flash device found on 112 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). 113 114config NAND_SUNXI 115 bool "Support for NAND on Allwinner SoCs" 116 default ARCH_SUNXI 117 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I 118 select SYS_NAND_SELF_INIT 119 select SYS_NAND_U_BOOT_LOCATIONS 120 select SPL_NAND_SUPPORT 121 imply CMD_NAND 122 ---help--- 123 Enable support for NAND. This option enables the standard and 124 SPL drivers. 125 The SPL driver only supports reading from the NAND using DMA 126 transfers. 127 128if NAND_SUNXI 129 130config NAND_SUNXI_SPL_ECC_STRENGTH 131 int "Allwinner NAND SPL ECC Strength" 132 default 64 133 134config NAND_SUNXI_SPL_ECC_SIZE 135 int "Allwinner NAND SPL ECC Step Size" 136 default 1024 137 138config NAND_SUNXI_SPL_USABLE_PAGE_SIZE 139 int "Allwinner NAND SPL Usable Page Size" 140 default 1024 141 142endif 143 144config NAND_ARASAN 145 bool "Configure Arasan Nand" 146 select SYS_NAND_SELF_INIT 147 imply CMD_NAND 148 help 149 This enables Nand driver support for Arasan nand flash 150 controller. This uses the hardware ECC for read and 151 write operations. 152 153config NAND_MXC 154 bool "MXC NAND support" 155 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 156 imply CMD_NAND 157 help 158 This enables the NAND driver for the NAND flash controller on the 159 i.MX27 / i.MX31 / i.MX5 rocessors. 160 161config NAND_MXS 162 bool "MXS NAND support" 163 depends on MX23 || MX28 || MX6 || MX7 164 select SYS_NAND_SELF_INIT 165 imply CMD_NAND 166 select APBH_DMA 167 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 168 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 169 help 170 This enables NAND driver for the NAND flash controller on the 171 MXS processors. 172 173if NAND_MXS 174 175config NAND_MXS_DT 176 bool "Support MXS NAND controller as a DT device" 177 depends on OF_CONTROL && MTD 178 help 179 Enable the driver for MXS NAND flash on platforms using 180 device tree. 181 182config NAND_MXS_USE_MINIMUM_ECC 183 bool "Use minimum ECC strength supported by the controller" 184 default false 185 186endif 187 188config NAND_ZYNQ 189 bool "Support for Zynq Nand controller" 190 select SYS_NAND_SELF_INIT 191 imply CMD_NAND 192 help 193 This enables Nand driver support for Nand flash controller 194 found on Zynq SoC. 195 196config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 197 bool "Enable use of 1st stage bootloader timing for NAND" 198 depends on NAND_ZYNQ 199 help 200 This flag prevent U-boot reconfigure NAND flash controller and reuse 201 the NAND timing from 1st stage bootloader. 202 203comment "Generic NAND options" 204 205config SYS_NAND_BLOCK_SIZE 206 hex "NAND chip eraseblock size" 207 depends on ARCH_SUNXI 208 help 209 Number of data bytes in one eraseblock for the NAND chip on the 210 board. This is the multiple of NAND_PAGE_SIZE and the number of 211 pages. 212 213config SYS_NAND_PAGE_SIZE 214 hex "NAND chip page size" 215 depends on ARCH_SUNXI 216 help 217 Number of data bytes in one page for the NAND chip on the 218 board, not including the OOB area. 219 220config SYS_NAND_OOBSIZE 221 hex "NAND chip OOB size" 222 depends on ARCH_SUNXI 223 help 224 Number of bytes in the Out-Of-Band area for the NAND chip on 225 the board. 226 227# Enhance depends when converting drivers to Kconfig which use this config 228# option (mxc_nand, ndfc, omap_gpmc). 229config SYS_NAND_BUSWIDTH_16BIT 230 bool "Use 16-bit NAND interface" 231 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI 232 help 233 Indicates that NAND device has 16-bit wide data-bus. In absence of this 234 config, bus-width of NAND device is assumed to be either 8-bit and later 235 determined by reading ONFI params. 236 Above config is useful when NAND device's bus-width information cannot 237 be determined from on-chip ONFI params, like in following scenarios: 238 - SPL boot does not support reading of ONFI parameters. This is done to 239 keep SPL code foot-print small. 240 - In current U-Boot flow using nand_init(), driver initialization 241 happens in board_nand_init() which is called before any device probe 242 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are 243 not available while configuring controller. So a static CONFIG_NAND_xx 244 is needed to know the device's bus-width in advance. 245 246if SPL 247 248config SYS_NAND_U_BOOT_LOCATIONS 249 bool "Define U-boot binaries locations in NAND" 250 help 251 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. 252 This option should not be enabled when compiling U-boot for boards 253 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h 254 file. 255 256config SYS_NAND_U_BOOT_OFFS 257 hex "Location in NAND to read U-Boot from" 258 default 0x800000 if NAND_SUNXI 259 depends on SYS_NAND_U_BOOT_LOCATIONS 260 help 261 Set the offset from the start of the nand where u-boot should be 262 loaded from. 263 264config SYS_NAND_U_BOOT_OFFS_REDUND 265 hex "Location in NAND to read U-Boot from" 266 default SYS_NAND_U_BOOT_OFFS 267 depends on SYS_NAND_U_BOOT_LOCATIONS 268 help 269 Set the offset from the start of the nand where the redundant u-boot 270 should be loaded from. 271 272config SPL_NAND_AM33XX_BCH 273 bool "Enables SPL-NAND driver which supports ELM based" 274 depends on NAND_OMAP_GPMC && !OMAP34XX 275 default y 276 help 277 Hardware ECC correction. This is useful for platforms which have ELM 278 hardware engine and use NAND boot mode. 279 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 280 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling 281 SPL-NAND driver with software ECC correction support. 282 283config SPL_NAND_DENALI 284 bool "Support Denali NAND controller for SPL" 285 help 286 This is a small implementation of the Denali NAND controller 287 for use on SPL. 288 289config SPL_NAND_SIMPLE 290 bool "Use simple SPL NAND driver" 291 depends on !SPL_NAND_AM33XX_BCH 292 help 293 Support for NAND boot using simple NAND drivers that 294 expose the cmd_ctrl() interface. 295endif 296 297endif # if NAND 298