1 2menuconfig NAND 3 bool "Raw NAND Device Support" 4if NAND 5 6config SYS_NAND_SELF_INIT 7 bool 8 help 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 11 12config SYS_NAND_DRIVER_ECC_LAYOUT 13 bool 14 help 15 Omit standard ECC layouts to safe space. Select this if your driver 16 is known to provide its own ECC layout. 17 18config NAND_ATMEL 19 bool "Support Atmel NAND controller" 20 imply SYS_NAND_USE_FLASH_BBT 21 help 22 Enable this driver for NAND flash platforms using an Atmel NAND 23 controller. 24 25config NAND_DAVINCI 26 bool "Support TI Davinci NAND controller" 27 help 28 Enable this driver for NAND flash controllers available in TI Davinci 29 and Keystone2 platforms 30 31config NAND_DENALI 32 bool 33 select SYS_NAND_SELF_INIT 34 imply CMD_NAND 35 36config NAND_DENALI_DT 37 bool "Support Denali NAND controller as a DT device" 38 select NAND_DENALI 39 depends on OF_CONTROL && DM 40 help 41 Enable the driver for NAND flash on platforms using a Denali NAND 42 controller as a DT device. 43 44config NAND_DENALI_SPARE_AREA_SKIP_BYTES 45 int "Number of bytes skipped in OOB area" 46 depends on NAND_DENALI 47 range 0 63 48 help 49 This option specifies the number of bytes to skip from the beginning 50 of OOB area before last ECC sector data starts. This is potentially 51 used to preserve the bad block marker in the OOB area. 52 53config NAND_LPC32XX_SLC 54 bool "Support LPC32XX_SLC controller" 55 help 56 Enable the LPC32XX SLC NAND controller. 57 58config NAND_OMAP_GPMC 59 bool "Support OMAP GPMC NAND controller" 60 depends on ARCH_OMAP2PLUS 61 help 62 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. 63 GPMC controller is used for parallel NAND flash devices, and can 64 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 65 and BCH16 ECC algorithms. 66 67config NAND_OMAP_GPMC_PREFETCH 68 bool "Enable GPMC Prefetch" 69 depends on NAND_OMAP_GPMC 70 default y 71 help 72 On OMAP platforms that use the GPMC controller 73 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that 74 uses the prefetch mode to speed up read operations. 75 76config NAND_OMAP_ELM 77 bool "Enable ELM driver for OMAPxx and AMxx platforms." 78 depends on NAND_OMAP_GPMC && !OMAP34XX 79 help 80 ELM controller is used for ECC error detection (not ECC calculation) 81 of BCH4, BCH8 and BCH16 ECC algorithms. 82 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 83 thus such SoC platforms need to depend on software library for ECC error 84 detection. However ECC calculation on such plaforms would still be 85 done by GPMC controller. 86 87config NAND_VF610_NFC 88 bool "Support for Freescale NFC for VF610" 89 select SYS_NAND_SELF_INIT 90 select SYS_NAND_DRIVER_ECC_LAYOUT 91 imply CMD_NAND 92 help 93 Enables support for NAND Flash Controller on some Freescale 94 processors like the VF610, MCF54418 or Kinetis K70. 95 The driver supports a maximum 2k page size. The driver 96 currently does not support hardware ECC. 97 98if NAND_VF610_NFC 99 100config NAND_VF610_NFC_DT 101 bool "Support Vybrid's vf610 NAND controller as a DT device" 102 depends on OF_CONTROL && MTD 103 help 104 Enable the driver for Vybrid's vf610 NAND flash on platforms 105 using device tree. 106 107choice 108 prompt "Hardware ECC strength" 109 depends on NAND_VF610_NFC 110 default SYS_NAND_VF610_NFC_45_ECC_BYTES 111 help 112 Select the ECC strength used in the hardware BCH ECC block. 113 114config SYS_NAND_VF610_NFC_45_ECC_BYTES 115 bool "24-error correction (45 ECC bytes)" 116 117config SYS_NAND_VF610_NFC_60_ECC_BYTES 118 bool "32-error correction (60 ECC bytes)" 119 120endchoice 121 122endif 123 124config NAND_PXA3XX 125 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 126 select SYS_NAND_SELF_INIT 127 imply CMD_NAND 128 help 129 This enables the driver for the NAND flash device found on 130 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). 131 132config NAND_SUNXI 133 bool "Support for NAND on Allwinner SoCs" 134 default ARCH_SUNXI 135 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I 136 select SYS_NAND_SELF_INIT 137 select SYS_NAND_U_BOOT_LOCATIONS 138 select SPL_NAND_SUPPORT 139 imply CMD_NAND 140 ---help--- 141 Enable support for NAND. This option enables the standard and 142 SPL drivers. 143 The SPL driver only supports reading from the NAND using DMA 144 transfers. 145 146if NAND_SUNXI 147 148config NAND_SUNXI_SPL_ECC_STRENGTH 149 int "Allwinner NAND SPL ECC Strength" 150 default 64 151 152config NAND_SUNXI_SPL_ECC_SIZE 153 int "Allwinner NAND SPL ECC Step Size" 154 default 1024 155 156config NAND_SUNXI_SPL_USABLE_PAGE_SIZE 157 int "Allwinner NAND SPL Usable Page Size" 158 default 1024 159 160endif 161 162config NAND_ARASAN 163 bool "Configure Arasan Nand" 164 select SYS_NAND_SELF_INIT 165 imply CMD_NAND 166 help 167 This enables Nand driver support for Arasan nand flash 168 controller. This uses the hardware ECC for read and 169 write operations. 170 171config NAND_MXC 172 bool "MXC NAND support" 173 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 174 imply CMD_NAND 175 help 176 This enables the NAND driver for the NAND flash controller on the 177 i.MX27 / i.MX31 / i.MX5 rocessors. 178 179config NAND_MXS 180 bool "MXS NAND support" 181 depends on MX23 || MX28 || MX6 || MX7 182 select SYS_NAND_SELF_INIT 183 imply CMD_NAND 184 select APBH_DMA 185 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 186 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 187 help 188 This enables NAND driver for the NAND flash controller on the 189 MXS processors. 190 191if NAND_MXS 192 193config NAND_MXS_DT 194 bool "Support MXS NAND controller as a DT device" 195 depends on OF_CONTROL && MTD 196 help 197 Enable the driver for MXS NAND flash on platforms using 198 device tree. 199 200config NAND_MXS_USE_MINIMUM_ECC 201 bool "Use minimum ECC strength supported by the controller" 202 default false 203 204endif 205 206config NAND_ZYNQ 207 bool "Support for Zynq Nand controller" 208 select SYS_NAND_SELF_INIT 209 imply CMD_NAND 210 help 211 This enables Nand driver support for Nand flash controller 212 found on Zynq SoC. 213 214config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 215 bool "Enable use of 1st stage bootloader timing for NAND" 216 depends on NAND_ZYNQ 217 help 218 This flag prevent U-boot reconfigure NAND flash controller and reuse 219 the NAND timing from 1st stage bootloader. 220 221comment "Generic NAND options" 222 223config SYS_NAND_BLOCK_SIZE 224 hex "NAND chip eraseblock size" 225 depends on ARCH_SUNXI 226 help 227 Number of data bytes in one eraseblock for the NAND chip on the 228 board. This is the multiple of NAND_PAGE_SIZE and the number of 229 pages. 230 231config SYS_NAND_PAGE_SIZE 232 hex "NAND chip page size" 233 depends on ARCH_SUNXI 234 help 235 Number of data bytes in one page for the NAND chip on the 236 board, not including the OOB area. 237 238config SYS_NAND_OOBSIZE 239 hex "NAND chip OOB size" 240 depends on ARCH_SUNXI 241 help 242 Number of bytes in the Out-Of-Band area for the NAND chip on 243 the board. 244 245# Enhance depends when converting drivers to Kconfig which use this config 246# option (mxc_nand, ndfc, omap_gpmc). 247config SYS_NAND_BUSWIDTH_16BIT 248 bool "Use 16-bit NAND interface" 249 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI 250 help 251 Indicates that NAND device has 16-bit wide data-bus. In absence of this 252 config, bus-width of NAND device is assumed to be either 8-bit and later 253 determined by reading ONFI params. 254 Above config is useful when NAND device's bus-width information cannot 255 be determined from on-chip ONFI params, like in following scenarios: 256 - SPL boot does not support reading of ONFI parameters. This is done to 257 keep SPL code foot-print small. 258 - In current U-Boot flow using nand_init(), driver initialization 259 happens in board_nand_init() which is called before any device probe 260 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are 261 not available while configuring controller. So a static CONFIG_NAND_xx 262 is needed to know the device's bus-width in advance. 263 264if SPL 265 266config SYS_NAND_U_BOOT_LOCATIONS 267 bool "Define U-boot binaries locations in NAND" 268 help 269 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. 270 This option should not be enabled when compiling U-boot for boards 271 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h 272 file. 273 274config SYS_NAND_U_BOOT_OFFS 275 hex "Location in NAND to read U-Boot from" 276 default 0x800000 if NAND_SUNXI 277 depends on SYS_NAND_U_BOOT_LOCATIONS 278 help 279 Set the offset from the start of the nand where u-boot should be 280 loaded from. 281 282config SYS_NAND_U_BOOT_OFFS_REDUND 283 hex "Location in NAND to read U-Boot from" 284 default SYS_NAND_U_BOOT_OFFS 285 depends on SYS_NAND_U_BOOT_LOCATIONS 286 help 287 Set the offset from the start of the nand where the redundant u-boot 288 should be loaded from. 289 290config SPL_NAND_AM33XX_BCH 291 bool "Enables SPL-NAND driver which supports ELM based" 292 depends on NAND_OMAP_GPMC && !OMAP34XX 293 default y 294 help 295 Hardware ECC correction. This is useful for platforms which have ELM 296 hardware engine and use NAND boot mode. 297 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 298 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling 299 SPL-NAND driver with software ECC correction support. 300 301config SPL_NAND_DENALI 302 bool "Support Denali NAND controller for SPL" 303 help 304 This is a small implementation of the Denali NAND controller 305 for use on SPL. 306 307config SPL_NAND_SIMPLE 308 bool "Use simple SPL NAND driver" 309 depends on !SPL_NAND_AM33XX_BCH 310 help 311 Support for NAND boot using simple NAND drivers that 312 expose the cmd_ctrl() interface. 313endif 314 315endif # if NAND 316