1 2menuconfig NAND 3 bool "NAND Device Support" 4if NAND 5 6config SYS_NAND_SELF_INIT 7 bool 8 help 9 This option, if enabled, provides more flexible and linux-like 10 NAND initialization process. 11 12config NAND_DENALI 13 bool 14 select SYS_NAND_SELF_INIT 15 imply CMD_NAND 16 17config NAND_DENALI_DT 18 bool "Support Denali NAND controller as a DT device" 19 select NAND_DENALI 20 depends on OF_CONTROL && DM 21 help 22 Enable the driver for NAND flash on platforms using a Denali NAND 23 controller as a DT device. 24 25config NAND_DENALI_SPARE_AREA_SKIP_BYTES 26 int "Number of bytes skipped in OOB area" 27 depends on NAND_DENALI 28 range 0 63 29 help 30 This option specifies the number of bytes to skip from the beginning 31 of OOB area before last ECC sector data starts. This is potentially 32 used to preserve the bad block marker in the OOB area. 33 34config NAND_LPC32XX_SLC 35 bool "Support LPC32XX_SLC controller" 36 help 37 Enable the LPC32XX SLC NAND controller. 38 39config NAND_OMAP_GPMC 40 bool "Support OMAP GPMC NAND controller" 41 depends on ARCH_OMAP2PLUS 42 help 43 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. 44 GPMC controller is used for parallel NAND flash devices, and can 45 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 46 and BCH16 ECC algorithms. 47 48config NAND_OMAP_GPMC_PREFETCH 49 bool "Enable GPMC Prefetch" 50 depends on NAND_OMAP_GPMC 51 default y 52 help 53 On OMAP platforms that use the GPMC controller 54 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that 55 uses the prefetch mode to speed up read operations. 56 57config NAND_OMAP_ELM 58 bool "Enable ELM driver for OMAPxx and AMxx platforms." 59 depends on NAND_OMAP_GPMC && !OMAP34XX 60 help 61 ELM controller is used for ECC error detection (not ECC calculation) 62 of BCH4, BCH8 and BCH16 ECC algorithms. 63 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 64 thus such SoC platforms need to depend on software library for ECC error 65 detection. However ECC calculation on such plaforms would still be 66 done by GPMC controller. 67 68config NAND_VF610_NFC 69 bool "Support for Freescale NFC for VF610" 70 select SYS_NAND_SELF_INIT 71 imply CMD_NAND 72 help 73 Enables support for NAND Flash Controller on some Freescale 74 processors like the VF610, MCF54418 or Kinetis K70. 75 The driver supports a maximum 2k page size. The driver 76 currently does not support hardware ECC. 77 78choice 79 prompt "Hardware ECC strength" 80 depends on NAND_VF610_NFC 81 default SYS_NAND_VF610_NFC_45_ECC_BYTES 82 help 83 Select the ECC strength used in the hardware BCH ECC block. 84 85config SYS_NAND_VF610_NFC_45_ECC_BYTES 86 bool "24-error correction (45 ECC bytes)" 87 88config SYS_NAND_VF610_NFC_60_ECC_BYTES 89 bool "32-error correction (60 ECC bytes)" 90 91endchoice 92 93config NAND_PXA3XX 94 bool "Support for NAND on PXA3xx and Armada 370/XP/38x" 95 select SYS_NAND_SELF_INIT 96 imply CMD_NAND 97 help 98 This enables the driver for the NAND flash device found on 99 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). 100 101config NAND_SUNXI 102 bool "Support for NAND on Allwinner SoCs" 103 default ARCH_SUNXI 104 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I 105 select SYS_NAND_SELF_INIT 106 select SYS_NAND_U_BOOT_LOCATIONS 107 select SPL_NAND_SUPPORT 108 imply CMD_NAND 109 ---help--- 110 Enable support for NAND. This option enables the standard and 111 SPL drivers. 112 The SPL driver only supports reading from the NAND using DMA 113 transfers. 114 115if NAND_SUNXI 116 117config NAND_SUNXI_SPL_ECC_STRENGTH 118 int "Allwinner NAND SPL ECC Strength" 119 default 64 120 121config NAND_SUNXI_SPL_ECC_SIZE 122 int "Allwinner NAND SPL ECC Step Size" 123 default 1024 124 125config NAND_SUNXI_SPL_USABLE_PAGE_SIZE 126 int "Allwinner NAND SPL Usable Page Size" 127 default 1024 128 129endif 130 131config NAND_ARASAN 132 bool "Configure Arasan Nand" 133 select SYS_NAND_SELF_INIT 134 imply CMD_NAND 135 help 136 This enables Nand driver support for Arasan nand flash 137 controller. This uses the hardware ECC for read and 138 write operations. 139 140config NAND_MXC 141 bool "MXC NAND support" 142 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 143 imply CMD_NAND 144 help 145 This enables the NAND driver for the NAND flash controller on the 146 i.MX27 / i.MX31 / i.MX5 rocessors. 147 148config NAND_MXS 149 bool "MXS NAND support" 150 depends on MX23 || MX28 || MX6 || MX7 151 select SYS_NAND_SELF_INIT 152 imply CMD_NAND 153 select APBH_DMA 154 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 155 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 156 help 157 This enables NAND driver for the NAND flash controller on the 158 MXS processors. 159 160if NAND_MXS 161 162config NAND_MXS_DT 163 bool "Support MXS NAND controller as a DT device" 164 depends on OF_CONTROL && MTD 165 help 166 Enable the driver for MXS NAND flash on platforms using 167 device tree. 168 169config NAND_MXS_USE_MINIMUM_ECC 170 bool "Use minimum ECC strength supported by the controller" 171 default false 172 173endif 174 175config NAND_ZYNQ 176 bool "Support for Zynq Nand controller" 177 select SYS_NAND_SELF_INIT 178 imply CMD_NAND 179 help 180 This enables Nand driver support for Nand flash controller 181 found on Zynq SoC. 182 183config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS 184 bool "Enable use of 1st stage bootloader timing for NAND" 185 depends on NAND_ZYNQ 186 help 187 This flag prevent U-boot reconfigure NAND flash controller and reuse 188 the NAND timing from 1st stage bootloader. 189 190comment "Generic NAND options" 191 192config SYS_NAND_BLOCK_SIZE 193 hex "NAND chip eraseblock size" 194 depends on ARCH_SUNXI 195 help 196 Number of data bytes in one eraseblock for the NAND chip on the 197 board. This is the multiple of NAND_PAGE_SIZE and the number of 198 pages. 199 200config SYS_NAND_PAGE_SIZE 201 hex "NAND chip page size" 202 depends on ARCH_SUNXI 203 help 204 Number of data bytes in one page for the NAND chip on the 205 board, not including the OOB area. 206 207config SYS_NAND_OOBSIZE 208 hex "NAND chip OOB size" 209 depends on ARCH_SUNXI 210 help 211 Number of bytes in the Out-Of-Band area for the NAND chip on 212 the board. 213 214# Enhance depends when converting drivers to Kconfig which use this config 215# option (mxc_nand, ndfc, omap_gpmc). 216config SYS_NAND_BUSWIDTH_16BIT 217 bool "Use 16-bit NAND interface" 218 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI 219 help 220 Indicates that NAND device has 16-bit wide data-bus. In absence of this 221 config, bus-width of NAND device is assumed to be either 8-bit and later 222 determined by reading ONFI params. 223 Above config is useful when NAND device's bus-width information cannot 224 be determined from on-chip ONFI params, like in following scenarios: 225 - SPL boot does not support reading of ONFI parameters. This is done to 226 keep SPL code foot-print small. 227 - In current U-Boot flow using nand_init(), driver initialization 228 happens in board_nand_init() which is called before any device probe 229 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are 230 not available while configuring controller. So a static CONFIG_NAND_xx 231 is needed to know the device's bus-width in advance. 232 233if SPL 234 235config SYS_NAND_U_BOOT_LOCATIONS 236 bool "Define U-boot binaries locations in NAND" 237 help 238 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. 239 This option should not be enabled when compiling U-boot for boards 240 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h 241 file. 242 243config SYS_NAND_U_BOOT_OFFS 244 hex "Location in NAND to read U-Boot from" 245 default 0x800000 if NAND_SUNXI 246 depends on SYS_NAND_U_BOOT_LOCATIONS 247 help 248 Set the offset from the start of the nand where u-boot should be 249 loaded from. 250 251config SYS_NAND_U_BOOT_OFFS_REDUND 252 hex "Location in NAND to read U-Boot from" 253 default SYS_NAND_U_BOOT_OFFS 254 depends on SYS_NAND_U_BOOT_LOCATIONS 255 help 256 Set the offset from the start of the nand where the redundant u-boot 257 should be loaded from. 258 259config SPL_NAND_AM33XX_BCH 260 bool "Enables SPL-NAND driver which supports ELM based" 261 depends on NAND_OMAP_GPMC && !OMAP34XX 262 default y 263 help 264 Hardware ECC correction. This is useful for platforms which have ELM 265 hardware engine and use NAND boot mode. 266 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, 267 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling 268 SPL-NAND driver with software ECC correction support. 269 270config SPL_NAND_DENALI 271 bool "Support Denali NAND controller for SPL" 272 help 273 This is a small implementation of the Denali NAND controller 274 for use on SPL. 275 276config SPL_NAND_SIMPLE 277 bool "Use simple SPL NAND driver" 278 depends on !SPL_NAND_AM33XX_BCH 279 help 280 Support for NAND boot using simple NAND drivers that 281 expose the cmd_ctrl() interface. 282endif 283 284endif # if NAND 285