xref: /openbmc/u-boot/drivers/mtd/nand/Kconfig (revision 614539d4)
1
2menuconfig NAND
3	bool "NAND Device Support"
4if NAND
5
6config SYS_NAND_SELF_INIT
7	bool
8	help
9	  This option, if enabled, provides more flexible and linux-like
10	  NAND initialization process.
11
12config NAND_DENALI
13	bool "Support Denali NAND controller"
14	select SYS_NAND_SELF_INIT
15	imply CMD_NAND
16	help
17	  Enable support for the Denali NAND controller.
18
19config NAND_DENALI_DT
20	bool "Support Denali NAND controller as a DT device"
21	depends on NAND_DENALI && OF_CONTROL && DM
22	help
23	  Enable the driver for NAND flash on platforms using a Denali NAND
24	  controller as a DT device.
25
26config NAND_DENALI_SPARE_AREA_SKIP_BYTES
27	int "Number of bytes skipped in OOB area"
28	depends on NAND_DENALI
29	range 0 63
30	help
31	  This option specifies the number of bytes to skip from the beginning
32	  of OOB area before last ECC sector data starts.  This is potentially
33	  used to preserve the bad block marker in the OOB area.
34
35config NAND_OMAP_GPMC
36	bool "Support OMAP GPMC NAND controller"
37	depends on ARCH_OMAP2PLUS
38	help
39	  Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
40	  GPMC controller is used for parallel NAND flash devices, and can
41	  do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
42	  and BCH16 ECC algorithms.
43
44config NAND_OMAP_GPMC_PREFETCH
45	bool "Enable GPMC Prefetch"
46	depends on NAND_OMAP_GPMC
47	default y
48	help
49	  On OMAP platforms that use the GPMC controller
50	  (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
51	  uses the prefetch mode to speed up read operations.
52
53config NAND_OMAP_ELM
54	bool "Enable ELM driver for OMAPxx and AMxx platforms."
55	depends on NAND_OMAP_GPMC && !OMAP34XX
56	help
57	  ELM controller is used for ECC error detection (not ECC calculation)
58	  of BCH4, BCH8 and BCH16 ECC algorithms.
59	  Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
60	  thus such SoC platforms need to depend on software library for ECC error
61	  detection. However ECC calculation on such plaforms would still be
62	  done by GPMC controller.
63
64config NAND_VF610_NFC
65	bool "Support for Freescale NFC for VF610"
66	select SYS_NAND_SELF_INIT
67	imply CMD_NAND
68	help
69	  Enables support for NAND Flash Controller on some Freescale
70	  processors like the VF610, MCF54418 or Kinetis K70.
71	  The driver supports a maximum 2k page size. The driver
72	  currently does not support hardware ECC.
73
74choice
75	prompt "Hardware ECC strength"
76	depends on NAND_VF610_NFC
77	default SYS_NAND_VF610_NFC_45_ECC_BYTES
78	help
79	  Select the ECC strength used in the hardware BCH ECC block.
80
81config SYS_NAND_VF610_NFC_45_ECC_BYTES
82	bool "24-error correction (45 ECC bytes)"
83
84config SYS_NAND_VF610_NFC_60_ECC_BYTES
85	bool "32-error correction (60 ECC bytes)"
86
87endchoice
88
89config NAND_PXA3XX
90	bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
91	select SYS_NAND_SELF_INIT
92	imply CMD_NAND
93	help
94	  This enables the driver for the NAND flash device found on
95	  PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
96
97config NAND_SUNXI
98	bool "Support for NAND on Allwinner SoCs"
99	depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
100	select SYS_NAND_SELF_INIT
101	select SYS_NAND_U_BOOT_LOCATIONS
102	imply CMD_NAND
103	---help---
104	Enable support for NAND. This option enables the standard and
105	SPL drivers.
106	The SPL driver only supports reading from the NAND using DMA
107	transfers.
108
109if NAND_SUNXI
110
111config NAND_SUNXI_SPL_ECC_STRENGTH
112	int "Allwinner NAND SPL ECC Strength"
113	default 64
114
115config NAND_SUNXI_SPL_ECC_SIZE
116	int "Allwinner NAND SPL ECC Step Size"
117	default 1024
118
119config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
120	int "Allwinner NAND SPL Usable Page Size"
121	default 1024
122
123endif
124
125config NAND_ARASAN
126	bool "Configure Arasan Nand"
127	imply CMD_NAND
128	help
129	  This enables Nand driver support for Arasan nand flash
130	  controller. This uses the hardware ECC for read and
131	  write operations.
132
133config NAND_MXC
134	bool "MXC NAND support"
135	depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
136	imply CMD_NAND
137	help
138	  This enables the NAND driver for the NAND flash controller on the
139	  i.MX27 / i.MX31 / i.MX5 rocessors.
140
141config NAND_MXS
142	bool "MXS NAND support"
143	depends on MX6 || MX7
144	imply CMD_NAND
145	help
146	  This enables NAND driver for the NAND flash controller on the
147	  MXS processors.
148
149config NAND_ZYNQ
150	bool "Support for Zynq Nand controller"
151	select SYS_NAND_SELF_INIT
152	imply CMD_NAND
153	help
154	  This enables Nand driver support for Nand flash controller
155	  found on Zynq SoC.
156
157config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
158	bool "Enable use of 1st stage bootloader timing for NAND"
159	depends on NAND_ZYNQ
160	help
161	  This flag prevent U-boot reconfigure NAND flash controller and reuse
162	  the NAND timing from 1st stage bootloader.
163
164comment "Generic NAND options"
165
166# Enhance depends when converting drivers to Kconfig which use this config
167# option (mxc_nand, ndfc, omap_gpmc).
168config SYS_NAND_BUSWIDTH_16BIT
169	bool "Use 16-bit NAND interface"
170	depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
171	help
172	  Indicates that NAND device has 16-bit wide data-bus. In absence of this
173	  config, bus-width of NAND device is assumed to be either 8-bit and later
174	  determined by reading ONFI params.
175	  Above config is useful when NAND device's bus-width information cannot
176	  be determined from on-chip ONFI params, like in following scenarios:
177	  - SPL boot does not support reading of ONFI parameters. This is done to
178	    keep SPL code foot-print small.
179	  - In current U-Boot flow using nand_init(), driver initialization
180	    happens in board_nand_init() which is called before any device probe
181	    (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
182	    not available while configuring controller. So a static CONFIG_NAND_xx
183	    is needed to know the device's bus-width in advance.
184
185if SPL
186
187config SYS_NAND_U_BOOT_LOCATIONS
188	bool "Define U-boot binaries locations in NAND"
189	help
190	Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
191	This option should not be enabled when compiling U-boot for boards
192	defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
193	file.
194
195config SYS_NAND_U_BOOT_OFFS
196	hex "Location in NAND to read U-Boot from"
197	default 0x800000 if NAND_SUNXI
198	depends on SYS_NAND_U_BOOT_LOCATIONS
199	help
200	Set the offset from the start of the nand where u-boot should be
201	loaded from.
202
203config SYS_NAND_U_BOOT_OFFS_REDUND
204	hex "Location in NAND to read U-Boot from"
205	default SYS_NAND_U_BOOT_OFFS
206	depends on SYS_NAND_U_BOOT_LOCATIONS
207	help
208	Set the offset from the start of the nand where the redundant u-boot
209	should be loaded from.
210
211config SPL_NAND_AM33XX_BCH
212	bool "Enables SPL-NAND driver which supports ELM based"
213	depends on NAND_OMAP_GPMC && !OMAP34XX
214	default y
215        help
216	  Hardware ECC correction. This is useful for platforms which have ELM
217	  hardware engine and use NAND boot mode.
218	  Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
219	  so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
220          SPL-NAND driver with software ECC correction support.
221
222config SPL_NAND_DENALI
223	bool "Support Denali NAND controller for SPL"
224	help
225	  This is a small implementation of the Denali NAND controller
226	  for use on SPL.
227
228config SPL_NAND_SIMPLE
229	bool "Use simple SPL NAND driver"
230	depends on !SPL_NAND_AM33XX_BCH
231	help
232	  Support for NAND boot using simple NAND drivers that
233	  expose the cmd_ctrl() interface.
234endif
235
236endif   # if NAND
237