1 /* 2 * (C) Copyright 2007 3 * Michael Schwingen, <michael@schwingen.org> 4 * 5 * based in great part on jedec_probe.c from linux kernel: 6 * (C) 2000 Red Hat. GPL'd. 7 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 */ 28 29 /* The DEBUG define must be before common to enable debugging */ 30 /*#define DEBUG*/ 31 32 #include <common.h> 33 #include <asm/processor.h> 34 #include <asm/io.h> 35 #include <asm/byteorder.h> 36 #include <environment.h> 37 38 #define P_ID_AMD_STD CFI_CMDSET_AMD_LEGACY 39 40 /* AMD */ 41 #define AM29DL800BB 0x22CB 42 #define AM29DL800BT 0x224A 43 44 #define AM29F400BB 0x22AB 45 #define AM29F800BB 0x2258 46 #define AM29F800BT 0x22D6 47 #define AM29LV400BB 0x22BA 48 #define AM29LV400BT 0x22B9 49 #define AM29LV800BB 0x225B 50 #define AM29LV800BT 0x22DA 51 #define AM29LV160DT 0x22C4 52 #define AM29LV160DB 0x2249 53 #define AM29F017D 0x003D 54 #define AM29F016D 0x00AD 55 #define AM29F080 0x00D5 56 #define AM29F040 0x00A4 57 #define AM29LV040B 0x004F 58 #define AM29F032B 0x0041 59 #define AM29F002T 0x00B0 60 61 /* SST */ 62 #define SST39LF800 0x2781 63 #define SST39LF160 0x2782 64 #define SST39VF1601 0x234b 65 #define SST39LF512 0x00D4 66 #define SST39LF010 0x00D5 67 #define SST39LF020 0x00D6 68 #define SST39LF040 0x00D7 69 #define SST39SF010A 0x00B5 70 #define SST39SF020A 0x00B6 71 72 /* STM */ 73 #define STM29F400BB 0x00D6 74 75 /* MXIC */ 76 #define MX29LV040 0x004F 77 78 /* WINBOND */ 79 #define W39L040A 0x00D6 80 81 /* AMIC */ 82 #define A29L040 0x0092 83 84 /* EON */ 85 #define EN29LV040A 0x004F 86 87 /* 88 * Unlock address sets for AMD command sets. 89 * Intel command sets use the MTD_UADDR_UNNECESSARY. 90 * Each identifier, except MTD_UADDR_UNNECESSARY, and 91 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[]. 92 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure 93 * initialization need not require initializing all of the 94 * unlock addresses for all bit widths. 95 */ 96 enum uaddr { 97 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */ 98 MTD_UADDR_0x0555_0x02AA, 99 MTD_UADDR_0x0555_0x0AAA, 100 MTD_UADDR_0x5555_0x2AAA, 101 MTD_UADDR_0x0AAA_0x0555, 102 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */ 103 MTD_UADDR_UNNECESSARY, /* Does not require any address */ 104 }; 105 106 107 struct unlock_addr { 108 u32 addr1; 109 u32 addr2; 110 }; 111 112 113 /* 114 * I don't like the fact that the first entry in unlock_addrs[] 115 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore, 116 * should not be used. The problem is that structures with 117 * initializers have extra fields initialized to 0. It is _very_ 118 * desireable to have the unlock address entries for unsupported 119 * data widths automatically initialized - that means that 120 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here 121 * must go unused. 122 */ 123 static const struct unlock_addr unlock_addrs[] = { 124 [MTD_UADDR_NOT_SUPPORTED] = { 125 .addr1 = 0xffff, 126 .addr2 = 0xffff 127 }, 128 129 [MTD_UADDR_0x0555_0x02AA] = { 130 .addr1 = 0x0555, 131 .addr2 = 0x02aa 132 }, 133 134 [MTD_UADDR_0x0555_0x0AAA] = { 135 .addr1 = 0x0555, 136 .addr2 = 0x0aaa 137 }, 138 139 [MTD_UADDR_0x5555_0x2AAA] = { 140 .addr1 = 0x5555, 141 .addr2 = 0x2aaa 142 }, 143 144 [MTD_UADDR_0x0AAA_0x0555] = { 145 .addr1 = 0x0AAA, 146 .addr2 = 0x0555 147 }, 148 149 [MTD_UADDR_DONT_CARE] = { 150 .addr1 = 0x0000, /* Doesn't matter which address */ 151 .addr2 = 0x0000 /* is used - must be last entry */ 152 }, 153 154 [MTD_UADDR_UNNECESSARY] = { 155 .addr1 = 0x0000, 156 .addr2 = 0x0000 157 } 158 }; 159 160 161 struct amd_flash_info { 162 const __u16 mfr_id; 163 const __u16 dev_id; 164 const char *name; 165 const int DevSize; 166 const int NumEraseRegions; 167 const int CmdSet; 168 const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */ 169 const ulong regions[6]; 170 }; 171 172 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1) 173 174 #define SIZE_64KiB 16 175 #define SIZE_128KiB 17 176 #define SIZE_256KiB 18 177 #define SIZE_512KiB 19 178 #define SIZE_1MiB 20 179 #define SIZE_2MiB 21 180 #define SIZE_4MiB 22 181 #define SIZE_8MiB 23 182 183 static const struct amd_flash_info jedec_table[] = { 184 #ifdef CONFIG_SYS_FLASH_LEGACY_256Kx8 185 { 186 .mfr_id = (u16)SST_MANUFACT, 187 .dev_id = SST39LF020, 188 .name = "SST 39LF020", 189 .uaddr = { 190 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 191 }, 192 .DevSize = SIZE_256KiB, 193 .CmdSet = P_ID_AMD_STD, 194 .NumEraseRegions= 1, 195 .regions = { 196 ERASEINFO(0x01000,64), 197 } 198 }, 199 #endif 200 #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx8 201 { 202 .mfr_id = (u16)AMD_MANUFACT, 203 .dev_id = AM29LV040B, 204 .name = "AMD AM29LV040B", 205 .uaddr = { 206 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 207 }, 208 .DevSize = SIZE_512KiB, 209 .CmdSet = P_ID_AMD_STD, 210 .NumEraseRegions= 1, 211 .regions = { 212 ERASEINFO(0x10000,8), 213 } 214 }, 215 { 216 .mfr_id = (u16)SST_MANUFACT, 217 .dev_id = SST39LF040, 218 .name = "SST 39LF040", 219 .uaddr = { 220 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 221 }, 222 .DevSize = SIZE_512KiB, 223 .CmdSet = P_ID_AMD_STD, 224 .NumEraseRegions= 1, 225 .regions = { 226 ERASEINFO(0x01000,128), 227 } 228 }, 229 { 230 .mfr_id = (u16)STM_MANUFACT, 231 .dev_id = STM_ID_M29W040B, 232 .name = "ST Micro M29W040B", 233 .uaddr = { 234 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 235 }, 236 .DevSize = SIZE_512KiB, 237 .CmdSet = P_ID_AMD_STD, 238 .NumEraseRegions= 1, 239 .regions = { 240 ERASEINFO(0x10000,8), 241 } 242 }, 243 { 244 .mfr_id = (u16)MX_MANUFACT, 245 .dev_id = MX29LV040, 246 .name = "MXIC MX29LV040", 247 .uaddr = { 248 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 249 }, 250 .DevSize = SIZE_512KiB, 251 .CmdSet = P_ID_AMD_STD, 252 .NumEraseRegions= 1, 253 .regions = { 254 ERASEINFO(0x10000, 8), 255 } 256 }, 257 { 258 .mfr_id = (u16)WINB_MANUFACT, 259 .dev_id = W39L040A, 260 .name = "WINBOND W39L040A", 261 .uaddr = { 262 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ 263 }, 264 .DevSize = SIZE_512KiB, 265 .CmdSet = P_ID_AMD_STD, 266 .NumEraseRegions= 1, 267 .regions = { 268 ERASEINFO(0x10000, 8), 269 } 270 }, 271 { 272 .mfr_id = (u16)AMIC_MANUFACT, 273 .dev_id = A29L040, 274 .name = "AMIC A29L040", 275 .uaddr = { 276 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 277 }, 278 .DevSize = SIZE_512KiB, 279 .CmdSet = P_ID_AMD_STD, 280 .NumEraseRegions= 1, 281 .regions = { 282 ERASEINFO(0x10000, 8), 283 } 284 }, 285 { 286 .mfr_id = (u16)EON_MANUFACT, 287 .dev_id = EN29LV040A, 288 .name = "EON EN29LV040A", 289 .uaddr = { 290 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ 291 }, 292 .DevSize = SIZE_512KiB, 293 .CmdSet = P_ID_AMD_STD, 294 .NumEraseRegions= 1, 295 .regions = { 296 ERASEINFO(0x10000, 8), 297 } 298 }, 299 #endif 300 #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16 301 { 302 .mfr_id = (u16)AMD_MANUFACT, 303 .dev_id = AM29F400BB, 304 .name = "AMD AM29F400BB", 305 .uaddr = { 306 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ 307 }, 308 .DevSize = SIZE_512KiB, 309 .CmdSet = CFI_CMDSET_AMD_LEGACY, 310 .NumEraseRegions= 4, 311 .regions = { 312 ERASEINFO(0x04000, 1), 313 ERASEINFO(0x02000, 2), 314 ERASEINFO(0x08000, 1), 315 ERASEINFO(0x10000, 7), 316 } 317 }, 318 { 319 .mfr_id = (u16)AMD_MANUFACT, 320 .dev_id = AM29LV400BB, 321 .name = "AMD AM29LV400BB", 322 .uaddr = { 323 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ 324 }, 325 .DevSize = SIZE_512KiB, 326 .CmdSet = CFI_CMDSET_AMD_LEGACY, 327 .NumEraseRegions= 4, 328 .regions = { 329 ERASEINFO(0x04000,1), 330 ERASEINFO(0x02000,2), 331 ERASEINFO(0x08000,1), 332 ERASEINFO(0x10000,7), 333 } 334 }, 335 { 336 .mfr_id = (u16)AMD_MANUFACT, 337 .dev_id = AM29LV800BB, 338 .name = "AMD AM29LV800BB", 339 .uaddr = { 340 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ 341 }, 342 .DevSize = SIZE_1MiB, 343 .CmdSet = CFI_CMDSET_AMD_LEGACY, 344 .NumEraseRegions= 4, 345 .regions = { 346 ERASEINFO(0x04000, 1), 347 ERASEINFO(0x02000, 2), 348 ERASEINFO(0x08000, 1), 349 ERASEINFO(0x10000, 15), 350 } 351 }, 352 { 353 .mfr_id = (u16)STM_MANUFACT, 354 .dev_id = STM29F400BB, 355 .name = "ST Micro M29F400BB", 356 .uaddr = { 357 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */ 358 }, 359 .DevSize = SIZE_512KiB, 360 .CmdSet = CFI_CMDSET_AMD_LEGACY, 361 .NumEraseRegions = 4, 362 .regions = { 363 ERASEINFO(0x04000, 1), 364 ERASEINFO(0x02000, 2), 365 ERASEINFO(0x08000, 1), 366 ERASEINFO(0x10000, 7), 367 } 368 }, 369 #endif 370 }; 371 372 static inline void fill_info(flash_info_t *info, const struct amd_flash_info *jedec_entry, ulong base) 373 { 374 int i,j; 375 int sect_cnt; 376 int size_ratio; 377 int total_size; 378 enum uaddr uaddr_idx; 379 380 size_ratio = info->portwidth / info->chipwidth; 381 382 debug("Found JEDEC Flash: %s\n", jedec_entry->name); 383 info->vendor = jedec_entry->CmdSet; 384 /* Todo: do we need device-specific timeouts? */ 385 info->erase_blk_tout = 30000; 386 info->buffer_write_tout = 1000; 387 info->write_tout = 100; 388 info->name = jedec_entry->name; 389 390 /* copy unlock addresses from device table to CFI info struct. This 391 is just here because the addresses are in the table anyway - if 392 the flash is not detected due to wrong unlock addresses, 393 flash_detect_legacy would have to try all of them before we even 394 get here. */ 395 switch(info->chipwidth) { 396 case FLASH_CFI_8BIT: 397 uaddr_idx = jedec_entry->uaddr[0]; 398 break; 399 case FLASH_CFI_16BIT: 400 uaddr_idx = jedec_entry->uaddr[1]; 401 break; 402 case FLASH_CFI_32BIT: 403 uaddr_idx = jedec_entry->uaddr[2]; 404 break; 405 default: 406 uaddr_idx = MTD_UADDR_NOT_SUPPORTED; 407 break; 408 } 409 410 debug("unlock address index %d\n", uaddr_idx); 411 info->addr_unlock1 = unlock_addrs[uaddr_idx].addr1; 412 info->addr_unlock2 = unlock_addrs[uaddr_idx].addr2; 413 debug("unlock addresses are 0x%lx/0x%lx\n", 414 info->addr_unlock1, info->addr_unlock2); 415 416 sect_cnt = 0; 417 total_size = 0; 418 for (i = 0; i < jedec_entry->NumEraseRegions; i++) { 419 ulong erase_region_size = jedec_entry->regions[i] >> 8; 420 ulong erase_region_count = (jedec_entry->regions[i] & 0xff) + 1; 421 422 total_size += erase_region_size * erase_region_count; 423 debug("erase_region_count = %ld erase_region_size = %ld\n", 424 erase_region_count, erase_region_size); 425 for (j = 0; j < erase_region_count; j++) { 426 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { 427 printf("ERROR: too many flash sectors\n"); 428 break; 429 } 430 info->start[sect_cnt] = base; 431 base += (erase_region_size * size_ratio); 432 sect_cnt++; 433 } 434 } 435 info->sector_count = sect_cnt; 436 info->size = total_size * size_ratio; 437 } 438 439 /*----------------------------------------------------------------------- 440 * match jedec ids against table. If a match is found, fill flash_info entry 441 */ 442 int jedec_flash_match(flash_info_t *info, ulong base) 443 { 444 int ret = 0; 445 int i; 446 ulong mask = 0xFFFF; 447 if (info->chipwidth == 1) 448 mask = 0xFF; 449 450 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) { 451 if ((jedec_table[i].mfr_id & mask) == (info->manufacturer_id & mask) && 452 (jedec_table[i].dev_id & mask) == (info->device_id & mask)) { 453 fill_info(info, &jedec_table[i], base); 454 ret = 1; 455 break; 456 } 457 } 458 return ret; 459 } 460