1 /* 2 * (C) Copyright 2002-2004 3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com 4 * 5 * Copyright (C) 2003 Arabella Software Ltd. 6 * Yuli Barcohen <yuli@arabellasw.com> 7 * 8 * Copyright (C) 2004 9 * Ed Okerson 10 * 11 * Copyright (C) 2006 12 * Tolunay Orkun <listmember@orkun.us> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 /* The DEBUG define must be before common to enable debugging */ 18 /* #define DEBUG */ 19 20 #include <common.h> 21 #include <console.h> 22 #include <dm.h> 23 #include <errno.h> 24 #include <fdt_support.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include <asm/byteorder.h> 28 #include <asm/unaligned.h> 29 #include <environment.h> 30 #include <mtd/cfi_flash.h> 31 #include <watchdog.h> 32 33 /* 34 * This file implements a Common Flash Interface (CFI) driver for 35 * U-Boot. 36 * 37 * The width of the port and the width of the chips are determined at 38 * initialization. These widths are used to calculate the address for 39 * access CFI data structures. 40 * 41 * References 42 * JEDEC Standard JESD68 - Common Flash Interface (CFI) 43 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes 44 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets 45 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet 46 * AMD CFI Specification, Release 2.0 December 1, 2001 47 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte 48 * Device IDs, Publication Number 25538 Revision A, November 8, 2001 49 * 50 * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between 51 * reading and writing ... (yes there is such a Hardware). 52 */ 53 54 DECLARE_GLOBAL_DATA_PTR; 55 56 static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; 57 #ifdef CONFIG_FLASH_CFI_MTD 58 static uint flash_verbose = 1; 59 #else 60 #define flash_verbose 1 61 #endif 62 63 flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ 64 65 /* 66 * Check if chip width is defined. If not, start detecting with 8bit. 67 */ 68 #ifndef CONFIG_SYS_FLASH_CFI_WIDTH 69 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 70 #endif 71 72 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 73 #define __maybe_weak __weak 74 #else 75 #define __maybe_weak static 76 #endif 77 78 /* 79 * 0xffff is an undefined value for the configuration register. When 80 * this value is returned, the configuration register shall not be 81 * written at all (default mode). 82 */ 83 static u16 cfi_flash_config_reg(int i) 84 { 85 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS 86 return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i]; 87 #else 88 return 0xffff; 89 #endif 90 } 91 92 #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) 93 int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; 94 #endif 95 96 #ifdef CONFIG_CFI_FLASH /* for driver model */ 97 static void cfi_flash_init_dm(void) 98 { 99 struct udevice *dev; 100 101 cfi_flash_num_flash_banks = 0; 102 /* 103 * The uclass_first_device() will probe the first device and 104 * uclass_next_device() will probe the rest if they exist. So 105 * that cfi_flash_probe() will get called assigning the base 106 * addresses that are available. 107 */ 108 for (uclass_first_device(UCLASS_MTD, &dev); 109 dev; 110 uclass_next_device(&dev)) { 111 } 112 } 113 114 static phys_addr_t cfi_flash_base[CFI_MAX_FLASH_BANKS]; 115 116 phys_addr_t cfi_flash_bank_addr(int i) 117 { 118 return cfi_flash_base[i]; 119 } 120 #else 121 __weak phys_addr_t cfi_flash_bank_addr(int i) 122 { 123 return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; 124 } 125 #endif 126 127 __weak unsigned long cfi_flash_bank_size(int i) 128 { 129 #ifdef CONFIG_SYS_FLASH_BANKS_SIZES 130 return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; 131 #else 132 return 0; 133 #endif 134 } 135 136 __maybe_weak void flash_write8(u8 value, void *addr) 137 { 138 __raw_writeb(value, addr); 139 } 140 141 __maybe_weak void flash_write16(u16 value, void *addr) 142 { 143 __raw_writew(value, addr); 144 } 145 146 __maybe_weak void flash_write32(u32 value, void *addr) 147 { 148 __raw_writel(value, addr); 149 } 150 151 __maybe_weak void flash_write64(u64 value, void *addr) 152 { 153 /* No architectures currently implement __raw_writeq() */ 154 *(volatile u64 *)addr = value; 155 } 156 157 __maybe_weak u8 flash_read8(void *addr) 158 { 159 return __raw_readb(addr); 160 } 161 162 __maybe_weak u16 flash_read16(void *addr) 163 { 164 return __raw_readw(addr); 165 } 166 167 __maybe_weak u32 flash_read32(void *addr) 168 { 169 return __raw_readl(addr); 170 } 171 172 __maybe_weak u64 flash_read64(void *addr) 173 { 174 /* No architectures currently implement __raw_readq() */ 175 return *(volatile u64 *)addr; 176 } 177 178 /*----------------------------------------------------------------------- 179 */ 180 #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) 181 flash_info_t *flash_get_info(ulong base) 182 { 183 int i; 184 flash_info_t *info; 185 186 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { 187 info = &flash_info[i]; 188 if (info->size && info->start[0] <= base && 189 base <= info->start[0] + info->size - 1) 190 return info; 191 } 192 193 return NULL; 194 } 195 #endif 196 197 unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) 198 { 199 if (sect != (info->sector_count - 1)) 200 return info->start[sect + 1] - info->start[sect]; 201 else 202 return info->start[0] + info->size - info->start[sect]; 203 } 204 205 /*----------------------------------------------------------------------- 206 * create an address based on the offset and the port width 207 */ 208 static inline void * 209 flash_map (flash_info_t * info, flash_sect_t sect, uint offset) 210 { 211 unsigned int byte_offset = offset * info->portwidth; 212 213 return (void *)(info->start[sect] + byte_offset); 214 } 215 216 static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, 217 unsigned int offset, void *addr) 218 { 219 } 220 221 /*----------------------------------------------------------------------- 222 * make a proper sized command based on the port and chip widths 223 */ 224 static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) 225 { 226 int i; 227 int cword_offset; 228 int cp_offset; 229 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 230 u32 cmd_le = cpu_to_le32(cmd); 231 #endif 232 uchar val; 233 uchar *cp = (uchar *) cmdbuf; 234 235 for (i = info->portwidth; i > 0; i--){ 236 cword_offset = (info->portwidth-i)%info->chipwidth; 237 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 238 cp_offset = info->portwidth - i; 239 val = *((uchar*)&cmd_le + cword_offset); 240 #else 241 cp_offset = i - 1; 242 val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1); 243 #endif 244 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val; 245 } 246 } 247 248 #ifdef DEBUG 249 /*----------------------------------------------------------------------- 250 * Debug support 251 */ 252 static void print_longlong (char *str, unsigned long long data) 253 { 254 int i; 255 char *cp; 256 257 cp = (char *) &data; 258 for (i = 0; i < 8; i++) 259 sprintf (&str[i * 2], "%2.2x", *cp++); 260 } 261 262 static void flash_printqry (struct cfi_qry *qry) 263 { 264 u8 *p = (u8 *)qry; 265 int x, y; 266 267 for (x = 0; x < sizeof(struct cfi_qry); x += 16) { 268 debug("%02x : ", x); 269 for (y = 0; y < 16; y++) 270 debug("%2.2x ", p[x + y]); 271 debug(" "); 272 for (y = 0; y < 16; y++) { 273 unsigned char c = p[x + y]; 274 if (c >= 0x20 && c <= 0x7e) 275 debug("%c", c); 276 else 277 debug("."); 278 } 279 debug("\n"); 280 } 281 } 282 #endif 283 284 285 /*----------------------------------------------------------------------- 286 * read a character at a port width address 287 */ 288 static inline uchar flash_read_uchar (flash_info_t * info, uint offset) 289 { 290 uchar *cp; 291 uchar retval; 292 293 cp = flash_map (info, 0, offset); 294 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 295 retval = flash_read8(cp); 296 #else 297 retval = flash_read8(cp + info->portwidth - 1); 298 #endif 299 flash_unmap (info, 0, offset, cp); 300 return retval; 301 } 302 303 /*----------------------------------------------------------------------- 304 * read a word at a port width address, assume 16bit bus 305 */ 306 static inline ushort flash_read_word (flash_info_t * info, uint offset) 307 { 308 ushort *addr, retval; 309 310 addr = flash_map (info, 0, offset); 311 retval = flash_read16 (addr); 312 flash_unmap (info, 0, offset, addr); 313 return retval; 314 } 315 316 317 /*----------------------------------------------------------------------- 318 * read a long word by picking the least significant byte of each maximum 319 * port size word. Swap for ppc format. 320 */ 321 static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, 322 uint offset) 323 { 324 uchar *addr; 325 ulong retval; 326 327 #ifdef DEBUG 328 int x; 329 #endif 330 addr = flash_map (info, sect, offset); 331 332 #ifdef DEBUG 333 debug ("long addr is at %p info->portwidth = %d\n", addr, 334 info->portwidth); 335 for (x = 0; x < 4 * info->portwidth; x++) { 336 debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); 337 } 338 #endif 339 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 340 retval = ((flash_read8(addr) << 16) | 341 (flash_read8(addr + info->portwidth) << 24) | 342 (flash_read8(addr + 2 * info->portwidth)) | 343 (flash_read8(addr + 3 * info->portwidth) << 8)); 344 #else 345 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | 346 (flash_read8(addr + info->portwidth - 1) << 16) | 347 (flash_read8(addr + 4 * info->portwidth - 1) << 8) | 348 (flash_read8(addr + 3 * info->portwidth - 1))); 349 #endif 350 flash_unmap(info, sect, offset, addr); 351 352 return retval; 353 } 354 355 /* 356 * Write a proper sized command to the correct address 357 */ 358 void flash_write_cmd (flash_info_t * info, flash_sect_t sect, 359 uint offset, u32 cmd) 360 { 361 362 void *addr; 363 cfiword_t cword; 364 365 addr = flash_map (info, sect, offset); 366 flash_make_cmd (info, cmd, &cword); 367 switch (info->portwidth) { 368 case FLASH_CFI_8BIT: 369 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, 370 cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 371 flash_write8(cword.w8, addr); 372 break; 373 case FLASH_CFI_16BIT: 374 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, 375 cmd, cword.w16, 376 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 377 flash_write16(cword.w16, addr); 378 break; 379 case FLASH_CFI_32BIT: 380 debug ("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr, 381 cmd, cword.w32, 382 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 383 flash_write32(cword.w32, addr); 384 break; 385 case FLASH_CFI_64BIT: 386 #ifdef DEBUG 387 { 388 char str[20]; 389 390 print_longlong (str, cword.w64); 391 392 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", 393 addr, cmd, str, 394 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 395 } 396 #endif 397 flash_write64(cword.w64, addr); 398 break; 399 } 400 401 /* Ensure all the instructions are fully finished */ 402 sync(); 403 404 flash_unmap(info, sect, offset, addr); 405 } 406 407 static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) 408 { 409 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); 410 flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); 411 } 412 413 /*----------------------------------------------------------------------- 414 */ 415 static int flash_isequal (flash_info_t * info, flash_sect_t sect, 416 uint offset, uchar cmd) 417 { 418 void *addr; 419 cfiword_t cword; 420 int retval; 421 422 addr = flash_map (info, sect, offset); 423 flash_make_cmd (info, cmd, &cword); 424 425 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); 426 switch (info->portwidth) { 427 case FLASH_CFI_8BIT: 428 debug ("is= %x %x\n", flash_read8(addr), cword.w8); 429 retval = (flash_read8(addr) == cword.w8); 430 break; 431 case FLASH_CFI_16BIT: 432 debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16); 433 retval = (flash_read16(addr) == cword.w16); 434 break; 435 case FLASH_CFI_32BIT: 436 debug ("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32); 437 retval = (flash_read32(addr) == cword.w32); 438 break; 439 case FLASH_CFI_64BIT: 440 #ifdef DEBUG 441 { 442 char str1[20]; 443 char str2[20]; 444 445 print_longlong (str1, flash_read64(addr)); 446 print_longlong (str2, cword.w64); 447 debug ("is= %s %s\n", str1, str2); 448 } 449 #endif 450 retval = (flash_read64(addr) == cword.w64); 451 break; 452 default: 453 retval = 0; 454 break; 455 } 456 flash_unmap(info, sect, offset, addr); 457 458 return retval; 459 } 460 461 /*----------------------------------------------------------------------- 462 */ 463 static int flash_isset (flash_info_t * info, flash_sect_t sect, 464 uint offset, uchar cmd) 465 { 466 void *addr; 467 cfiword_t cword; 468 int retval; 469 470 addr = flash_map (info, sect, offset); 471 flash_make_cmd (info, cmd, &cword); 472 switch (info->portwidth) { 473 case FLASH_CFI_8BIT: 474 retval = ((flash_read8(addr) & cword.w8) == cword.w8); 475 break; 476 case FLASH_CFI_16BIT: 477 retval = ((flash_read16(addr) & cword.w16) == cword.w16); 478 break; 479 case FLASH_CFI_32BIT: 480 retval = ((flash_read32(addr) & cword.w32) == cword.w32); 481 break; 482 case FLASH_CFI_64BIT: 483 retval = ((flash_read64(addr) & cword.w64) == cword.w64); 484 break; 485 default: 486 retval = 0; 487 break; 488 } 489 flash_unmap(info, sect, offset, addr); 490 491 return retval; 492 } 493 494 /*----------------------------------------------------------------------- 495 */ 496 static int flash_toggle (flash_info_t * info, flash_sect_t sect, 497 uint offset, uchar cmd) 498 { 499 void *addr; 500 cfiword_t cword; 501 int retval; 502 503 addr = flash_map (info, sect, offset); 504 flash_make_cmd (info, cmd, &cword); 505 switch (info->portwidth) { 506 case FLASH_CFI_8BIT: 507 retval = flash_read8(addr) != flash_read8(addr); 508 break; 509 case FLASH_CFI_16BIT: 510 retval = flash_read16(addr) != flash_read16(addr); 511 break; 512 case FLASH_CFI_32BIT: 513 retval = flash_read32(addr) != flash_read32(addr); 514 break; 515 case FLASH_CFI_64BIT: 516 retval = ( (flash_read32( addr ) != flash_read32( addr )) || 517 (flash_read32(addr+4) != flash_read32(addr+4)) ); 518 break; 519 default: 520 retval = 0; 521 break; 522 } 523 flash_unmap(info, sect, offset, addr); 524 525 return retval; 526 } 527 528 /* 529 * flash_is_busy - check to see if the flash is busy 530 * 531 * This routine checks the status of the chip and returns true if the 532 * chip is busy. 533 */ 534 static int flash_is_busy (flash_info_t * info, flash_sect_t sect) 535 { 536 int retval; 537 538 switch (info->vendor) { 539 case CFI_CMDSET_INTEL_PROG_REGIONS: 540 case CFI_CMDSET_INTEL_STANDARD: 541 case CFI_CMDSET_INTEL_EXTENDED: 542 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); 543 break; 544 case CFI_CMDSET_AMD_STANDARD: 545 case CFI_CMDSET_AMD_EXTENDED: 546 #ifdef CONFIG_FLASH_CFI_LEGACY 547 case CFI_CMDSET_AMD_LEGACY: 548 #endif 549 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); 550 break; 551 default: 552 retval = 0; 553 } 554 debug ("flash_is_busy: %d\n", retval); 555 return retval; 556 } 557 558 /*----------------------------------------------------------------------- 559 * wait for XSR.7 to be set. Time out with an error if it does not. 560 * This routine does not set the flash to read-array mode. 561 */ 562 static int flash_status_check (flash_info_t * info, flash_sect_t sector, 563 ulong tout, char *prompt) 564 { 565 ulong start; 566 567 #if CONFIG_SYS_HZ != 1000 568 if ((ulong)CONFIG_SYS_HZ > 100000) 569 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ 570 else 571 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); 572 #endif 573 574 /* Wait for command completion */ 575 #ifdef CONFIG_SYS_LOW_RES_TIMER 576 reset_timer(); 577 #endif 578 start = get_timer (0); 579 WATCHDOG_RESET(); 580 while (flash_is_busy (info, sector)) { 581 if (get_timer (start) > tout) { 582 printf ("Flash %s timeout at address %lx data %lx\n", 583 prompt, info->start[sector], 584 flash_read_long (info, sector, 0)); 585 flash_write_cmd (info, sector, 0, info->cmd_reset); 586 udelay(1); 587 return ERR_TIMOUT; 588 } 589 udelay (1); /* also triggers watchdog */ 590 } 591 return ERR_OK; 592 } 593 594 /*----------------------------------------------------------------------- 595 * Wait for XSR.7 to be set, if it times out print an error, otherwise 596 * do a full status check. 597 * 598 * This routine sets the flash to read-array mode. 599 */ 600 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, 601 ulong tout, char *prompt) 602 { 603 int retcode; 604 605 retcode = flash_status_check (info, sector, tout, prompt); 606 switch (info->vendor) { 607 case CFI_CMDSET_INTEL_PROG_REGIONS: 608 case CFI_CMDSET_INTEL_EXTENDED: 609 case CFI_CMDSET_INTEL_STANDARD: 610 if ((retcode == ERR_OK) 611 && !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { 612 retcode = ERR_INVAL; 613 printf ("Flash %s error at address %lx\n", prompt, 614 info->start[sector]); 615 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | 616 FLASH_STATUS_PSLBS)) { 617 puts ("Command Sequence Error.\n"); 618 } else if (flash_isset (info, sector, 0, 619 FLASH_STATUS_ECLBS)) { 620 puts ("Block Erase Error.\n"); 621 retcode = ERR_NOT_ERASED; 622 } else if (flash_isset (info, sector, 0, 623 FLASH_STATUS_PSLBS)) { 624 puts ("Locking Error\n"); 625 } 626 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { 627 puts ("Block locked.\n"); 628 retcode = ERR_PROTECTED; 629 } 630 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) 631 puts ("Vpp Low Error.\n"); 632 } 633 flash_write_cmd (info, sector, 0, info->cmd_reset); 634 udelay(1); 635 break; 636 default: 637 break; 638 } 639 return retcode; 640 } 641 642 static int use_flash_status_poll(flash_info_t *info) 643 { 644 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL 645 if (info->vendor == CFI_CMDSET_AMD_EXTENDED || 646 info->vendor == CFI_CMDSET_AMD_STANDARD) 647 return 1; 648 #endif 649 return 0; 650 } 651 652 static int flash_status_poll(flash_info_t *info, void *src, void *dst, 653 ulong tout, char *prompt) 654 { 655 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL 656 ulong start; 657 int ready; 658 659 #if CONFIG_SYS_HZ != 1000 660 if ((ulong)CONFIG_SYS_HZ > 100000) 661 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ 662 else 663 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); 664 #endif 665 666 /* Wait for command completion */ 667 #ifdef CONFIG_SYS_LOW_RES_TIMER 668 reset_timer(); 669 #endif 670 start = get_timer(0); 671 WATCHDOG_RESET(); 672 while (1) { 673 switch (info->portwidth) { 674 case FLASH_CFI_8BIT: 675 ready = flash_read8(dst) == flash_read8(src); 676 break; 677 case FLASH_CFI_16BIT: 678 ready = flash_read16(dst) == flash_read16(src); 679 break; 680 case FLASH_CFI_32BIT: 681 ready = flash_read32(dst) == flash_read32(src); 682 break; 683 case FLASH_CFI_64BIT: 684 ready = flash_read64(dst) == flash_read64(src); 685 break; 686 default: 687 ready = 0; 688 break; 689 } 690 if (ready) 691 break; 692 if (get_timer(start) > tout) { 693 printf("Flash %s timeout at address %lx data %lx\n", 694 prompt, (ulong)dst, (ulong)flash_read8(dst)); 695 return ERR_TIMOUT; 696 } 697 udelay(1); /* also triggers watchdog */ 698 } 699 #endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */ 700 return ERR_OK; 701 } 702 703 /*----------------------------------------------------------------------- 704 */ 705 static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) 706 { 707 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 708 unsigned short w; 709 unsigned int l; 710 unsigned long long ll; 711 #endif 712 713 switch (info->portwidth) { 714 case FLASH_CFI_8BIT: 715 cword->w8 = c; 716 break; 717 case FLASH_CFI_16BIT: 718 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 719 w = c; 720 w <<= 8; 721 cword->w16 = (cword->w16 >> 8) | w; 722 #else 723 cword->w16 = (cword->w16 << 8) | c; 724 #endif 725 break; 726 case FLASH_CFI_32BIT: 727 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 728 l = c; 729 l <<= 24; 730 cword->w32 = (cword->w32 >> 8) | l; 731 #else 732 cword->w32 = (cword->w32 << 8) | c; 733 #endif 734 break; 735 case FLASH_CFI_64BIT: 736 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 737 ll = c; 738 ll <<= 56; 739 cword->w64 = (cword->w64 >> 8) | ll; 740 #else 741 cword->w64 = (cword->w64 << 8) | c; 742 #endif 743 break; 744 } 745 } 746 747 /* 748 * Loop through the sector table starting from the previously found sector. 749 * Searches forwards or backwards, dependent on the passed address. 750 */ 751 static flash_sect_t find_sector (flash_info_t * info, ulong addr) 752 { 753 static flash_sect_t saved_sector; /* previously found sector */ 754 static flash_info_t *saved_info; /* previously used flash bank */ 755 flash_sect_t sector = saved_sector; 756 757 if ((info != saved_info) || (sector >= info->sector_count)) 758 sector = 0; 759 760 while ((info->start[sector] < addr) 761 && (sector < info->sector_count - 1)) 762 sector++; 763 while ((info->start[sector] > addr) && (sector > 0)) 764 /* 765 * also decrements the sector in case of an overshot 766 * in the first loop 767 */ 768 sector--; 769 770 saved_sector = sector; 771 saved_info = info; 772 return sector; 773 } 774 775 /*----------------------------------------------------------------------- 776 */ 777 static int flash_write_cfiword (flash_info_t * info, ulong dest, 778 cfiword_t cword) 779 { 780 void *dstaddr = (void *)dest; 781 int flag; 782 flash_sect_t sect = 0; 783 char sect_found = 0; 784 785 /* Check if Flash is (sufficiently) erased */ 786 switch (info->portwidth) { 787 case FLASH_CFI_8BIT: 788 flag = ((flash_read8(dstaddr) & cword.w8) == cword.w8); 789 break; 790 case FLASH_CFI_16BIT: 791 flag = ((flash_read16(dstaddr) & cword.w16) == cword.w16); 792 break; 793 case FLASH_CFI_32BIT: 794 flag = ((flash_read32(dstaddr) & cword.w32) == cword.w32); 795 break; 796 case FLASH_CFI_64BIT: 797 flag = ((flash_read64(dstaddr) & cword.w64) == cword.w64); 798 break; 799 default: 800 flag = 0; 801 break; 802 } 803 if (!flag) 804 return ERR_NOT_ERASED; 805 806 /* Disable interrupts which might cause a timeout here */ 807 flag = disable_interrupts (); 808 809 switch (info->vendor) { 810 case CFI_CMDSET_INTEL_PROG_REGIONS: 811 case CFI_CMDSET_INTEL_EXTENDED: 812 case CFI_CMDSET_INTEL_STANDARD: 813 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); 814 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); 815 break; 816 case CFI_CMDSET_AMD_EXTENDED: 817 case CFI_CMDSET_AMD_STANDARD: 818 sect = find_sector(info, dest); 819 flash_unlock_seq (info, sect); 820 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE); 821 sect_found = 1; 822 break; 823 #ifdef CONFIG_FLASH_CFI_LEGACY 824 case CFI_CMDSET_AMD_LEGACY: 825 sect = find_sector(info, dest); 826 flash_unlock_seq (info, 0); 827 flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE); 828 sect_found = 1; 829 break; 830 #endif 831 } 832 833 switch (info->portwidth) { 834 case FLASH_CFI_8BIT: 835 flash_write8(cword.w8, dstaddr); 836 break; 837 case FLASH_CFI_16BIT: 838 flash_write16(cword.w16, dstaddr); 839 break; 840 case FLASH_CFI_32BIT: 841 flash_write32(cword.w32, dstaddr); 842 break; 843 case FLASH_CFI_64BIT: 844 flash_write64(cword.w64, dstaddr); 845 break; 846 } 847 848 /* re-enable interrupts if necessary */ 849 if (flag) 850 enable_interrupts (); 851 852 if (!sect_found) 853 sect = find_sector (info, dest); 854 855 if (use_flash_status_poll(info)) 856 return flash_status_poll(info, &cword, dstaddr, 857 info->write_tout, "write"); 858 else 859 return flash_full_status_check(info, sect, 860 info->write_tout, "write"); 861 } 862 863 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 864 865 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, 866 int len) 867 { 868 flash_sect_t sector; 869 int cnt; 870 int retcode; 871 void *src = cp; 872 void *dst = (void *)dest; 873 void *dst2 = dst; 874 int flag = 1; 875 uint offset = 0; 876 unsigned int shift; 877 uchar write_cmd; 878 879 switch (info->portwidth) { 880 case FLASH_CFI_8BIT: 881 shift = 0; 882 break; 883 case FLASH_CFI_16BIT: 884 shift = 1; 885 break; 886 case FLASH_CFI_32BIT: 887 shift = 2; 888 break; 889 case FLASH_CFI_64BIT: 890 shift = 3; 891 break; 892 default: 893 retcode = ERR_INVAL; 894 goto out_unmap; 895 } 896 897 cnt = len >> shift; 898 899 while ((cnt-- > 0) && (flag == 1)) { 900 switch (info->portwidth) { 901 case FLASH_CFI_8BIT: 902 flag = ((flash_read8(dst2) & flash_read8(src)) == 903 flash_read8(src)); 904 src += 1, dst2 += 1; 905 break; 906 case FLASH_CFI_16BIT: 907 flag = ((flash_read16(dst2) & flash_read16(src)) == 908 flash_read16(src)); 909 src += 2, dst2 += 2; 910 break; 911 case FLASH_CFI_32BIT: 912 flag = ((flash_read32(dst2) & flash_read32(src)) == 913 flash_read32(src)); 914 src += 4, dst2 += 4; 915 break; 916 case FLASH_CFI_64BIT: 917 flag = ((flash_read64(dst2) & flash_read64(src)) == 918 flash_read64(src)); 919 src += 8, dst2 += 8; 920 break; 921 } 922 } 923 if (!flag) { 924 retcode = ERR_NOT_ERASED; 925 goto out_unmap; 926 } 927 928 src = cp; 929 sector = find_sector (info, dest); 930 931 switch (info->vendor) { 932 case CFI_CMDSET_INTEL_PROG_REGIONS: 933 case CFI_CMDSET_INTEL_STANDARD: 934 case CFI_CMDSET_INTEL_EXTENDED: 935 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? 936 FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER; 937 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); 938 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS); 939 flash_write_cmd (info, sector, 0, write_cmd); 940 retcode = flash_status_check (info, sector, 941 info->buffer_write_tout, 942 "write to buffer"); 943 if (retcode == ERR_OK) { 944 /* reduce the number of loops by the width of 945 * the port */ 946 cnt = len >> shift; 947 flash_write_cmd (info, sector, 0, cnt - 1); 948 while (cnt-- > 0) { 949 switch (info->portwidth) { 950 case FLASH_CFI_8BIT: 951 flash_write8(flash_read8(src), dst); 952 src += 1, dst += 1; 953 break; 954 case FLASH_CFI_16BIT: 955 flash_write16(flash_read16(src), dst); 956 src += 2, dst += 2; 957 break; 958 case FLASH_CFI_32BIT: 959 flash_write32(flash_read32(src), dst); 960 src += 4, dst += 4; 961 break; 962 case FLASH_CFI_64BIT: 963 flash_write64(flash_read64(src), dst); 964 src += 8, dst += 8; 965 break; 966 default: 967 retcode = ERR_INVAL; 968 goto out_unmap; 969 } 970 } 971 flash_write_cmd (info, sector, 0, 972 FLASH_CMD_WRITE_BUFFER_CONFIRM); 973 retcode = flash_full_status_check ( 974 info, sector, info->buffer_write_tout, 975 "buffer write"); 976 } 977 978 break; 979 980 case CFI_CMDSET_AMD_STANDARD: 981 case CFI_CMDSET_AMD_EXTENDED: 982 flash_unlock_seq(info, sector); 983 984 #ifdef CONFIG_FLASH_SPANSION_S29WS_N 985 offset = ((unsigned long)dst - info->start[sector]) >> shift; 986 #endif 987 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); 988 cnt = len >> shift; 989 flash_write_cmd(info, sector, offset, cnt - 1); 990 991 switch (info->portwidth) { 992 case FLASH_CFI_8BIT: 993 while (cnt-- > 0) { 994 flash_write8(flash_read8(src), dst); 995 src += 1, dst += 1; 996 } 997 break; 998 case FLASH_CFI_16BIT: 999 while (cnt-- > 0) { 1000 flash_write16(flash_read16(src), dst); 1001 src += 2, dst += 2; 1002 } 1003 break; 1004 case FLASH_CFI_32BIT: 1005 while (cnt-- > 0) { 1006 flash_write32(flash_read32(src), dst); 1007 src += 4, dst += 4; 1008 } 1009 break; 1010 case FLASH_CFI_64BIT: 1011 while (cnt-- > 0) { 1012 flash_write64(flash_read64(src), dst); 1013 src += 8, dst += 8; 1014 } 1015 break; 1016 default: 1017 retcode = ERR_INVAL; 1018 goto out_unmap; 1019 } 1020 1021 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); 1022 if (use_flash_status_poll(info)) 1023 retcode = flash_status_poll(info, src - (1 << shift), 1024 dst - (1 << shift), 1025 info->buffer_write_tout, 1026 "buffer write"); 1027 else 1028 retcode = flash_full_status_check(info, sector, 1029 info->buffer_write_tout, 1030 "buffer write"); 1031 break; 1032 1033 default: 1034 debug ("Unknown Command Set\n"); 1035 retcode = ERR_INVAL; 1036 break; 1037 } 1038 1039 out_unmap: 1040 return retcode; 1041 } 1042 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 1043 1044 1045 /*----------------------------------------------------------------------- 1046 */ 1047 int flash_erase (flash_info_t * info, int s_first, int s_last) 1048 { 1049 int rcode = 0; 1050 int prot; 1051 flash_sect_t sect; 1052 int st; 1053 1054 if (info->flash_id != FLASH_MAN_CFI) { 1055 puts ("Can't erase unknown flash type - aborted\n"); 1056 return 1; 1057 } 1058 if ((s_first < 0) || (s_first > s_last)) { 1059 puts ("- no sectors to erase\n"); 1060 return 1; 1061 } 1062 1063 prot = 0; 1064 for (sect = s_first; sect <= s_last; ++sect) { 1065 if (info->protect[sect]) { 1066 prot++; 1067 } 1068 } 1069 if (prot) { 1070 printf ("- Warning: %d protected sectors will not be erased!\n", 1071 prot); 1072 } else if (flash_verbose) { 1073 putc ('\n'); 1074 } 1075 1076 1077 for (sect = s_first; sect <= s_last; sect++) { 1078 if (ctrlc()) { 1079 printf("\n"); 1080 return 1; 1081 } 1082 1083 if (info->protect[sect] == 0) { /* not protected */ 1084 #ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE 1085 int k; 1086 int size; 1087 int erased; 1088 u32 *flash; 1089 1090 /* 1091 * Check if whole sector is erased 1092 */ 1093 size = flash_sector_size(info, sect); 1094 erased = 1; 1095 flash = (u32 *)info->start[sect]; 1096 /* divide by 4 for longword access */ 1097 size = size >> 2; 1098 for (k = 0; k < size; k++) { 1099 if (flash_read32(flash++) != 0xffffffff) { 1100 erased = 0; 1101 break; 1102 } 1103 } 1104 if (erased) { 1105 if (flash_verbose) 1106 putc(','); 1107 continue; 1108 } 1109 #endif 1110 switch (info->vendor) { 1111 case CFI_CMDSET_INTEL_PROG_REGIONS: 1112 case CFI_CMDSET_INTEL_STANDARD: 1113 case CFI_CMDSET_INTEL_EXTENDED: 1114 flash_write_cmd (info, sect, 0, 1115 FLASH_CMD_CLEAR_STATUS); 1116 flash_write_cmd (info, sect, 0, 1117 FLASH_CMD_BLOCK_ERASE); 1118 flash_write_cmd (info, sect, 0, 1119 FLASH_CMD_ERASE_CONFIRM); 1120 break; 1121 case CFI_CMDSET_AMD_STANDARD: 1122 case CFI_CMDSET_AMD_EXTENDED: 1123 flash_unlock_seq (info, sect); 1124 flash_write_cmd (info, sect, 1125 info->addr_unlock1, 1126 AMD_CMD_ERASE_START); 1127 flash_unlock_seq (info, sect); 1128 flash_write_cmd (info, sect, 0, 1129 info->cmd_erase_sector); 1130 break; 1131 #ifdef CONFIG_FLASH_CFI_LEGACY 1132 case CFI_CMDSET_AMD_LEGACY: 1133 flash_unlock_seq (info, 0); 1134 flash_write_cmd (info, 0, info->addr_unlock1, 1135 AMD_CMD_ERASE_START); 1136 flash_unlock_seq (info, 0); 1137 flash_write_cmd (info, sect, 0, 1138 AMD_CMD_ERASE_SECTOR); 1139 break; 1140 #endif 1141 default: 1142 debug ("Unkown flash vendor %d\n", 1143 info->vendor); 1144 break; 1145 } 1146 1147 if (use_flash_status_poll(info)) { 1148 cfiword_t cword; 1149 void *dest; 1150 cword.w64 = 0xffffffffffffffffULL; 1151 dest = flash_map(info, sect, 0); 1152 st = flash_status_poll(info, &cword, dest, 1153 info->erase_blk_tout, "erase"); 1154 flash_unmap(info, sect, 0, dest); 1155 } else 1156 st = flash_full_status_check(info, sect, 1157 info->erase_blk_tout, 1158 "erase"); 1159 if (st) 1160 rcode = 1; 1161 else if (flash_verbose) 1162 putc ('.'); 1163 } 1164 } 1165 1166 if (flash_verbose) 1167 puts (" done\n"); 1168 1169 return rcode; 1170 } 1171 1172 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 1173 static int sector_erased(flash_info_t *info, int i) 1174 { 1175 int k; 1176 int size; 1177 u32 *flash; 1178 1179 /* 1180 * Check if whole sector is erased 1181 */ 1182 size = flash_sector_size(info, i); 1183 flash = (u32 *)info->start[i]; 1184 /* divide by 4 for longword access */ 1185 size = size >> 2; 1186 1187 for (k = 0; k < size; k++) { 1188 if (flash_read32(flash++) != 0xffffffff) 1189 return 0; /* not erased */ 1190 } 1191 1192 return 1; /* erased */ 1193 } 1194 #endif /* CONFIG_SYS_FLASH_EMPTY_INFO */ 1195 1196 void flash_print_info (flash_info_t * info) 1197 { 1198 int i; 1199 1200 if (info->flash_id != FLASH_MAN_CFI) { 1201 puts ("missing or unknown FLASH type\n"); 1202 return; 1203 } 1204 1205 printf ("%s flash (%d x %d)", 1206 info->name, 1207 (info->portwidth << 3), (info->chipwidth << 3)); 1208 if (info->size < 1024*1024) 1209 printf (" Size: %ld kB in %d Sectors\n", 1210 info->size >> 10, info->sector_count); 1211 else 1212 printf (" Size: %ld MB in %d Sectors\n", 1213 info->size >> 20, info->sector_count); 1214 printf (" "); 1215 switch (info->vendor) { 1216 case CFI_CMDSET_INTEL_PROG_REGIONS: 1217 printf ("Intel Prog Regions"); 1218 break; 1219 case CFI_CMDSET_INTEL_STANDARD: 1220 printf ("Intel Standard"); 1221 break; 1222 case CFI_CMDSET_INTEL_EXTENDED: 1223 printf ("Intel Extended"); 1224 break; 1225 case CFI_CMDSET_AMD_STANDARD: 1226 printf ("AMD Standard"); 1227 break; 1228 case CFI_CMDSET_AMD_EXTENDED: 1229 printf ("AMD Extended"); 1230 break; 1231 #ifdef CONFIG_FLASH_CFI_LEGACY 1232 case CFI_CMDSET_AMD_LEGACY: 1233 printf ("AMD Legacy"); 1234 break; 1235 #endif 1236 default: 1237 printf ("Unknown (%d)", info->vendor); 1238 break; 1239 } 1240 printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x", 1241 info->manufacturer_id); 1242 printf (info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", 1243 info->device_id); 1244 if ((info->device_id & 0xff) == 0x7E) { 1245 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", 1246 info->device_id2); 1247 } 1248 if ((info->vendor == CFI_CMDSET_AMD_STANDARD) && (info->legacy_unlock)) 1249 printf("\n Advanced Sector Protection (PPB) enabled"); 1250 printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", 1251 info->erase_blk_tout, 1252 info->write_tout); 1253 if (info->buffer_size > 1) { 1254 printf (" Buffer write timeout: %ld ms, " 1255 "buffer size: %d bytes\n", 1256 info->buffer_write_tout, 1257 info->buffer_size); 1258 } 1259 1260 puts ("\n Sector Start Addresses:"); 1261 for (i = 0; i < info->sector_count; ++i) { 1262 if (ctrlc()) 1263 break; 1264 if ((i % 5) == 0) 1265 putc('\n'); 1266 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 1267 /* print empty and read-only info */ 1268 printf (" %08lX %c %s ", 1269 info->start[i], 1270 sector_erased(info, i) ? 'E' : ' ', 1271 info->protect[i] ? "RO" : " "); 1272 #else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */ 1273 printf (" %08lX %s ", 1274 info->start[i], 1275 info->protect[i] ? "RO" : " "); 1276 #endif 1277 } 1278 putc ('\n'); 1279 return; 1280 } 1281 1282 /*----------------------------------------------------------------------- 1283 * This is used in a few places in write_buf() to show programming 1284 * progress. Making it a function is nasty because it needs to do side 1285 * effect updates to digit and dots. Repeated code is nasty too, so 1286 * we define it once here. 1287 */ 1288 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1289 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ 1290 if (flash_verbose) { \ 1291 dots -= dots_sub; \ 1292 if ((scale > 0) && (dots <= 0)) { \ 1293 if ((digit % 5) == 0) \ 1294 printf ("%d", digit / 5); \ 1295 else \ 1296 putc ('.'); \ 1297 digit--; \ 1298 dots += scale; \ 1299 } \ 1300 } 1301 #else 1302 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) 1303 #endif 1304 1305 /*----------------------------------------------------------------------- 1306 * Copy memory to flash, returns: 1307 * 0 - OK 1308 * 1 - write timeout 1309 * 2 - Flash not erased 1310 */ 1311 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) 1312 { 1313 ulong wp; 1314 uchar *p; 1315 int aln; 1316 cfiword_t cword; 1317 int i, rc; 1318 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1319 int buffered_size; 1320 #endif 1321 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1322 int digit = CONFIG_FLASH_SHOW_PROGRESS; 1323 int scale = 0; 1324 int dots = 0; 1325 1326 /* 1327 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. 1328 */ 1329 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { 1330 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / 1331 CONFIG_FLASH_SHOW_PROGRESS); 1332 } 1333 #endif 1334 1335 /* get lower aligned address */ 1336 wp = (addr & ~(info->portwidth - 1)); 1337 1338 /* handle unaligned start */ 1339 if ((aln = addr - wp) != 0) { 1340 cword.w32 = 0; 1341 p = (uchar *)wp; 1342 for (i = 0; i < aln; ++i) 1343 flash_add_byte (info, &cword, flash_read8(p + i)); 1344 1345 for (; (i < info->portwidth) && (cnt > 0); i++) { 1346 flash_add_byte (info, &cword, *src++); 1347 cnt--; 1348 } 1349 for (; (cnt == 0) && (i < info->portwidth); ++i) 1350 flash_add_byte (info, &cword, flash_read8(p + i)); 1351 1352 rc = flash_write_cfiword (info, wp, cword); 1353 if (rc != 0) 1354 return rc; 1355 1356 wp += i; 1357 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1358 } 1359 1360 /* handle the aligned part */ 1361 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1362 buffered_size = (info->portwidth / info->chipwidth); 1363 buffered_size *= info->buffer_size; 1364 while (cnt >= info->portwidth) { 1365 /* prohibit buffer write when buffer_size is 1 */ 1366 if (info->buffer_size == 1) { 1367 cword.w32 = 0; 1368 for (i = 0; i < info->portwidth; i++) 1369 flash_add_byte (info, &cword, *src++); 1370 if ((rc = flash_write_cfiword (info, wp, cword)) != 0) 1371 return rc; 1372 wp += info->portwidth; 1373 cnt -= info->portwidth; 1374 continue; 1375 } 1376 1377 /* write buffer until next buffered_size aligned boundary */ 1378 i = buffered_size - (wp % buffered_size); 1379 if (i > cnt) 1380 i = cnt; 1381 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) 1382 return rc; 1383 i -= i & (info->portwidth - 1); 1384 wp += i; 1385 src += i; 1386 cnt -= i; 1387 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1388 /* Only check every once in a while */ 1389 if ((cnt & 0xFFFF) < buffered_size && ctrlc()) 1390 return ERR_ABORTED; 1391 } 1392 #else 1393 while (cnt >= info->portwidth) { 1394 cword.w32 = 0; 1395 for (i = 0; i < info->portwidth; i++) { 1396 flash_add_byte (info, &cword, *src++); 1397 } 1398 if ((rc = flash_write_cfiword (info, wp, cword)) != 0) 1399 return rc; 1400 wp += info->portwidth; 1401 cnt -= info->portwidth; 1402 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); 1403 /* Only check every once in a while */ 1404 if ((cnt & 0xFFFF) < info->portwidth && ctrlc()) 1405 return ERR_ABORTED; 1406 } 1407 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 1408 1409 if (cnt == 0) { 1410 return (0); 1411 } 1412 1413 /* 1414 * handle unaligned tail bytes 1415 */ 1416 cword.w32 = 0; 1417 p = (uchar *)wp; 1418 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { 1419 flash_add_byte (info, &cword, *src++); 1420 --cnt; 1421 } 1422 for (; i < info->portwidth; ++i) 1423 flash_add_byte (info, &cword, flash_read8(p + i)); 1424 1425 return flash_write_cfiword (info, wp, cword); 1426 } 1427 1428 static inline int manufact_match(flash_info_t *info, u32 manu) 1429 { 1430 return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16); 1431 } 1432 1433 /*----------------------------------------------------------------------- 1434 */ 1435 #ifdef CONFIG_SYS_FLASH_PROTECTION 1436 1437 static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot) 1438 { 1439 if (manufact_match(info, INTEL_MANUFACT) 1440 && info->device_id == NUMONYX_256MBIT) { 1441 /* 1442 * see errata called 1443 * "Numonyx Axcell P33/P30 Specification Update" :) 1444 */ 1445 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_ID); 1446 if (!flash_isequal(info, sector, FLASH_OFFSET_PROTECT, 1447 prot)) { 1448 /* 1449 * cmd must come before FLASH_CMD_PROTECT + 20us 1450 * Disable interrupts which might cause a timeout here. 1451 */ 1452 int flag = disable_interrupts(); 1453 unsigned short cmd; 1454 1455 if (prot) 1456 cmd = FLASH_CMD_PROTECT_SET; 1457 else 1458 cmd = FLASH_CMD_PROTECT_CLEAR; 1459 1460 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); 1461 flash_write_cmd(info, sector, 0, cmd); 1462 /* re-enable interrupts if necessary */ 1463 if (flag) 1464 enable_interrupts(); 1465 } 1466 return 1; 1467 } 1468 return 0; 1469 } 1470 1471 int flash_real_protect (flash_info_t * info, long sector, int prot) 1472 { 1473 int retcode = 0; 1474 1475 switch (info->vendor) { 1476 case CFI_CMDSET_INTEL_PROG_REGIONS: 1477 case CFI_CMDSET_INTEL_STANDARD: 1478 case CFI_CMDSET_INTEL_EXTENDED: 1479 if (!cfi_protect_bugfix(info, sector, prot)) { 1480 flash_write_cmd(info, sector, 0, 1481 FLASH_CMD_CLEAR_STATUS); 1482 flash_write_cmd(info, sector, 0, 1483 FLASH_CMD_PROTECT); 1484 if (prot) 1485 flash_write_cmd(info, sector, 0, 1486 FLASH_CMD_PROTECT_SET); 1487 else 1488 flash_write_cmd(info, sector, 0, 1489 FLASH_CMD_PROTECT_CLEAR); 1490 1491 } 1492 break; 1493 case CFI_CMDSET_AMD_EXTENDED: 1494 case CFI_CMDSET_AMD_STANDARD: 1495 /* U-Boot only checks the first byte */ 1496 if (manufact_match(info, ATM_MANUFACT)) { 1497 if (prot) { 1498 flash_unlock_seq (info, 0); 1499 flash_write_cmd (info, 0, 1500 info->addr_unlock1, 1501 ATM_CMD_SOFTLOCK_START); 1502 flash_unlock_seq (info, 0); 1503 flash_write_cmd (info, sector, 0, 1504 ATM_CMD_LOCK_SECT); 1505 } else { 1506 flash_write_cmd (info, 0, 1507 info->addr_unlock1, 1508 AMD_CMD_UNLOCK_START); 1509 if (info->device_id == ATM_ID_BV6416) 1510 flash_write_cmd (info, sector, 1511 0, ATM_CMD_UNLOCK_SECT); 1512 } 1513 } 1514 if (info->legacy_unlock) { 1515 int flag = disable_interrupts(); 1516 int lock_flag; 1517 1518 flash_unlock_seq(info, 0); 1519 flash_write_cmd(info, 0, info->addr_unlock1, 1520 AMD_CMD_SET_PPB_ENTRY); 1521 lock_flag = flash_isset(info, sector, 0, 0x01); 1522 if (prot) { 1523 if (lock_flag) { 1524 flash_write_cmd(info, sector, 0, 1525 AMD_CMD_PPB_LOCK_BC1); 1526 flash_write_cmd(info, sector, 0, 1527 AMD_CMD_PPB_LOCK_BC2); 1528 } 1529 debug("sector %ld %slocked\n", sector, 1530 lock_flag ? "" : "already "); 1531 } else { 1532 if (!lock_flag) { 1533 debug("unlock %ld\n", sector); 1534 flash_write_cmd(info, 0, 0, 1535 AMD_CMD_PPB_UNLOCK_BC1); 1536 flash_write_cmd(info, 0, 0, 1537 AMD_CMD_PPB_UNLOCK_BC2); 1538 } 1539 debug("sector %ld %sunlocked\n", sector, 1540 !lock_flag ? "" : "already "); 1541 } 1542 if (flag) 1543 enable_interrupts(); 1544 1545 if (flash_status_check(info, sector, 1546 info->erase_blk_tout, 1547 prot ? "protect" : "unprotect")) 1548 printf("status check error\n"); 1549 1550 flash_write_cmd(info, 0, 0, 1551 AMD_CMD_SET_PPB_EXIT_BC1); 1552 flash_write_cmd(info, 0, 0, 1553 AMD_CMD_SET_PPB_EXIT_BC2); 1554 } 1555 break; 1556 #ifdef CONFIG_FLASH_CFI_LEGACY 1557 case CFI_CMDSET_AMD_LEGACY: 1558 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); 1559 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); 1560 if (prot) 1561 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); 1562 else 1563 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); 1564 #endif 1565 }; 1566 1567 /* 1568 * Flash needs to be in status register read mode for 1569 * flash_full_status_check() to work correctly 1570 */ 1571 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); 1572 if ((retcode = 1573 flash_full_status_check (info, sector, info->erase_blk_tout, 1574 prot ? "protect" : "unprotect")) == 0) { 1575 1576 info->protect[sector] = prot; 1577 1578 /* 1579 * On some of Intel's flash chips (marked via legacy_unlock) 1580 * unprotect unprotects all locking. 1581 */ 1582 if ((prot == 0) && (info->legacy_unlock)) { 1583 flash_sect_t i; 1584 1585 for (i = 0; i < info->sector_count; i++) { 1586 if (info->protect[i]) 1587 flash_real_protect (info, i, 1); 1588 } 1589 } 1590 } 1591 return retcode; 1592 } 1593 1594 /*----------------------------------------------------------------------- 1595 * flash_read_user_serial - read the OneTimeProgramming cells 1596 */ 1597 void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, 1598 int len) 1599 { 1600 uchar *src; 1601 uchar *dst; 1602 1603 dst = buffer; 1604 src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION); 1605 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); 1606 memcpy (dst, src + offset, len); 1607 flash_write_cmd (info, 0, 0, info->cmd_reset); 1608 udelay(1); 1609 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); 1610 } 1611 1612 /* 1613 * flash_read_factory_serial - read the device Id from the protection area 1614 */ 1615 void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, 1616 int len) 1617 { 1618 uchar *src; 1619 1620 src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION); 1621 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); 1622 memcpy (buffer, src + offset, len); 1623 flash_write_cmd (info, 0, 0, info->cmd_reset); 1624 udelay(1); 1625 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); 1626 } 1627 1628 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 1629 1630 /*----------------------------------------------------------------------- 1631 * Reverse the order of the erase regions in the CFI QRY structure. 1632 * This is needed for chips that are either a) correctly detected as 1633 * top-boot, or b) buggy. 1634 */ 1635 static void cfi_reverse_geometry(struct cfi_qry *qry) 1636 { 1637 unsigned int i, j; 1638 u32 tmp; 1639 1640 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { 1641 tmp = get_unaligned(&(qry->erase_region_info[i])); 1642 put_unaligned(get_unaligned(&(qry->erase_region_info[j])), 1643 &(qry->erase_region_info[i])); 1644 put_unaligned(tmp, &(qry->erase_region_info[j])); 1645 } 1646 } 1647 1648 /*----------------------------------------------------------------------- 1649 * read jedec ids from device and set corresponding fields in info struct 1650 * 1651 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct 1652 * 1653 */ 1654 static void cmdset_intel_read_jedec_ids(flash_info_t *info) 1655 { 1656 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1657 udelay(1); 1658 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1659 udelay(1000); /* some flash are slow to respond */ 1660 info->manufacturer_id = flash_read_uchar (info, 1661 FLASH_OFFSET_MANUFACTURER_ID); 1662 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ? 1663 flash_read_word (info, FLASH_OFFSET_DEVICE_ID) : 1664 flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID); 1665 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1666 } 1667 1668 static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) 1669 { 1670 info->cmd_reset = FLASH_CMD_RESET; 1671 1672 cmdset_intel_read_jedec_ids(info); 1673 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1674 1675 #ifdef CONFIG_SYS_FLASH_PROTECTION 1676 /* read legacy lock/unlock bit from intel flash */ 1677 if (info->ext_addr) { 1678 info->legacy_unlock = flash_read_uchar (info, 1679 info->ext_addr + 5) & 0x08; 1680 } 1681 #endif 1682 1683 return 0; 1684 } 1685 1686 static void cmdset_amd_read_jedec_ids(flash_info_t *info) 1687 { 1688 ushort bankId = 0; 1689 uchar manuId; 1690 1691 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1692 flash_unlock_seq(info, 0); 1693 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); 1694 udelay(1000); /* some flash are slow to respond */ 1695 1696 manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID); 1697 /* JEDEC JEP106Z specifies ID codes up to bank 7 */ 1698 while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { 1699 bankId += 0x100; 1700 manuId = flash_read_uchar (info, 1701 bankId | FLASH_OFFSET_MANUFACTURER_ID); 1702 } 1703 info->manufacturer_id = manuId; 1704 1705 switch (info->chipwidth){ 1706 case FLASH_CFI_8BIT: 1707 info->device_id = flash_read_uchar (info, 1708 FLASH_OFFSET_DEVICE_ID); 1709 if (info->device_id == 0x7E) { 1710 /* AMD 3-byte (expanded) device ids */ 1711 info->device_id2 = flash_read_uchar (info, 1712 FLASH_OFFSET_DEVICE_ID2); 1713 info->device_id2 <<= 8; 1714 info->device_id2 |= flash_read_uchar (info, 1715 FLASH_OFFSET_DEVICE_ID3); 1716 } 1717 break; 1718 case FLASH_CFI_16BIT: 1719 info->device_id = flash_read_word (info, 1720 FLASH_OFFSET_DEVICE_ID); 1721 if ((info->device_id & 0xff) == 0x7E) { 1722 /* AMD 3-byte (expanded) device ids */ 1723 info->device_id2 = flash_read_uchar (info, 1724 FLASH_OFFSET_DEVICE_ID2); 1725 info->device_id2 <<= 8; 1726 info->device_id2 |= flash_read_uchar (info, 1727 FLASH_OFFSET_DEVICE_ID3); 1728 } 1729 break; 1730 default: 1731 break; 1732 } 1733 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1734 udelay(1); 1735 } 1736 1737 static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) 1738 { 1739 info->cmd_reset = AMD_CMD_RESET; 1740 info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR; 1741 1742 cmdset_amd_read_jedec_ids(info); 1743 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1744 1745 #ifdef CONFIG_SYS_FLASH_PROTECTION 1746 if (info->ext_addr) { 1747 /* read sector protect/unprotect scheme (at 0x49) */ 1748 if (flash_read_uchar(info, info->ext_addr + 9) == 0x8) 1749 info->legacy_unlock = 1; 1750 } 1751 #endif 1752 1753 return 0; 1754 } 1755 1756 #ifdef CONFIG_FLASH_CFI_LEGACY 1757 static void flash_read_jedec_ids (flash_info_t * info) 1758 { 1759 info->manufacturer_id = 0; 1760 info->device_id = 0; 1761 info->device_id2 = 0; 1762 1763 switch (info->vendor) { 1764 case CFI_CMDSET_INTEL_PROG_REGIONS: 1765 case CFI_CMDSET_INTEL_STANDARD: 1766 case CFI_CMDSET_INTEL_EXTENDED: 1767 cmdset_intel_read_jedec_ids(info); 1768 break; 1769 case CFI_CMDSET_AMD_STANDARD: 1770 case CFI_CMDSET_AMD_EXTENDED: 1771 cmdset_amd_read_jedec_ids(info); 1772 break; 1773 default: 1774 break; 1775 } 1776 } 1777 1778 /*----------------------------------------------------------------------- 1779 * Call board code to request info about non-CFI flash. 1780 * board_flash_get_legacy needs to fill in at least: 1781 * info->portwidth, info->chipwidth and info->interface for Jedec probing. 1782 */ 1783 static int flash_detect_legacy(phys_addr_t base, int banknum) 1784 { 1785 flash_info_t *info = &flash_info[banknum]; 1786 1787 if (board_flash_get_legacy(base, banknum, info)) { 1788 /* board code may have filled info completely. If not, we 1789 use JEDEC ID probing. */ 1790 if (!info->vendor) { 1791 int modes[] = { 1792 CFI_CMDSET_AMD_STANDARD, 1793 CFI_CMDSET_INTEL_STANDARD 1794 }; 1795 int i; 1796 1797 for (i = 0; i < ARRAY_SIZE(modes); i++) { 1798 info->vendor = modes[i]; 1799 info->start[0] = 1800 (ulong)map_physmem(base, 1801 info->portwidth, 1802 MAP_NOCACHE); 1803 if (info->portwidth == FLASH_CFI_8BIT 1804 && info->interface == FLASH_CFI_X8X16) { 1805 info->addr_unlock1 = 0x2AAA; 1806 info->addr_unlock2 = 0x5555; 1807 } else { 1808 info->addr_unlock1 = 0x5555; 1809 info->addr_unlock2 = 0x2AAA; 1810 } 1811 flash_read_jedec_ids(info); 1812 debug("JEDEC PROBE: ID %x %x %x\n", 1813 info->manufacturer_id, 1814 info->device_id, 1815 info->device_id2); 1816 if (jedec_flash_match(info, info->start[0])) 1817 break; 1818 else 1819 unmap_physmem((void *)info->start[0], 1820 info->portwidth); 1821 } 1822 } 1823 1824 switch(info->vendor) { 1825 case CFI_CMDSET_INTEL_PROG_REGIONS: 1826 case CFI_CMDSET_INTEL_STANDARD: 1827 case CFI_CMDSET_INTEL_EXTENDED: 1828 info->cmd_reset = FLASH_CMD_RESET; 1829 break; 1830 case CFI_CMDSET_AMD_STANDARD: 1831 case CFI_CMDSET_AMD_EXTENDED: 1832 case CFI_CMDSET_AMD_LEGACY: 1833 info->cmd_reset = AMD_CMD_RESET; 1834 break; 1835 } 1836 info->flash_id = FLASH_MAN_CFI; 1837 return 1; 1838 } 1839 return 0; /* use CFI */ 1840 } 1841 #else 1842 static inline int flash_detect_legacy(phys_addr_t base, int banknum) 1843 { 1844 return 0; /* use CFI */ 1845 } 1846 #endif 1847 1848 /*----------------------------------------------------------------------- 1849 * detect if flash is compatible with the Common Flash Interface (CFI) 1850 * http://www.jedec.org/download/search/jesd68.pdf 1851 */ 1852 static void flash_read_cfi (flash_info_t *info, void *buf, 1853 unsigned int start, size_t len) 1854 { 1855 u8 *p = buf; 1856 unsigned int i; 1857 1858 for (i = 0; i < len; i++) 1859 p[i] = flash_read_uchar(info, start + i); 1860 } 1861 1862 static void __flash_cmd_reset(flash_info_t *info) 1863 { 1864 /* 1865 * We do not yet know what kind of commandset to use, so we issue 1866 * the reset command in both Intel and AMD variants, in the hope 1867 * that AMD flash roms ignore the Intel command. 1868 */ 1869 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1870 udelay(1); 1871 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1872 } 1873 void flash_cmd_reset(flash_info_t *info) 1874 __attribute__((weak,alias("__flash_cmd_reset"))); 1875 1876 static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) 1877 { 1878 int cfi_offset; 1879 1880 /* Issue FLASH reset command */ 1881 flash_cmd_reset(info); 1882 1883 for (cfi_offset = 0; cfi_offset < ARRAY_SIZE(flash_offset_cfi); 1884 cfi_offset++) { 1885 flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], 1886 FLASH_CMD_CFI); 1887 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') 1888 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') 1889 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { 1890 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, 1891 sizeof(struct cfi_qry)); 1892 info->interface = le16_to_cpu(qry->interface_desc); 1893 1894 info->cfi_offset = flash_offset_cfi[cfi_offset]; 1895 debug ("device interface is %d\n", 1896 info->interface); 1897 debug ("found port %d chip %d ", 1898 info->portwidth, info->chipwidth); 1899 debug ("port %d bits chip %d bits\n", 1900 info->portwidth << CFI_FLASH_SHIFT_WIDTH, 1901 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 1902 1903 /* calculate command offsets as in the Linux driver */ 1904 info->addr_unlock1 = 0x555; 1905 info->addr_unlock2 = 0x2aa; 1906 1907 /* 1908 * modify the unlock address if we are 1909 * in compatibility mode 1910 */ 1911 if ( /* x8/x16 in x8 mode */ 1912 ((info->chipwidth == FLASH_CFI_BY8) && 1913 (info->interface == FLASH_CFI_X8X16)) || 1914 /* x16/x32 in x16 mode */ 1915 ((info->chipwidth == FLASH_CFI_BY16) && 1916 (info->interface == FLASH_CFI_X16X32))) 1917 { 1918 info->addr_unlock1 = 0xaaa; 1919 info->addr_unlock2 = 0x555; 1920 } 1921 1922 info->name = "CFI conformant"; 1923 return 1; 1924 } 1925 } 1926 1927 return 0; 1928 } 1929 1930 static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) 1931 { 1932 debug ("flash detect cfi\n"); 1933 1934 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; 1935 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { 1936 for (info->chipwidth = FLASH_CFI_BY8; 1937 info->chipwidth <= info->portwidth; 1938 info->chipwidth <<= 1) 1939 if (__flash_detect_cfi(info, qry)) 1940 return 1; 1941 } 1942 debug ("not found\n"); 1943 return 0; 1944 } 1945 1946 /* 1947 * Manufacturer-specific quirks. Add workarounds for geometry 1948 * reversal, etc. here. 1949 */ 1950 static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) 1951 { 1952 /* check if flash geometry needs reversal */ 1953 if (qry->num_erase_regions > 1) { 1954 /* reverse geometry if top boot part */ 1955 if (info->cfi_version < 0x3131) { 1956 /* CFI < 1.1, try to guess from device id */ 1957 if ((info->device_id & 0x80) != 0) 1958 cfi_reverse_geometry(qry); 1959 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 1960 /* CFI >= 1.1, deduct from top/bottom flag */ 1961 /* note: ext_addr is valid since cfi_version > 0 */ 1962 cfi_reverse_geometry(qry); 1963 } 1964 } 1965 } 1966 1967 static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) 1968 { 1969 int reverse_geometry = 0; 1970 1971 /* Check the "top boot" bit in the PRI */ 1972 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) 1973 reverse_geometry = 1; 1974 1975 /* AT49BV6416(T) list the erase regions in the wrong order. 1976 * However, the device ID is identical with the non-broken 1977 * AT49BV642D they differ in the high byte. 1978 */ 1979 if (info->device_id == 0xd6 || info->device_id == 0xd2) 1980 reverse_geometry = !reverse_geometry; 1981 1982 if (reverse_geometry) 1983 cfi_reverse_geometry(qry); 1984 } 1985 1986 static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) 1987 { 1988 /* check if flash geometry needs reversal */ 1989 if (qry->num_erase_regions > 1) { 1990 /* reverse geometry if top boot part */ 1991 if (info->cfi_version < 0x3131) { 1992 /* CFI < 1.1, guess by device id */ 1993 if (info->device_id == 0x22CA || /* M29W320DT */ 1994 info->device_id == 0x2256 || /* M29W320ET */ 1995 info->device_id == 0x22D7) { /* M29W800DT */ 1996 cfi_reverse_geometry(qry); 1997 } 1998 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 1999 /* CFI >= 1.1, deduct from top/bottom flag */ 2000 /* note: ext_addr is valid since cfi_version > 0 */ 2001 cfi_reverse_geometry(qry); 2002 } 2003 } 2004 } 2005 2006 static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry) 2007 { 2008 /* 2009 * SST, for many recent nor parallel flashes, says they are 2010 * CFI-conformant. This is not true, since qry struct. 2011 * reports a std. AMD command set (0x0002), while SST allows to 2012 * erase two different sector sizes for the same memory. 2013 * 64KB sector (SST call it block) needs 0x30 to be erased. 2014 * 4KB sector (SST call it sector) needs 0x50 to be erased. 2015 * Since CFI query detect the 4KB number of sectors, users expects 2016 * a sector granularity of 4KB, and it is here set. 2017 */ 2018 if (info->device_id == 0x5D23 || /* SST39VF3201B */ 2019 info->device_id == 0x5C23) { /* SST39VF3202B */ 2020 /* set sector granularity to 4KB */ 2021 info->cmd_erase_sector=0x50; 2022 } 2023 } 2024 2025 static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry) 2026 { 2027 /* 2028 * The M29EW devices seem to report the CFI information wrong 2029 * when it's in 8 bit mode. 2030 * There's an app note from Numonyx on this issue. 2031 * So adjust the buffer size for M29EW while operating in 8-bit mode 2032 */ 2033 if (((qry->max_buf_write_size) > 0x8) && 2034 (info->device_id == 0x7E) && 2035 (info->device_id2 == 0x2201 || 2036 info->device_id2 == 0x2301 || 2037 info->device_id2 == 0x2801 || 2038 info->device_id2 == 0x4801)) { 2039 debug("Adjusted buffer size on Numonyx flash" 2040 " M29EW family in 8 bit mode\n"); 2041 qry->max_buf_write_size = 0x8; 2042 } 2043 } 2044 2045 /* 2046 * The following code cannot be run from FLASH! 2047 * 2048 */ 2049 ulong flash_get_size (phys_addr_t base, int banknum) 2050 { 2051 flash_info_t *info = &flash_info[banknum]; 2052 int i, j; 2053 flash_sect_t sect_cnt; 2054 phys_addr_t sector; 2055 unsigned long tmp; 2056 int size_ratio; 2057 uchar num_erase_regions; 2058 int erase_region_size; 2059 int erase_region_count; 2060 struct cfi_qry qry; 2061 unsigned long max_size; 2062 2063 memset(&qry, 0, sizeof(qry)); 2064 2065 info->ext_addr = 0; 2066 info->cfi_version = 0; 2067 #ifdef CONFIG_SYS_FLASH_PROTECTION 2068 info->legacy_unlock = 0; 2069 #endif 2070 2071 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE); 2072 2073 if (flash_detect_cfi (info, &qry)) { 2074 info->vendor = le16_to_cpu(get_unaligned(&(qry.p_id))); 2075 info->ext_addr = le16_to_cpu(get_unaligned(&(qry.p_adr))); 2076 num_erase_regions = qry.num_erase_regions; 2077 2078 if (info->ext_addr) { 2079 info->cfi_version = (ushort) flash_read_uchar (info, 2080 info->ext_addr + 3) << 8; 2081 info->cfi_version |= (ushort) flash_read_uchar (info, 2082 info->ext_addr + 4); 2083 } 2084 2085 #ifdef DEBUG 2086 flash_printqry (&qry); 2087 #endif 2088 2089 switch (info->vendor) { 2090 case CFI_CMDSET_INTEL_PROG_REGIONS: 2091 case CFI_CMDSET_INTEL_STANDARD: 2092 case CFI_CMDSET_INTEL_EXTENDED: 2093 cmdset_intel_init(info, &qry); 2094 break; 2095 case CFI_CMDSET_AMD_STANDARD: 2096 case CFI_CMDSET_AMD_EXTENDED: 2097 cmdset_amd_init(info, &qry); 2098 break; 2099 default: 2100 printf("CFI: Unknown command set 0x%x\n", 2101 info->vendor); 2102 /* 2103 * Unfortunately, this means we don't know how 2104 * to get the chip back to Read mode. Might 2105 * as well try an Intel-style reset... 2106 */ 2107 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 2108 return 0; 2109 } 2110 2111 /* Do manufacturer-specific fixups */ 2112 switch (info->manufacturer_id) { 2113 case 0x0001: /* AMD */ 2114 case 0x0037: /* AMIC */ 2115 flash_fixup_amd(info, &qry); 2116 break; 2117 case 0x001f: 2118 flash_fixup_atmel(info, &qry); 2119 break; 2120 case 0x0020: 2121 flash_fixup_stm(info, &qry); 2122 break; 2123 case 0x00bf: /* SST */ 2124 flash_fixup_sst(info, &qry); 2125 break; 2126 case 0x0089: /* Numonyx */ 2127 flash_fixup_num(info, &qry); 2128 break; 2129 } 2130 2131 debug ("manufacturer is %d\n", info->vendor); 2132 debug ("manufacturer id is 0x%x\n", info->manufacturer_id); 2133 debug ("device id is 0x%x\n", info->device_id); 2134 debug ("device id2 is 0x%x\n", info->device_id2); 2135 debug ("cfi version is 0x%04x\n", info->cfi_version); 2136 2137 size_ratio = info->portwidth / info->chipwidth; 2138 /* if the chip is x8/x16 reduce the ratio by half */ 2139 if ((info->interface == FLASH_CFI_X8X16) 2140 && (info->chipwidth == FLASH_CFI_BY8)) { 2141 size_ratio >>= 1; 2142 } 2143 debug ("size_ratio %d port %d bits chip %d bits\n", 2144 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, 2145 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 2146 info->size = 1 << qry.dev_size; 2147 /* multiply the size by the number of chips */ 2148 info->size *= size_ratio; 2149 max_size = cfi_flash_bank_size(banknum); 2150 if (max_size && (info->size > max_size)) { 2151 debug("[truncated from %ldMiB]", info->size >> 20); 2152 info->size = max_size; 2153 } 2154 debug ("found %d erase regions\n", num_erase_regions); 2155 sect_cnt = 0; 2156 sector = base; 2157 for (i = 0; i < num_erase_regions; i++) { 2158 if (i > NUM_ERASE_REGIONS) { 2159 printf ("%d erase regions found, only %d used\n", 2160 num_erase_regions, NUM_ERASE_REGIONS); 2161 break; 2162 } 2163 2164 tmp = le32_to_cpu(get_unaligned( 2165 &(qry.erase_region_info[i]))); 2166 debug("erase region %u: 0x%08lx\n", i, tmp); 2167 2168 erase_region_count = (tmp & 0xffff) + 1; 2169 tmp >>= 16; 2170 erase_region_size = 2171 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; 2172 debug ("erase_region_count = %d erase_region_size = %d\n", 2173 erase_region_count, erase_region_size); 2174 for (j = 0; j < erase_region_count; j++) { 2175 if (sector - base >= info->size) 2176 break; 2177 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { 2178 printf("ERROR: too many flash sectors\n"); 2179 break; 2180 } 2181 info->start[sect_cnt] = 2182 (ulong)map_physmem(sector, 2183 info->portwidth, 2184 MAP_NOCACHE); 2185 sector += (erase_region_size * size_ratio); 2186 2187 /* 2188 * Only read protection status from 2189 * supported devices (intel...) 2190 */ 2191 switch (info->vendor) { 2192 case CFI_CMDSET_INTEL_PROG_REGIONS: 2193 case CFI_CMDSET_INTEL_EXTENDED: 2194 case CFI_CMDSET_INTEL_STANDARD: 2195 /* 2196 * Set flash to read-id mode. Otherwise 2197 * reading protected status is not 2198 * guaranteed. 2199 */ 2200 flash_write_cmd(info, sect_cnt, 0, 2201 FLASH_CMD_READ_ID); 2202 info->protect[sect_cnt] = 2203 flash_isset (info, sect_cnt, 2204 FLASH_OFFSET_PROTECT, 2205 FLASH_STATUS_PROTECT); 2206 flash_write_cmd(info, sect_cnt, 0, 2207 FLASH_CMD_RESET); 2208 break; 2209 case CFI_CMDSET_AMD_EXTENDED: 2210 case CFI_CMDSET_AMD_STANDARD: 2211 if (!info->legacy_unlock) { 2212 /* default: not protected */ 2213 info->protect[sect_cnt] = 0; 2214 break; 2215 } 2216 2217 /* Read protection (PPB) from sector */ 2218 flash_write_cmd(info, 0, 0, 2219 info->cmd_reset); 2220 flash_unlock_seq(info, 0); 2221 flash_write_cmd(info, 0, 2222 info->addr_unlock1, 2223 FLASH_CMD_READ_ID); 2224 info->protect[sect_cnt] = 2225 flash_isset( 2226 info, sect_cnt, 2227 FLASH_OFFSET_PROTECT, 2228 FLASH_STATUS_PROTECT); 2229 break; 2230 default: 2231 /* default: not protected */ 2232 info->protect[sect_cnt] = 0; 2233 } 2234 2235 sect_cnt++; 2236 } 2237 } 2238 2239 info->sector_count = sect_cnt; 2240 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); 2241 tmp = 1 << qry.block_erase_timeout_typ; 2242 info->erase_blk_tout = tmp * 2243 (1 << qry.block_erase_timeout_max); 2244 tmp = (1 << qry.buf_write_timeout_typ) * 2245 (1 << qry.buf_write_timeout_max); 2246 2247 /* round up when converting to ms */ 2248 info->buffer_write_tout = (tmp + 999) / 1000; 2249 tmp = (1 << qry.word_write_timeout_typ) * 2250 (1 << qry.word_write_timeout_max); 2251 /* round up when converting to ms */ 2252 info->write_tout = (tmp + 999) / 1000; 2253 info->flash_id = FLASH_MAN_CFI; 2254 if ((info->interface == FLASH_CFI_X8X16) && 2255 (info->chipwidth == FLASH_CFI_BY8)) { 2256 /* XXX - Need to test on x8/x16 in parallel. */ 2257 info->portwidth >>= 1; 2258 } 2259 2260 flash_write_cmd (info, 0, 0, info->cmd_reset); 2261 } 2262 2263 return (info->size); 2264 } 2265 2266 #ifdef CONFIG_FLASH_CFI_MTD 2267 void flash_set_verbose(uint v) 2268 { 2269 flash_verbose = v; 2270 } 2271 #endif 2272 2273 static void cfi_flash_set_config_reg(u32 base, u16 val) 2274 { 2275 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS 2276 /* 2277 * Only set this config register if really defined 2278 * to a valid value (0xffff is invalid) 2279 */ 2280 if (val == 0xffff) 2281 return; 2282 2283 /* 2284 * Set configuration register. Data is "encrypted" in the 16 lower 2285 * address bits. 2286 */ 2287 flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1))); 2288 flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1))); 2289 2290 /* 2291 * Finally issue reset-command to bring device back to 2292 * read-array mode 2293 */ 2294 flash_write16(FLASH_CMD_RESET, (void *)base); 2295 #endif 2296 } 2297 2298 /*----------------------------------------------------------------------- 2299 */ 2300 2301 void flash_protect_default(void) 2302 { 2303 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) 2304 int i; 2305 struct apl_s { 2306 ulong start; 2307 ulong size; 2308 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST; 2309 #endif 2310 2311 /* Monitor protection ON by default */ 2312 #if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ 2313 (!defined(CONFIG_MONITOR_IS_IN_RAM)) 2314 flash_protect(FLAG_PROTECT_SET, 2315 CONFIG_SYS_MONITOR_BASE, 2316 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, 2317 flash_get_info(CONFIG_SYS_MONITOR_BASE)); 2318 #endif 2319 2320 /* Environment protection ON by default */ 2321 #ifdef CONFIG_ENV_IS_IN_FLASH 2322 flash_protect(FLAG_PROTECT_SET, 2323 CONFIG_ENV_ADDR, 2324 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, 2325 flash_get_info(CONFIG_ENV_ADDR)); 2326 #endif 2327 2328 /* Redundant environment protection ON by default */ 2329 #ifdef CONFIG_ENV_ADDR_REDUND 2330 flash_protect(FLAG_PROTECT_SET, 2331 CONFIG_ENV_ADDR_REDUND, 2332 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, 2333 flash_get_info(CONFIG_ENV_ADDR_REDUND)); 2334 #endif 2335 2336 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) 2337 for (i = 0; i < ARRAY_SIZE(apl); i++) { 2338 debug("autoprotecting from %08lx to %08lx\n", 2339 apl[i].start, apl[i].start + apl[i].size - 1); 2340 flash_protect(FLAG_PROTECT_SET, 2341 apl[i].start, 2342 apl[i].start + apl[i].size - 1, 2343 flash_get_info(apl[i].start)); 2344 } 2345 #endif 2346 } 2347 2348 unsigned long flash_init (void) 2349 { 2350 unsigned long size = 0; 2351 int i; 2352 2353 #ifdef CONFIG_SYS_FLASH_PROTECTION 2354 /* read environment from EEPROM */ 2355 char s[64]; 2356 getenv_f("unlock", s, sizeof(s)); 2357 #endif 2358 2359 #ifdef CONFIG_CFI_FLASH /* for driver model */ 2360 cfi_flash_init_dm(); 2361 #endif 2362 2363 /* Init: no FLASHes known */ 2364 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { 2365 flash_info[i].flash_id = FLASH_UNKNOWN; 2366 2367 /* Optionally write flash configuration register */ 2368 cfi_flash_set_config_reg(cfi_flash_bank_addr(i), 2369 cfi_flash_config_reg(i)); 2370 2371 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) 2372 flash_get_size(cfi_flash_bank_addr(i), i); 2373 size += flash_info[i].size; 2374 if (flash_info[i].flash_id == FLASH_UNKNOWN) { 2375 #ifndef CONFIG_SYS_FLASH_QUIET_TEST 2376 printf ("## Unknown flash on Bank %d " 2377 "- Size = 0x%08lx = %ld MB\n", 2378 i+1, flash_info[i].size, 2379 flash_info[i].size >> 20); 2380 #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ 2381 } 2382 #ifdef CONFIG_SYS_FLASH_PROTECTION 2383 else if (strcmp(s, "yes") == 0) { 2384 /* 2385 * Only the U-Boot image and it's environment 2386 * is protected, all other sectors are 2387 * unprotected (unlocked) if flash hardware 2388 * protection is used (CONFIG_SYS_FLASH_PROTECTION) 2389 * and the environment variable "unlock" is 2390 * set to "yes". 2391 */ 2392 if (flash_info[i].legacy_unlock) { 2393 int k; 2394 2395 /* 2396 * Disable legacy_unlock temporarily, 2397 * since flash_real_protect would 2398 * relock all other sectors again 2399 * otherwise. 2400 */ 2401 flash_info[i].legacy_unlock = 0; 2402 2403 /* 2404 * Legacy unlocking (e.g. Intel J3) -> 2405 * unlock only one sector. This will 2406 * unlock all sectors. 2407 */ 2408 flash_real_protect (&flash_info[i], 0, 0); 2409 2410 flash_info[i].legacy_unlock = 1; 2411 2412 /* 2413 * Manually mark other sectors as 2414 * unlocked (unprotected) 2415 */ 2416 for (k = 1; k < flash_info[i].sector_count; k++) 2417 flash_info[i].protect[k] = 0; 2418 } else { 2419 /* 2420 * No legancy unlocking -> unlock all sectors 2421 */ 2422 flash_protect (FLAG_PROTECT_CLEAR, 2423 flash_info[i].start[0], 2424 flash_info[i].start[0] 2425 + flash_info[i].size - 1, 2426 &flash_info[i]); 2427 } 2428 } 2429 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 2430 } 2431 2432 flash_protect_default(); 2433 #ifdef CONFIG_FLASH_CFI_MTD 2434 cfi_mtd_init(); 2435 #endif 2436 2437 return (size); 2438 } 2439 2440 #ifdef CONFIG_CFI_FLASH /* for driver model */ 2441 static int cfi_flash_probe(struct udevice *dev) 2442 { 2443 void *blob = (void *)gd->fdt_blob; 2444 int node = dev_of_offset(dev); 2445 const fdt32_t *cell; 2446 phys_addr_t addr; 2447 int parent, addrc, sizec; 2448 int len, idx; 2449 2450 parent = fdt_parent_offset(blob, node); 2451 of_bus_default_count_cells(blob, parent, &addrc, &sizec); 2452 /* decode regs, there may be multiple reg tuples. */ 2453 cell = fdt_getprop(blob, node, "reg", &len); 2454 if (!cell) 2455 return -ENOENT; 2456 idx = 0; 2457 len /= sizeof(fdt32_t); 2458 while (idx < len) { 2459 addr = fdt_translate_address((void *)blob, 2460 node, cell + idx); 2461 cfi_flash_base[cfi_flash_num_flash_banks++] = addr; 2462 idx += addrc + sizec; 2463 } 2464 gd->bd->bi_flashstart = cfi_flash_base[0]; 2465 2466 return 0; 2467 } 2468 2469 static const struct udevice_id cfi_flash_ids[] = { 2470 { .compatible = "cfi-flash" }, 2471 { .compatible = "jedec-flash" }, 2472 {} 2473 }; 2474 2475 U_BOOT_DRIVER(cfi_flash) = { 2476 .name = "cfi_flash", 2477 .id = UCLASS_MTD, 2478 .of_match = cfi_flash_ids, 2479 .probe = cfi_flash_probe, 2480 }; 2481 #endif /* CONFIG_CFI_FLASH */ 2482