1 /* 2 * (C) Copyright 2002-2004 3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com 4 * 5 * Copyright (C) 2003 Arabella Software Ltd. 6 * Yuli Barcohen <yuli@arabellasw.com> 7 * 8 * Copyright (C) 2004 9 * Ed Okerson 10 * 11 * Copyright (C) 2006 12 * Tolunay Orkun <listmember@orkun.us> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 /* The DEBUG define must be before common to enable debugging */ 18 /* #define DEBUG */ 19 20 #include <common.h> 21 #include <console.h> 22 #include <dm.h> 23 #include <errno.h> 24 #include <fdt_support.h> 25 #include <asm/processor.h> 26 #include <asm/io.h> 27 #include <asm/byteorder.h> 28 #include <asm/unaligned.h> 29 #include <environment.h> 30 #include <mtd/cfi_flash.h> 31 #include <watchdog.h> 32 33 /* 34 * This file implements a Common Flash Interface (CFI) driver for 35 * U-Boot. 36 * 37 * The width of the port and the width of the chips are determined at 38 * initialization. These widths are used to calculate the address for 39 * access CFI data structures. 40 * 41 * References 42 * JEDEC Standard JESD68 - Common Flash Interface (CFI) 43 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes 44 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets 45 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet 46 * AMD CFI Specification, Release 2.0 December 1, 2001 47 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte 48 * Device IDs, Publication Number 25538 Revision A, November 8, 2001 49 * 50 * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between 51 * reading and writing ... (yes there is such a Hardware). 52 */ 53 54 DECLARE_GLOBAL_DATA_PTR; 55 56 static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; 57 #ifdef CONFIG_FLASH_CFI_MTD 58 static uint flash_verbose = 1; 59 #else 60 #define flash_verbose 1 61 #endif 62 63 flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ 64 65 /* 66 * Check if chip width is defined. If not, start detecting with 8bit. 67 */ 68 #ifndef CONFIG_SYS_FLASH_CFI_WIDTH 69 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 70 #endif 71 72 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 73 #define __maybe_weak __weak 74 #else 75 #define __maybe_weak static 76 #endif 77 78 /* 79 * 0xffff is an undefined value for the configuration register. When 80 * this value is returned, the configuration register shall not be 81 * written at all (default mode). 82 */ 83 static u16 cfi_flash_config_reg(int i) 84 { 85 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS 86 return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i]; 87 #else 88 return 0xffff; 89 #endif 90 } 91 92 #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) 93 int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; 94 #else 95 int cfi_flash_num_flash_banks; 96 #endif 97 98 #ifdef CONFIG_CFI_FLASH /* for driver model */ 99 static void cfi_flash_init_dm(void) 100 { 101 struct udevice *dev; 102 103 cfi_flash_num_flash_banks = 0; 104 /* 105 * The uclass_first_device() will probe the first device and 106 * uclass_next_device() will probe the rest if they exist. So 107 * that cfi_flash_probe() will get called assigning the base 108 * addresses that are available. 109 */ 110 for (uclass_first_device(UCLASS_MTD, &dev); 111 dev; 112 uclass_next_device(&dev)) { 113 } 114 } 115 116 phys_addr_t cfi_flash_bank_addr(int i) 117 { 118 return flash_info[i].base; 119 } 120 #else 121 __weak phys_addr_t cfi_flash_bank_addr(int i) 122 { 123 return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; 124 } 125 #endif 126 127 __weak unsigned long cfi_flash_bank_size(int i) 128 { 129 #ifdef CONFIG_SYS_FLASH_BANKS_SIZES 130 return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; 131 #else 132 return 0; 133 #endif 134 } 135 136 __maybe_weak void flash_write8(u8 value, void *addr) 137 { 138 __raw_writeb(value, addr); 139 } 140 141 __maybe_weak void flash_write16(u16 value, void *addr) 142 { 143 __raw_writew(value, addr); 144 } 145 146 __maybe_weak void flash_write32(u32 value, void *addr) 147 { 148 __raw_writel(value, addr); 149 } 150 151 __maybe_weak void flash_write64(u64 value, void *addr) 152 { 153 /* No architectures currently implement __raw_writeq() */ 154 *(volatile u64 *)addr = value; 155 } 156 157 __maybe_weak u8 flash_read8(void *addr) 158 { 159 return __raw_readb(addr); 160 } 161 162 __maybe_weak u16 flash_read16(void *addr) 163 { 164 return __raw_readw(addr); 165 } 166 167 __maybe_weak u32 flash_read32(void *addr) 168 { 169 return __raw_readl(addr); 170 } 171 172 __maybe_weak u64 flash_read64(void *addr) 173 { 174 /* No architectures currently implement __raw_readq() */ 175 return *(volatile u64 *)addr; 176 } 177 178 /*----------------------------------------------------------------------- 179 */ 180 #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \ 181 (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) 182 static flash_info_t *flash_get_info(ulong base) 183 { 184 int i; 185 flash_info_t *info; 186 187 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { 188 info = &flash_info[i]; 189 if (info->size && info->start[0] <= base && 190 base <= info->start[0] + info->size - 1) 191 return info; 192 } 193 194 return NULL; 195 } 196 #endif 197 198 unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) 199 { 200 if (sect != (info->sector_count - 1)) 201 return info->start[sect + 1] - info->start[sect]; 202 else 203 return info->start[0] + info->size - info->start[sect]; 204 } 205 206 /*----------------------------------------------------------------------- 207 * create an address based on the offset and the port width 208 */ 209 static inline void * 210 flash_map(flash_info_t *info, flash_sect_t sect, uint offset) 211 { 212 unsigned int byte_offset = offset * info->portwidth; 213 214 return (void *)(info->start[sect] + byte_offset); 215 } 216 217 static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, 218 unsigned int offset, void *addr) 219 { 220 } 221 222 /*----------------------------------------------------------------------- 223 * make a proper sized command based on the port and chip widths 224 */ 225 static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) 226 { 227 int i; 228 int cword_offset; 229 int cp_offset; 230 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 231 u32 cmd_le = cpu_to_le32(cmd); 232 #endif 233 uchar val; 234 uchar *cp = (uchar *) cmdbuf; 235 236 for (i = info->portwidth; i > 0; i--) { 237 cword_offset = (info->portwidth - i) % info->chipwidth; 238 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 239 cp_offset = info->portwidth - i; 240 val = *((uchar *)&cmd_le + cword_offset); 241 #else 242 cp_offset = i - 1; 243 val = *((uchar *)&cmd + sizeof(u32) - cword_offset - 1); 244 #endif 245 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val; 246 } 247 } 248 249 #ifdef DEBUG 250 /*----------------------------------------------------------------------- 251 * Debug support 252 */ 253 static void print_longlong(char *str, unsigned long long data) 254 { 255 int i; 256 char *cp; 257 258 cp = (char *)&data; 259 for (i = 0; i < 8; i++) 260 sprintf(&str[i * 2], "%2.2x", *cp++); 261 } 262 263 static void flash_printqry(struct cfi_qry *qry) 264 { 265 u8 *p = (u8 *)qry; 266 int x, y; 267 268 for (x = 0; x < sizeof(struct cfi_qry); x += 16) { 269 debug("%02x : ", x); 270 for (y = 0; y < 16; y++) 271 debug("%2.2x ", p[x + y]); 272 debug(" "); 273 for (y = 0; y < 16; y++) { 274 unsigned char c = p[x + y]; 275 276 if (c >= 0x20 && c <= 0x7e) 277 debug("%c", c); 278 else 279 debug("."); 280 } 281 debug("\n"); 282 } 283 } 284 #endif 285 286 /*----------------------------------------------------------------------- 287 * read a character at a port width address 288 */ 289 static inline uchar flash_read_uchar(flash_info_t *info, uint offset) 290 { 291 uchar *cp; 292 uchar retval; 293 294 cp = flash_map(info, 0, offset); 295 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 296 retval = flash_read8(cp); 297 #else 298 retval = flash_read8(cp + info->portwidth - 1); 299 #endif 300 flash_unmap(info, 0, offset, cp); 301 return retval; 302 } 303 304 /*----------------------------------------------------------------------- 305 * read a word at a port width address, assume 16bit bus 306 */ 307 static inline ushort flash_read_word(flash_info_t *info, uint offset) 308 { 309 ushort *addr, retval; 310 311 addr = flash_map(info, 0, offset); 312 retval = flash_read16(addr); 313 flash_unmap(info, 0, offset, addr); 314 return retval; 315 } 316 317 /*----------------------------------------------------------------------- 318 * read a long word by picking the least significant byte of each maximum 319 * port size word. Swap for ppc format. 320 */ 321 static ulong flash_read_long (flash_info_t *info, flash_sect_t sect, 322 uint offset) 323 { 324 uchar *addr; 325 ulong retval; 326 327 #ifdef DEBUG 328 int x; 329 #endif 330 addr = flash_map(info, sect, offset); 331 332 #ifdef DEBUG 333 debug("long addr is at %p info->portwidth = %d\n", addr, 334 info->portwidth); 335 for (x = 0; x < 4 * info->portwidth; x++) 336 debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); 337 #endif 338 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 339 retval = ((flash_read8(addr) << 16) | 340 (flash_read8(addr + info->portwidth) << 24) | 341 (flash_read8(addr + 2 * info->portwidth)) | 342 (flash_read8(addr + 3 * info->portwidth) << 8)); 343 #else 344 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | 345 (flash_read8(addr + info->portwidth - 1) << 16) | 346 (flash_read8(addr + 4 * info->portwidth - 1) << 8) | 347 (flash_read8(addr + 3 * info->portwidth - 1))); 348 #endif 349 flash_unmap(info, sect, offset, addr); 350 351 return retval; 352 } 353 354 /* 355 * Write a proper sized command to the correct address 356 */ 357 static void flash_write_cmd(flash_info_t *info, flash_sect_t sect, 358 uint offset, u32 cmd) 359 { 360 void *addr; 361 cfiword_t cword; 362 363 addr = flash_map(info, sect, offset); 364 flash_make_cmd(info, cmd, &cword); 365 switch (info->portwidth) { 366 case FLASH_CFI_8BIT: 367 debug("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, 368 cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 369 flash_write8(cword.w8, addr); 370 break; 371 case FLASH_CFI_16BIT: 372 debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, 373 cmd, cword.w16, 374 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 375 flash_write16(cword.w16, addr); 376 break; 377 case FLASH_CFI_32BIT: 378 debug("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr, 379 cmd, cword.w32, 380 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 381 flash_write32(cword.w32, addr); 382 break; 383 case FLASH_CFI_64BIT: 384 #ifdef DEBUG 385 { 386 char str[20]; 387 388 print_longlong(str, cword.w64); 389 390 debug("fwrite addr %p cmd %x %s 64 bit x %d bit\n", 391 addr, cmd, str, 392 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 393 } 394 #endif 395 flash_write64(cword.w64, addr); 396 break; 397 } 398 399 /* Ensure all the instructions are fully finished */ 400 sync(); 401 402 flash_unmap(info, sect, offset, addr); 403 } 404 405 static void flash_unlock_seq(flash_info_t *info, flash_sect_t sect) 406 { 407 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); 408 flash_write_cmd(info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); 409 } 410 411 /*----------------------------------------------------------------------- 412 */ 413 static int flash_isequal(flash_info_t *info, flash_sect_t sect, uint offset, 414 uchar cmd) 415 { 416 void *addr; 417 cfiword_t cword; 418 int retval; 419 420 addr = flash_map(info, sect, offset); 421 flash_make_cmd(info, cmd, &cword); 422 423 debug("is= cmd %x(%c) addr %p ", cmd, cmd, addr); 424 switch (info->portwidth) { 425 case FLASH_CFI_8BIT: 426 debug("is= %x %x\n", flash_read8(addr), cword.w8); 427 retval = (flash_read8(addr) == cword.w8); 428 break; 429 case FLASH_CFI_16BIT: 430 debug("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16); 431 retval = (flash_read16(addr) == cword.w16); 432 break; 433 case FLASH_CFI_32BIT: 434 debug("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32); 435 retval = (flash_read32(addr) == cword.w32); 436 break; 437 case FLASH_CFI_64BIT: 438 #ifdef DEBUG 439 { 440 char str1[20]; 441 char str2[20]; 442 443 print_longlong(str1, flash_read64(addr)); 444 print_longlong(str2, cword.w64); 445 debug("is= %s %s\n", str1, str2); 446 } 447 #endif 448 retval = (flash_read64(addr) == cword.w64); 449 break; 450 default: 451 retval = 0; 452 break; 453 } 454 flash_unmap(info, sect, offset, addr); 455 456 return retval; 457 } 458 459 /*----------------------------------------------------------------------- 460 */ 461 static int flash_isset(flash_info_t *info, flash_sect_t sect, uint offset, 462 uchar cmd) 463 { 464 void *addr; 465 cfiword_t cword; 466 int retval; 467 468 addr = flash_map(info, sect, offset); 469 flash_make_cmd(info, cmd, &cword); 470 switch (info->portwidth) { 471 case FLASH_CFI_8BIT: 472 retval = ((flash_read8(addr) & cword.w8) == cword.w8); 473 break; 474 case FLASH_CFI_16BIT: 475 retval = ((flash_read16(addr) & cword.w16) == cword.w16); 476 break; 477 case FLASH_CFI_32BIT: 478 retval = ((flash_read32(addr) & cword.w32) == cword.w32); 479 break; 480 case FLASH_CFI_64BIT: 481 retval = ((flash_read64(addr) & cword.w64) == cword.w64); 482 break; 483 default: 484 retval = 0; 485 break; 486 } 487 flash_unmap(info, sect, offset, addr); 488 489 return retval; 490 } 491 492 /*----------------------------------------------------------------------- 493 */ 494 static int flash_toggle(flash_info_t *info, flash_sect_t sect, uint offset, 495 uchar cmd) 496 { 497 u8 *addr; 498 cfiword_t cword; 499 int retval; 500 501 addr = flash_map(info, sect, offset); 502 flash_make_cmd(info, cmd, &cword); 503 switch (info->portwidth) { 504 case FLASH_CFI_8BIT: 505 retval = flash_read8(addr) != flash_read8(addr); 506 break; 507 case FLASH_CFI_16BIT: 508 retval = flash_read16(addr) != flash_read16(addr); 509 break; 510 case FLASH_CFI_32BIT: 511 retval = flash_read32(addr) != flash_read32(addr); 512 break; 513 case FLASH_CFI_64BIT: 514 retval = ((flash_read32(addr) != flash_read32(addr)) || 515 (flash_read32(addr + 4) != flash_read32(addr + 4))); 516 break; 517 default: 518 retval = 0; 519 break; 520 } 521 flash_unmap(info, sect, offset, addr); 522 523 return retval; 524 } 525 526 /* 527 * flash_is_busy - check to see if the flash is busy 528 * 529 * This routine checks the status of the chip and returns true if the 530 * chip is busy. 531 */ 532 static int flash_is_busy(flash_info_t *info, flash_sect_t sect) 533 { 534 int retval; 535 536 switch (info->vendor) { 537 case CFI_CMDSET_INTEL_PROG_REGIONS: 538 case CFI_CMDSET_INTEL_STANDARD: 539 case CFI_CMDSET_INTEL_EXTENDED: 540 retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE); 541 break; 542 case CFI_CMDSET_AMD_STANDARD: 543 case CFI_CMDSET_AMD_EXTENDED: 544 #ifdef CONFIG_FLASH_CFI_LEGACY 545 case CFI_CMDSET_AMD_LEGACY: 546 #endif 547 if (info->sr_supported) { 548 flash_write_cmd(info, sect, info->addr_unlock1, 549 FLASH_CMD_READ_STATUS); 550 retval = !flash_isset(info, sect, 0, 551 FLASH_STATUS_DONE); 552 } else { 553 retval = flash_toggle(info, sect, 0, 554 AMD_STATUS_TOGGLE); 555 } 556 557 break; 558 default: 559 retval = 0; 560 } 561 debug("%s: %d\n", __func__, retval); 562 return retval; 563 } 564 565 /*----------------------------------------------------------------------- 566 * wait for XSR.7 to be set. Time out with an error if it does not. 567 * This routine does not set the flash to read-array mode. 568 */ 569 static int flash_status_check(flash_info_t *info, flash_sect_t sector, 570 ulong tout, char *prompt) 571 { 572 ulong start; 573 574 #if CONFIG_SYS_HZ != 1000 575 /* Avoid overflow for large HZ */ 576 if ((ulong)CONFIG_SYS_HZ > 100000) 577 tout *= (ulong)CONFIG_SYS_HZ / 1000; 578 else 579 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); 580 #endif 581 582 /* Wait for command completion */ 583 #ifdef CONFIG_SYS_LOW_RES_TIMER 584 reset_timer(); 585 #endif 586 start = get_timer(0); 587 WATCHDOG_RESET(); 588 while (flash_is_busy(info, sector)) { 589 if (get_timer(start) > tout) { 590 printf("Flash %s timeout at address %lx data %lx\n", 591 prompt, info->start[sector], 592 flash_read_long(info, sector, 0)); 593 flash_write_cmd(info, sector, 0, info->cmd_reset); 594 udelay(1); 595 return ERR_TIMEOUT; 596 } 597 udelay(1); /* also triggers watchdog */ 598 } 599 return ERR_OK; 600 } 601 602 /*----------------------------------------------------------------------- 603 * Wait for XSR.7 to be set, if it times out print an error, otherwise 604 * do a full status check. 605 * 606 * This routine sets the flash to read-array mode. 607 */ 608 static int flash_full_status_check(flash_info_t *info, flash_sect_t sector, 609 ulong tout, char *prompt) 610 { 611 int retcode; 612 613 retcode = flash_status_check(info, sector, tout, prompt); 614 switch (info->vendor) { 615 case CFI_CMDSET_INTEL_PROG_REGIONS: 616 case CFI_CMDSET_INTEL_EXTENDED: 617 case CFI_CMDSET_INTEL_STANDARD: 618 if (retcode == ERR_OK && 619 !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { 620 retcode = ERR_INVAL; 621 printf("Flash %s error at address %lx\n", prompt, 622 info->start[sector]); 623 if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | 624 FLASH_STATUS_PSLBS)) { 625 puts("Command Sequence Error.\n"); 626 } else if (flash_isset(info, sector, 0, 627 FLASH_STATUS_ECLBS)) { 628 puts("Block Erase Error.\n"); 629 retcode = ERR_NOT_ERASED; 630 } else if (flash_isset(info, sector, 0, 631 FLASH_STATUS_PSLBS)) { 632 puts("Locking Error\n"); 633 } 634 if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) { 635 puts("Block locked.\n"); 636 retcode = ERR_PROTECTED; 637 } 638 if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) 639 puts("Vpp Low Error.\n"); 640 } 641 flash_write_cmd(info, sector, 0, info->cmd_reset); 642 udelay(1); 643 break; 644 default: 645 break; 646 } 647 return retcode; 648 } 649 650 static int use_flash_status_poll(flash_info_t *info) 651 { 652 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL 653 if (info->vendor == CFI_CMDSET_AMD_EXTENDED || 654 info->vendor == CFI_CMDSET_AMD_STANDARD) 655 return 1; 656 #endif 657 return 0; 658 } 659 660 static int flash_status_poll(flash_info_t *info, void *src, void *dst, 661 ulong tout, char *prompt) 662 { 663 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL 664 ulong start; 665 int ready; 666 667 #if CONFIG_SYS_HZ != 1000 668 /* Avoid overflow for large HZ */ 669 if ((ulong)CONFIG_SYS_HZ > 100000) 670 tout *= (ulong)CONFIG_SYS_HZ / 1000; 671 else 672 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); 673 #endif 674 675 /* Wait for command completion */ 676 #ifdef CONFIG_SYS_LOW_RES_TIMER 677 reset_timer(); 678 #endif 679 start = get_timer(0); 680 WATCHDOG_RESET(); 681 while (1) { 682 switch (info->portwidth) { 683 case FLASH_CFI_8BIT: 684 ready = flash_read8(dst) == flash_read8(src); 685 break; 686 case FLASH_CFI_16BIT: 687 ready = flash_read16(dst) == flash_read16(src); 688 break; 689 case FLASH_CFI_32BIT: 690 ready = flash_read32(dst) == flash_read32(src); 691 break; 692 case FLASH_CFI_64BIT: 693 ready = flash_read64(dst) == flash_read64(src); 694 break; 695 default: 696 ready = 0; 697 break; 698 } 699 if (ready) 700 break; 701 if (get_timer(start) > tout) { 702 printf("Flash %s timeout at address %lx data %lx\n", 703 prompt, (ulong)dst, (ulong)flash_read8(dst)); 704 return ERR_TIMEOUT; 705 } 706 udelay(1); /* also triggers watchdog */ 707 } 708 #endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */ 709 return ERR_OK; 710 } 711 712 /*----------------------------------------------------------------------- 713 */ 714 static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) 715 { 716 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 717 unsigned short w; 718 unsigned int l; 719 unsigned long long ll; 720 #endif 721 722 switch (info->portwidth) { 723 case FLASH_CFI_8BIT: 724 cword->w8 = c; 725 break; 726 case FLASH_CFI_16BIT: 727 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 728 w = c; 729 w <<= 8; 730 cword->w16 = (cword->w16 >> 8) | w; 731 #else 732 cword->w16 = (cword->w16 << 8) | c; 733 #endif 734 break; 735 case FLASH_CFI_32BIT: 736 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 737 l = c; 738 l <<= 24; 739 cword->w32 = (cword->w32 >> 8) | l; 740 #else 741 cword->w32 = (cword->w32 << 8) | c; 742 #endif 743 break; 744 case FLASH_CFI_64BIT: 745 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 746 ll = c; 747 ll <<= 56; 748 cword->w64 = (cword->w64 >> 8) | ll; 749 #else 750 cword->w64 = (cword->w64 << 8) | c; 751 #endif 752 break; 753 } 754 } 755 756 /* 757 * Loop through the sector table starting from the previously found sector. 758 * Searches forwards or backwards, dependent on the passed address. 759 */ 760 static flash_sect_t find_sector(flash_info_t *info, ulong addr) 761 { 762 static flash_sect_t saved_sector; /* previously found sector */ 763 static flash_info_t *saved_info; /* previously used flash bank */ 764 flash_sect_t sector = saved_sector; 765 766 if (info != saved_info || sector >= info->sector_count) 767 sector = 0; 768 769 while ((sector < info->sector_count - 1) && 770 (info->start[sector] < addr)) 771 sector++; 772 while ((info->start[sector] > addr) && (sector > 0)) 773 /* 774 * also decrements the sector in case of an overshot 775 * in the first loop 776 */ 777 sector--; 778 779 saved_sector = sector; 780 saved_info = info; 781 return sector; 782 } 783 784 /*----------------------------------------------------------------------- 785 */ 786 static int flash_write_cfiword(flash_info_t *info, ulong dest, cfiword_t cword) 787 { 788 void *dstaddr = (void *)dest; 789 int flag; 790 flash_sect_t sect = 0; 791 char sect_found = 0; 792 793 /* Check if Flash is (sufficiently) erased */ 794 switch (info->portwidth) { 795 case FLASH_CFI_8BIT: 796 flag = ((flash_read8(dstaddr) & cword.w8) == cword.w8); 797 break; 798 case FLASH_CFI_16BIT: 799 flag = ((flash_read16(dstaddr) & cword.w16) == cword.w16); 800 break; 801 case FLASH_CFI_32BIT: 802 flag = ((flash_read32(dstaddr) & cword.w32) == cword.w32); 803 break; 804 case FLASH_CFI_64BIT: 805 flag = ((flash_read64(dstaddr) & cword.w64) == cword.w64); 806 break; 807 default: 808 flag = 0; 809 break; 810 } 811 if (!flag) 812 return ERR_NOT_ERASED; 813 814 /* Disable interrupts which might cause a timeout here */ 815 flag = disable_interrupts(); 816 817 switch (info->vendor) { 818 case CFI_CMDSET_INTEL_PROG_REGIONS: 819 case CFI_CMDSET_INTEL_EXTENDED: 820 case CFI_CMDSET_INTEL_STANDARD: 821 flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); 822 flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); 823 break; 824 case CFI_CMDSET_AMD_EXTENDED: 825 case CFI_CMDSET_AMD_STANDARD: 826 sect = find_sector(info, dest); 827 flash_unlock_seq(info, sect); 828 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_WRITE); 829 sect_found = 1; 830 break; 831 #ifdef CONFIG_FLASH_CFI_LEGACY 832 case CFI_CMDSET_AMD_LEGACY: 833 sect = find_sector(info, dest); 834 flash_unlock_seq(info, 0); 835 flash_write_cmd(info, 0, info->addr_unlock1, AMD_CMD_WRITE); 836 sect_found = 1; 837 break; 838 #endif 839 } 840 841 switch (info->portwidth) { 842 case FLASH_CFI_8BIT: 843 flash_write8(cword.w8, dstaddr); 844 break; 845 case FLASH_CFI_16BIT: 846 flash_write16(cword.w16, dstaddr); 847 break; 848 case FLASH_CFI_32BIT: 849 flash_write32(cword.w32, dstaddr); 850 break; 851 case FLASH_CFI_64BIT: 852 flash_write64(cword.w64, dstaddr); 853 break; 854 } 855 856 /* re-enable interrupts if necessary */ 857 if (flag) 858 enable_interrupts(); 859 860 if (!sect_found) 861 sect = find_sector(info, dest); 862 863 if (use_flash_status_poll(info)) 864 return flash_status_poll(info, &cword, dstaddr, 865 info->write_tout, "write"); 866 else 867 return flash_full_status_check(info, sect, 868 info->write_tout, "write"); 869 } 870 871 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 872 873 static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp, 874 int len) 875 { 876 flash_sect_t sector; 877 int cnt; 878 int retcode; 879 u8 *src = cp; 880 u8 *dst = (u8 *)dest; 881 u8 *dst2 = dst; 882 int flag = 1; 883 uint offset = 0; 884 unsigned int shift; 885 uchar write_cmd; 886 887 switch (info->portwidth) { 888 case FLASH_CFI_8BIT: 889 shift = 0; 890 break; 891 case FLASH_CFI_16BIT: 892 shift = 1; 893 break; 894 case FLASH_CFI_32BIT: 895 shift = 2; 896 break; 897 case FLASH_CFI_64BIT: 898 shift = 3; 899 break; 900 default: 901 retcode = ERR_INVAL; 902 goto out_unmap; 903 } 904 905 cnt = len >> shift; 906 907 while ((cnt-- > 0) && (flag == 1)) { 908 switch (info->portwidth) { 909 case FLASH_CFI_8BIT: 910 flag = ((flash_read8(dst2) & flash_read8(src)) == 911 flash_read8(src)); 912 src += 1, dst2 += 1; 913 break; 914 case FLASH_CFI_16BIT: 915 flag = ((flash_read16(dst2) & flash_read16(src)) == 916 flash_read16(src)); 917 src += 2, dst2 += 2; 918 break; 919 case FLASH_CFI_32BIT: 920 flag = ((flash_read32(dst2) & flash_read32(src)) == 921 flash_read32(src)); 922 src += 4, dst2 += 4; 923 break; 924 case FLASH_CFI_64BIT: 925 flag = ((flash_read64(dst2) & flash_read64(src)) == 926 flash_read64(src)); 927 src += 8, dst2 += 8; 928 break; 929 } 930 } 931 if (!flag) { 932 retcode = ERR_NOT_ERASED; 933 goto out_unmap; 934 } 935 936 src = cp; 937 sector = find_sector(info, dest); 938 939 switch (info->vendor) { 940 case CFI_CMDSET_INTEL_PROG_REGIONS: 941 case CFI_CMDSET_INTEL_STANDARD: 942 case CFI_CMDSET_INTEL_EXTENDED: 943 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? 944 FLASH_CMD_WRITE_BUFFER_PROG : 945 FLASH_CMD_WRITE_TO_BUFFER; 946 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); 947 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); 948 flash_write_cmd(info, sector, 0, write_cmd); 949 retcode = flash_status_check(info, sector, 950 info->buffer_write_tout, 951 "write to buffer"); 952 if (retcode == ERR_OK) { 953 /* reduce the number of loops by the width of 954 * the port 955 */ 956 cnt = len >> shift; 957 flash_write_cmd(info, sector, 0, cnt - 1); 958 while (cnt-- > 0) { 959 switch (info->portwidth) { 960 case FLASH_CFI_8BIT: 961 flash_write8(flash_read8(src), dst); 962 src += 1, dst += 1; 963 break; 964 case FLASH_CFI_16BIT: 965 flash_write16(flash_read16(src), dst); 966 src += 2, dst += 2; 967 break; 968 case FLASH_CFI_32BIT: 969 flash_write32(flash_read32(src), dst); 970 src += 4, dst += 4; 971 break; 972 case FLASH_CFI_64BIT: 973 flash_write64(flash_read64(src), dst); 974 src += 8, dst += 8; 975 break; 976 default: 977 retcode = ERR_INVAL; 978 goto out_unmap; 979 } 980 } 981 flash_write_cmd(info, sector, 0, 982 FLASH_CMD_WRITE_BUFFER_CONFIRM); 983 retcode = flash_full_status_check( 984 info, sector, info->buffer_write_tout, 985 "buffer write"); 986 } 987 988 break; 989 990 case CFI_CMDSET_AMD_STANDARD: 991 case CFI_CMDSET_AMD_EXTENDED: 992 flash_unlock_seq(info, sector); 993 994 #ifdef CONFIG_FLASH_SPANSION_S29WS_N 995 offset = ((unsigned long)dst - info->start[sector]) >> shift; 996 #endif 997 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); 998 cnt = len >> shift; 999 flash_write_cmd(info, sector, offset, cnt - 1); 1000 1001 switch (info->portwidth) { 1002 case FLASH_CFI_8BIT: 1003 while (cnt-- > 0) { 1004 flash_write8(flash_read8(src), dst); 1005 src += 1, dst += 1; 1006 } 1007 break; 1008 case FLASH_CFI_16BIT: 1009 while (cnt-- > 0) { 1010 flash_write16(flash_read16(src), dst); 1011 src += 2, dst += 2; 1012 } 1013 break; 1014 case FLASH_CFI_32BIT: 1015 while (cnt-- > 0) { 1016 flash_write32(flash_read32(src), dst); 1017 src += 4, dst += 4; 1018 } 1019 break; 1020 case FLASH_CFI_64BIT: 1021 while (cnt-- > 0) { 1022 flash_write64(flash_read64(src), dst); 1023 src += 8, dst += 8; 1024 } 1025 break; 1026 default: 1027 retcode = ERR_INVAL; 1028 goto out_unmap; 1029 } 1030 1031 flash_write_cmd(info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); 1032 if (use_flash_status_poll(info)) 1033 retcode = flash_status_poll(info, src - (1 << shift), 1034 dst - (1 << shift), 1035 info->buffer_write_tout, 1036 "buffer write"); 1037 else 1038 retcode = flash_full_status_check(info, sector, 1039 info->buffer_write_tout, 1040 "buffer write"); 1041 break; 1042 1043 default: 1044 debug("Unknown Command Set\n"); 1045 retcode = ERR_INVAL; 1046 break; 1047 } 1048 1049 out_unmap: 1050 return retcode; 1051 } 1052 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 1053 1054 /*----------------------------------------------------------------------- 1055 */ 1056 int flash_erase(flash_info_t *info, int s_first, int s_last) 1057 { 1058 int rcode = 0; 1059 int prot; 1060 flash_sect_t sect; 1061 int st; 1062 1063 if (info->flash_id != FLASH_MAN_CFI) { 1064 puts("Can't erase unknown flash type - aborted\n"); 1065 return 1; 1066 } 1067 if (s_first < 0 || s_first > s_last) { 1068 puts("- no sectors to erase\n"); 1069 return 1; 1070 } 1071 1072 prot = 0; 1073 for (sect = s_first; sect <= s_last; ++sect) 1074 if (info->protect[sect]) 1075 prot++; 1076 if (prot) { 1077 printf("- Warning: %d protected sectors will not be erased!\n", 1078 prot); 1079 } else if (flash_verbose) { 1080 putc('\n'); 1081 } 1082 1083 for (sect = s_first; sect <= s_last; sect++) { 1084 if (ctrlc()) { 1085 printf("\n"); 1086 return 1; 1087 } 1088 1089 if (info->protect[sect] == 0) { /* not protected */ 1090 #ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE 1091 int k; 1092 int size; 1093 int erased; 1094 u32 *flash; 1095 1096 /* 1097 * Check if whole sector is erased 1098 */ 1099 size = flash_sector_size(info, sect); 1100 erased = 1; 1101 flash = (u32 *)info->start[sect]; 1102 /* divide by 4 for longword access */ 1103 size = size >> 2; 1104 for (k = 0; k < size; k++) { 1105 if (flash_read32(flash++) != 0xffffffff) { 1106 erased = 0; 1107 break; 1108 } 1109 } 1110 if (erased) { 1111 if (flash_verbose) 1112 putc(','); 1113 continue; 1114 } 1115 #endif 1116 switch (info->vendor) { 1117 case CFI_CMDSET_INTEL_PROG_REGIONS: 1118 case CFI_CMDSET_INTEL_STANDARD: 1119 case CFI_CMDSET_INTEL_EXTENDED: 1120 flash_write_cmd(info, sect, 0, 1121 FLASH_CMD_CLEAR_STATUS); 1122 flash_write_cmd(info, sect, 0, 1123 FLASH_CMD_BLOCK_ERASE); 1124 flash_write_cmd(info, sect, 0, 1125 FLASH_CMD_ERASE_CONFIRM); 1126 break; 1127 case CFI_CMDSET_AMD_STANDARD: 1128 case CFI_CMDSET_AMD_EXTENDED: 1129 flash_unlock_seq(info, sect); 1130 flash_write_cmd(info, sect, 1131 info->addr_unlock1, 1132 AMD_CMD_ERASE_START); 1133 flash_unlock_seq(info, sect); 1134 flash_write_cmd(info, sect, 0, 1135 info->cmd_erase_sector); 1136 break; 1137 #ifdef CONFIG_FLASH_CFI_LEGACY 1138 case CFI_CMDSET_AMD_LEGACY: 1139 flash_unlock_seq(info, 0); 1140 flash_write_cmd(info, 0, info->addr_unlock1, 1141 AMD_CMD_ERASE_START); 1142 flash_unlock_seq(info, 0); 1143 flash_write_cmd(info, sect, 0, 1144 AMD_CMD_ERASE_SECTOR); 1145 break; 1146 #endif 1147 default: 1148 debug("Unknown flash vendor %d\n", 1149 info->vendor); 1150 break; 1151 } 1152 1153 if (use_flash_status_poll(info)) { 1154 cfiword_t cword; 1155 void *dest; 1156 1157 cword.w64 = 0xffffffffffffffffULL; 1158 dest = flash_map(info, sect, 0); 1159 st = flash_status_poll(info, &cword, dest, 1160 info->erase_blk_tout, 1161 "erase"); 1162 flash_unmap(info, sect, 0, dest); 1163 } else { 1164 st = flash_full_status_check(info, sect, 1165 info->erase_blk_tout, 1166 "erase"); 1167 } 1168 1169 if (st) 1170 rcode = 1; 1171 else if (flash_verbose) 1172 putc('.'); 1173 } 1174 } 1175 1176 if (flash_verbose) 1177 puts(" done\n"); 1178 1179 return rcode; 1180 } 1181 1182 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 1183 static int sector_erased(flash_info_t *info, int i) 1184 { 1185 int k; 1186 int size; 1187 u32 *flash; 1188 1189 /* 1190 * Check if whole sector is erased 1191 */ 1192 size = flash_sector_size(info, i); 1193 flash = (u32 *)info->start[i]; 1194 /* divide by 4 for longword access */ 1195 size = size >> 2; 1196 1197 for (k = 0; k < size; k++) { 1198 if (flash_read32(flash++) != 0xffffffff) 1199 return 0; /* not erased */ 1200 } 1201 1202 return 1; /* erased */ 1203 } 1204 #endif /* CONFIG_SYS_FLASH_EMPTY_INFO */ 1205 1206 void flash_print_info(flash_info_t *info) 1207 { 1208 int i; 1209 1210 if (info->flash_id != FLASH_MAN_CFI) { 1211 puts("missing or unknown FLASH type\n"); 1212 return; 1213 } 1214 1215 printf("%s flash (%d x %d)", 1216 info->name, 1217 (info->portwidth << 3), (info->chipwidth << 3)); 1218 if (info->size < 1024 * 1024) 1219 printf(" Size: %ld kB in %d Sectors\n", 1220 info->size >> 10, info->sector_count); 1221 else 1222 printf(" Size: %ld MB in %d Sectors\n", 1223 info->size >> 20, info->sector_count); 1224 printf(" "); 1225 switch (info->vendor) { 1226 case CFI_CMDSET_INTEL_PROG_REGIONS: 1227 printf("Intel Prog Regions"); 1228 break; 1229 case CFI_CMDSET_INTEL_STANDARD: 1230 printf("Intel Standard"); 1231 break; 1232 case CFI_CMDSET_INTEL_EXTENDED: 1233 printf("Intel Extended"); 1234 break; 1235 case CFI_CMDSET_AMD_STANDARD: 1236 printf("AMD Standard"); 1237 break; 1238 case CFI_CMDSET_AMD_EXTENDED: 1239 printf("AMD Extended"); 1240 break; 1241 #ifdef CONFIG_FLASH_CFI_LEGACY 1242 case CFI_CMDSET_AMD_LEGACY: 1243 printf("AMD Legacy"); 1244 break; 1245 #endif 1246 default: 1247 printf("Unknown (%d)", info->vendor); 1248 break; 1249 } 1250 printf(" command set, Manufacturer ID: 0x%02X, Device ID: 0x", 1251 info->manufacturer_id); 1252 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", 1253 info->device_id); 1254 if ((info->device_id & 0xff) == 0x7E) { 1255 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", 1256 info->device_id2); 1257 } 1258 if (info->vendor == CFI_CMDSET_AMD_STANDARD && info->legacy_unlock) 1259 printf("\n Advanced Sector Protection (PPB) enabled"); 1260 printf("\n Erase timeout: %ld ms, write timeout: %ld ms\n", 1261 info->erase_blk_tout, info->write_tout); 1262 if (info->buffer_size > 1) { 1263 printf(" Buffer write timeout: %ld ms, ", 1264 info->buffer_write_tout); 1265 printf("buffer size: %d bytes\n", info->buffer_size); 1266 } 1267 1268 puts("\n Sector Start Addresses:"); 1269 for (i = 0; i < info->sector_count; ++i) { 1270 if (ctrlc()) 1271 break; 1272 if ((i % 5) == 0) 1273 putc('\n'); 1274 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 1275 /* print empty and read-only info */ 1276 printf(" %08lX %c %s ", 1277 info->start[i], 1278 sector_erased(info, i) ? 'E' : ' ', 1279 info->protect[i] ? "RO" : " "); 1280 #else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */ 1281 printf(" %08lX %s ", 1282 info->start[i], 1283 info->protect[i] ? "RO" : " "); 1284 #endif 1285 } 1286 putc('\n'); 1287 } 1288 1289 /*----------------------------------------------------------------------- 1290 * This is used in a few places in write_buf() to show programming 1291 * progress. Making it a function is nasty because it needs to do side 1292 * effect updates to digit and dots. Repeated code is nasty too, so 1293 * we define it once here. 1294 */ 1295 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1296 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ 1297 if (flash_verbose) { \ 1298 dots -= dots_sub; \ 1299 if (scale > 0 && dots <= 0) { \ 1300 if ((digit % 5) == 0) \ 1301 printf("%d", digit / 5); \ 1302 else \ 1303 putc('.'); \ 1304 digit--; \ 1305 dots += scale; \ 1306 } \ 1307 } 1308 #else 1309 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) 1310 #endif 1311 1312 /*----------------------------------------------------------------------- 1313 * Copy memory to flash, returns: 1314 * 0 - OK 1315 * 1 - write timeout 1316 * 2 - Flash not erased 1317 */ 1318 int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) 1319 { 1320 ulong wp; 1321 uchar *p; 1322 int aln; 1323 cfiword_t cword; 1324 int i, rc; 1325 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1326 int buffered_size; 1327 #endif 1328 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1329 int digit = CONFIG_FLASH_SHOW_PROGRESS; 1330 int scale = 0; 1331 int dots = 0; 1332 1333 /* 1334 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. 1335 */ 1336 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { 1337 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / 1338 CONFIG_FLASH_SHOW_PROGRESS); 1339 } 1340 #endif 1341 1342 /* get lower aligned address */ 1343 wp = (addr & ~(info->portwidth - 1)); 1344 1345 /* handle unaligned start */ 1346 aln = addr - wp; 1347 if (aln != 0) { 1348 cword.w32 = 0; 1349 p = (uchar *)wp; 1350 for (i = 0; i < aln; ++i) 1351 flash_add_byte(info, &cword, flash_read8(p + i)); 1352 1353 for (; (i < info->portwidth) && (cnt > 0); i++) { 1354 flash_add_byte(info, &cword, *src++); 1355 cnt--; 1356 } 1357 for (; (cnt == 0) && (i < info->portwidth); ++i) 1358 flash_add_byte(info, &cword, flash_read8(p + i)); 1359 1360 rc = flash_write_cfiword(info, wp, cword); 1361 if (rc != 0) 1362 return rc; 1363 1364 wp += i; 1365 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1366 } 1367 1368 /* handle the aligned part */ 1369 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1370 buffered_size = (info->portwidth / info->chipwidth); 1371 buffered_size *= info->buffer_size; 1372 while (cnt >= info->portwidth) { 1373 /* prohibit buffer write when buffer_size is 1 */ 1374 if (info->buffer_size == 1) { 1375 cword.w32 = 0; 1376 for (i = 0; i < info->portwidth; i++) 1377 flash_add_byte(info, &cword, *src++); 1378 rc = flash_write_cfiword(info, wp, cword); 1379 if (rc != 0) 1380 return rc; 1381 wp += info->portwidth; 1382 cnt -= info->portwidth; 1383 continue; 1384 } 1385 1386 /* write buffer until next buffered_size aligned boundary */ 1387 i = buffered_size - (wp % buffered_size); 1388 if (i > cnt) 1389 i = cnt; 1390 rc = flash_write_cfibuffer(info, wp, src, i); 1391 if (rc != ERR_OK) 1392 return rc; 1393 i -= i & (info->portwidth - 1); 1394 wp += i; 1395 src += i; 1396 cnt -= i; 1397 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1398 /* Only check every once in a while */ 1399 if ((cnt & 0xFFFF) < buffered_size && ctrlc()) 1400 return ERR_ABORTED; 1401 } 1402 #else 1403 while (cnt >= info->portwidth) { 1404 cword.w32 = 0; 1405 for (i = 0; i < info->portwidth; i++) 1406 flash_add_byte(info, &cword, *src++); 1407 rc = flash_write_cfiword(info, wp, cword); 1408 if (rc != 0) 1409 return rc; 1410 wp += info->portwidth; 1411 cnt -= info->portwidth; 1412 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); 1413 /* Only check every once in a while */ 1414 if ((cnt & 0xFFFF) < info->portwidth && ctrlc()) 1415 return ERR_ABORTED; 1416 } 1417 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 1418 1419 if (cnt == 0) 1420 return (0); 1421 1422 /* 1423 * handle unaligned tail bytes 1424 */ 1425 cword.w32 = 0; 1426 p = (uchar *)wp; 1427 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { 1428 flash_add_byte(info, &cword, *src++); 1429 --cnt; 1430 } 1431 for (; i < info->portwidth; ++i) 1432 flash_add_byte(info, &cword, flash_read8(p + i)); 1433 1434 return flash_write_cfiword(info, wp, cword); 1435 } 1436 1437 static inline int manufact_match(flash_info_t *info, u32 manu) 1438 { 1439 return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16); 1440 } 1441 1442 /*----------------------------------------------------------------------- 1443 */ 1444 #ifdef CONFIG_SYS_FLASH_PROTECTION 1445 1446 static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot) 1447 { 1448 if (manufact_match(info, INTEL_MANUFACT) && 1449 info->device_id == NUMONYX_256MBIT) { 1450 /* 1451 * see errata called 1452 * "Numonyx Axcell P33/P30 Specification Update" :) 1453 */ 1454 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_ID); 1455 if (!flash_isequal(info, sector, FLASH_OFFSET_PROTECT, 1456 prot)) { 1457 /* 1458 * cmd must come before FLASH_CMD_PROTECT + 20us 1459 * Disable interrupts which might cause a timeout here. 1460 */ 1461 int flag = disable_interrupts(); 1462 unsigned short cmd; 1463 1464 if (prot) 1465 cmd = FLASH_CMD_PROTECT_SET; 1466 else 1467 cmd = FLASH_CMD_PROTECT_CLEAR; 1468 1469 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); 1470 flash_write_cmd(info, sector, 0, cmd); 1471 /* re-enable interrupts if necessary */ 1472 if (flag) 1473 enable_interrupts(); 1474 } 1475 return 1; 1476 } 1477 return 0; 1478 } 1479 1480 int flash_real_protect(flash_info_t *info, long sector, int prot) 1481 { 1482 int retcode = 0; 1483 1484 switch (info->vendor) { 1485 case CFI_CMDSET_INTEL_PROG_REGIONS: 1486 case CFI_CMDSET_INTEL_STANDARD: 1487 case CFI_CMDSET_INTEL_EXTENDED: 1488 if (!cfi_protect_bugfix(info, sector, prot)) { 1489 flash_write_cmd(info, sector, 0, 1490 FLASH_CMD_CLEAR_STATUS); 1491 flash_write_cmd(info, sector, 0, 1492 FLASH_CMD_PROTECT); 1493 if (prot) 1494 flash_write_cmd(info, sector, 0, 1495 FLASH_CMD_PROTECT_SET); 1496 else 1497 flash_write_cmd(info, sector, 0, 1498 FLASH_CMD_PROTECT_CLEAR); 1499 } 1500 break; 1501 case CFI_CMDSET_AMD_EXTENDED: 1502 case CFI_CMDSET_AMD_STANDARD: 1503 /* U-Boot only checks the first byte */ 1504 if (manufact_match(info, ATM_MANUFACT)) { 1505 if (prot) { 1506 flash_unlock_seq(info, 0); 1507 flash_write_cmd(info, 0, 1508 info->addr_unlock1, 1509 ATM_CMD_SOFTLOCK_START); 1510 flash_unlock_seq(info, 0); 1511 flash_write_cmd(info, sector, 0, 1512 ATM_CMD_LOCK_SECT); 1513 } else { 1514 flash_write_cmd(info, 0, 1515 info->addr_unlock1, 1516 AMD_CMD_UNLOCK_START); 1517 if (info->device_id == ATM_ID_BV6416) 1518 flash_write_cmd(info, sector, 1519 0, ATM_CMD_UNLOCK_SECT); 1520 } 1521 } 1522 if (info->legacy_unlock) { 1523 int flag = disable_interrupts(); 1524 int lock_flag; 1525 1526 flash_unlock_seq(info, 0); 1527 flash_write_cmd(info, 0, info->addr_unlock1, 1528 AMD_CMD_SET_PPB_ENTRY); 1529 lock_flag = flash_isset(info, sector, 0, 0x01); 1530 if (prot) { 1531 if (lock_flag) { 1532 flash_write_cmd(info, sector, 0, 1533 AMD_CMD_PPB_LOCK_BC1); 1534 flash_write_cmd(info, sector, 0, 1535 AMD_CMD_PPB_LOCK_BC2); 1536 } 1537 debug("sector %ld %slocked\n", sector, 1538 lock_flag ? "" : "already "); 1539 } else { 1540 if (!lock_flag) { 1541 debug("unlock %ld\n", sector); 1542 flash_write_cmd(info, 0, 0, 1543 AMD_CMD_PPB_UNLOCK_BC1); 1544 flash_write_cmd(info, 0, 0, 1545 AMD_CMD_PPB_UNLOCK_BC2); 1546 } 1547 debug("sector %ld %sunlocked\n", sector, 1548 !lock_flag ? "" : "already "); 1549 } 1550 if (flag) 1551 enable_interrupts(); 1552 1553 if (flash_status_check(info, sector, 1554 info->erase_blk_tout, 1555 prot ? "protect" : "unprotect")) 1556 printf("status check error\n"); 1557 1558 flash_write_cmd(info, 0, 0, 1559 AMD_CMD_SET_PPB_EXIT_BC1); 1560 flash_write_cmd(info, 0, 0, 1561 AMD_CMD_SET_PPB_EXIT_BC2); 1562 } 1563 break; 1564 #ifdef CONFIG_FLASH_CFI_LEGACY 1565 case CFI_CMDSET_AMD_LEGACY: 1566 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); 1567 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); 1568 if (prot) 1569 flash_write_cmd(info, sector, 0, 1570 FLASH_CMD_PROTECT_SET); 1571 else 1572 flash_write_cmd(info, sector, 0, 1573 FLASH_CMD_PROTECT_CLEAR); 1574 #endif 1575 }; 1576 1577 /* 1578 * Flash needs to be in status register read mode for 1579 * flash_full_status_check() to work correctly 1580 */ 1581 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); 1582 retcode = flash_full_status_check(info, sector, info->erase_blk_tout, 1583 prot ? "protect" : "unprotect"); 1584 if (retcode == 0) { 1585 info->protect[sector] = prot; 1586 1587 /* 1588 * On some of Intel's flash chips (marked via legacy_unlock) 1589 * unprotect unprotects all locking. 1590 */ 1591 if (prot == 0 && info->legacy_unlock) { 1592 flash_sect_t i; 1593 1594 for (i = 0; i < info->sector_count; i++) { 1595 if (info->protect[i]) 1596 flash_real_protect(info, i, 1); 1597 } 1598 } 1599 } 1600 return retcode; 1601 } 1602 1603 /*----------------------------------------------------------------------- 1604 * flash_read_user_serial - read the OneTimeProgramming cells 1605 */ 1606 void flash_read_user_serial(flash_info_t *info, void *buffer, int offset, 1607 int len) 1608 { 1609 uchar *src; 1610 uchar *dst; 1611 1612 dst = buffer; 1613 src = flash_map(info, 0, FLASH_OFFSET_USER_PROTECTION); 1614 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1615 memcpy(dst, src + offset, len); 1616 flash_write_cmd(info, 0, 0, info->cmd_reset); 1617 udelay(1); 1618 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); 1619 } 1620 1621 /* 1622 * flash_read_factory_serial - read the device Id from the protection area 1623 */ 1624 void flash_read_factory_serial(flash_info_t *info, void *buffer, int offset, 1625 int len) 1626 { 1627 uchar *src; 1628 1629 src = flash_map(info, 0, FLASH_OFFSET_INTEL_PROTECTION); 1630 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1631 memcpy(buffer, src + offset, len); 1632 flash_write_cmd(info, 0, 0, info->cmd_reset); 1633 udelay(1); 1634 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); 1635 } 1636 1637 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 1638 1639 /*----------------------------------------------------------------------- 1640 * Reverse the order of the erase regions in the CFI QRY structure. 1641 * This is needed for chips that are either a) correctly detected as 1642 * top-boot, or b) buggy. 1643 */ 1644 static void cfi_reverse_geometry(struct cfi_qry *qry) 1645 { 1646 unsigned int i, j; 1647 u32 tmp; 1648 1649 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { 1650 tmp = get_unaligned(&qry->erase_region_info[i]); 1651 put_unaligned(get_unaligned(&qry->erase_region_info[j]), 1652 &qry->erase_region_info[i]); 1653 put_unaligned(tmp, &qry->erase_region_info[j]); 1654 } 1655 } 1656 1657 /*----------------------------------------------------------------------- 1658 * read jedec ids from device and set corresponding fields in info struct 1659 * 1660 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct 1661 * 1662 */ 1663 static void cmdset_intel_read_jedec_ids(flash_info_t *info) 1664 { 1665 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1666 udelay(1); 1667 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1668 udelay(1000); /* some flash are slow to respond */ 1669 info->manufacturer_id = flash_read_uchar(info, 1670 FLASH_OFFSET_MANUFACTURER_ID); 1671 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ? 1672 flash_read_word(info, FLASH_OFFSET_DEVICE_ID) : 1673 flash_read_uchar(info, FLASH_OFFSET_DEVICE_ID); 1674 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1675 } 1676 1677 static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) 1678 { 1679 info->cmd_reset = FLASH_CMD_RESET; 1680 1681 cmdset_intel_read_jedec_ids(info); 1682 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1683 1684 #ifdef CONFIG_SYS_FLASH_PROTECTION 1685 /* read legacy lock/unlock bit from intel flash */ 1686 if (info->ext_addr) { 1687 info->legacy_unlock = 1688 flash_read_uchar(info, info->ext_addr + 5) & 0x08; 1689 } 1690 #endif 1691 1692 return 0; 1693 } 1694 1695 static void cmdset_amd_read_jedec_ids(flash_info_t *info) 1696 { 1697 ushort bank_id = 0; 1698 uchar manu_id; 1699 uchar feature; 1700 1701 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1702 flash_unlock_seq(info, 0); 1703 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); 1704 udelay(1000); /* some flash are slow to respond */ 1705 1706 manu_id = flash_read_uchar(info, FLASH_OFFSET_MANUFACTURER_ID); 1707 /* JEDEC JEP106Z specifies ID codes up to bank 7 */ 1708 while (manu_id == FLASH_CONTINUATION_CODE && bank_id < 0x800) { 1709 bank_id += 0x100; 1710 manu_id = flash_read_uchar(info, 1711 bank_id | FLASH_OFFSET_MANUFACTURER_ID); 1712 } 1713 info->manufacturer_id = manu_id; 1714 1715 debug("info->ext_addr = 0x%x, cfi_version = 0x%x\n", 1716 info->ext_addr, info->cfi_version); 1717 if (info->ext_addr && info->cfi_version >= 0x3134) { 1718 /* read software feature (at 0x53) */ 1719 feature = flash_read_uchar(info, info->ext_addr + 0x13); 1720 debug("feature = 0x%x\n", feature); 1721 info->sr_supported = feature & 0x1; 1722 } 1723 1724 switch (info->chipwidth) { 1725 case FLASH_CFI_8BIT: 1726 info->device_id = flash_read_uchar(info, 1727 FLASH_OFFSET_DEVICE_ID); 1728 if (info->device_id == 0x7E) { 1729 /* AMD 3-byte (expanded) device ids */ 1730 info->device_id2 = flash_read_uchar(info, 1731 FLASH_OFFSET_DEVICE_ID2); 1732 info->device_id2 <<= 8; 1733 info->device_id2 |= flash_read_uchar(info, 1734 FLASH_OFFSET_DEVICE_ID3); 1735 } 1736 break; 1737 case FLASH_CFI_16BIT: 1738 info->device_id = flash_read_word(info, 1739 FLASH_OFFSET_DEVICE_ID); 1740 if ((info->device_id & 0xff) == 0x7E) { 1741 /* AMD 3-byte (expanded) device ids */ 1742 info->device_id2 = flash_read_uchar(info, 1743 FLASH_OFFSET_DEVICE_ID2); 1744 info->device_id2 <<= 8; 1745 info->device_id2 |= flash_read_uchar(info, 1746 FLASH_OFFSET_DEVICE_ID3); 1747 } 1748 break; 1749 default: 1750 break; 1751 } 1752 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1753 udelay(1); 1754 } 1755 1756 static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) 1757 { 1758 info->cmd_reset = AMD_CMD_RESET; 1759 info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR; 1760 1761 cmdset_amd_read_jedec_ids(info); 1762 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1763 1764 #ifdef CONFIG_SYS_FLASH_PROTECTION 1765 if (info->ext_addr) { 1766 /* read sector protect/unprotect scheme (at 0x49) */ 1767 if (flash_read_uchar(info, info->ext_addr + 9) == 0x8) 1768 info->legacy_unlock = 1; 1769 } 1770 #endif 1771 1772 return 0; 1773 } 1774 1775 #ifdef CONFIG_FLASH_CFI_LEGACY 1776 static void flash_read_jedec_ids(flash_info_t *info) 1777 { 1778 info->manufacturer_id = 0; 1779 info->device_id = 0; 1780 info->device_id2 = 0; 1781 1782 switch (info->vendor) { 1783 case CFI_CMDSET_INTEL_PROG_REGIONS: 1784 case CFI_CMDSET_INTEL_STANDARD: 1785 case CFI_CMDSET_INTEL_EXTENDED: 1786 cmdset_intel_read_jedec_ids(info); 1787 break; 1788 case CFI_CMDSET_AMD_STANDARD: 1789 case CFI_CMDSET_AMD_EXTENDED: 1790 cmdset_amd_read_jedec_ids(info); 1791 break; 1792 default: 1793 break; 1794 } 1795 } 1796 1797 /*----------------------------------------------------------------------- 1798 * Call board code to request info about non-CFI flash. 1799 * board_flash_get_legacy needs to fill in at least: 1800 * info->portwidth, info->chipwidth and info->interface for Jedec probing. 1801 */ 1802 static int flash_detect_legacy(phys_addr_t base, int banknum) 1803 { 1804 flash_info_t *info = &flash_info[banknum]; 1805 1806 if (board_flash_get_legacy(base, banknum, info)) { 1807 /* board code may have filled info completely. If not, we 1808 * use JEDEC ID probing. 1809 */ 1810 if (!info->vendor) { 1811 int modes[] = { 1812 CFI_CMDSET_AMD_STANDARD, 1813 CFI_CMDSET_INTEL_STANDARD 1814 }; 1815 int i; 1816 1817 for (i = 0; i < ARRAY_SIZE(modes); i++) { 1818 info->vendor = modes[i]; 1819 info->start[0] = 1820 (ulong)map_physmem(base, 1821 info->portwidth, 1822 MAP_NOCACHE); 1823 if (info->portwidth == FLASH_CFI_8BIT && 1824 info->interface == FLASH_CFI_X8X16) { 1825 info->addr_unlock1 = 0x2AAA; 1826 info->addr_unlock2 = 0x5555; 1827 } else { 1828 info->addr_unlock1 = 0x5555; 1829 info->addr_unlock2 = 0x2AAA; 1830 } 1831 flash_read_jedec_ids(info); 1832 debug("JEDEC PROBE: ID %x %x %x\n", 1833 info->manufacturer_id, 1834 info->device_id, 1835 info->device_id2); 1836 if (jedec_flash_match(info, info->start[0])) 1837 break; 1838 1839 unmap_physmem((void *)info->start[0], 1840 info->portwidth); 1841 } 1842 } 1843 1844 switch (info->vendor) { 1845 case CFI_CMDSET_INTEL_PROG_REGIONS: 1846 case CFI_CMDSET_INTEL_STANDARD: 1847 case CFI_CMDSET_INTEL_EXTENDED: 1848 info->cmd_reset = FLASH_CMD_RESET; 1849 break; 1850 case CFI_CMDSET_AMD_STANDARD: 1851 case CFI_CMDSET_AMD_EXTENDED: 1852 case CFI_CMDSET_AMD_LEGACY: 1853 info->cmd_reset = AMD_CMD_RESET; 1854 break; 1855 } 1856 info->flash_id = FLASH_MAN_CFI; 1857 return 1; 1858 } 1859 return 0; /* use CFI */ 1860 } 1861 #else 1862 static inline int flash_detect_legacy(phys_addr_t base, int banknum) 1863 { 1864 return 0; /* use CFI */ 1865 } 1866 #endif 1867 1868 /*----------------------------------------------------------------------- 1869 * detect if flash is compatible with the Common Flash Interface (CFI) 1870 * http://www.jedec.org/download/search/jesd68.pdf 1871 */ 1872 static void flash_read_cfi(flash_info_t *info, void *buf, unsigned int start, 1873 size_t len) 1874 { 1875 u8 *p = buf; 1876 unsigned int i; 1877 1878 for (i = 0; i < len; i++) 1879 p[i] = flash_read_uchar(info, start + i); 1880 } 1881 1882 static void __flash_cmd_reset(flash_info_t *info) 1883 { 1884 /* 1885 * We do not yet know what kind of commandset to use, so we issue 1886 * the reset command in both Intel and AMD variants, in the hope 1887 * that AMD flash roms ignore the Intel command. 1888 */ 1889 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1890 udelay(1); 1891 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1892 } 1893 1894 void flash_cmd_reset(flash_info_t *info) 1895 __attribute__((weak, alias("__flash_cmd_reset"))); 1896 1897 static int __flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry) 1898 { 1899 int cfi_offset; 1900 1901 /* Issue FLASH reset command */ 1902 flash_cmd_reset(info); 1903 1904 for (cfi_offset = 0; cfi_offset < ARRAY_SIZE(flash_offset_cfi); 1905 cfi_offset++) { 1906 flash_write_cmd(info, 0, flash_offset_cfi[cfi_offset], 1907 FLASH_CMD_CFI); 1908 if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && 1909 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && 1910 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { 1911 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, 1912 sizeof(struct cfi_qry)); 1913 info->interface = le16_to_cpu(qry->interface_desc); 1914 1915 info->cfi_offset = flash_offset_cfi[cfi_offset]; 1916 debug("device interface is %d\n", 1917 info->interface); 1918 debug("found port %d chip %d ", 1919 info->portwidth, info->chipwidth); 1920 debug("port %d bits chip %d bits\n", 1921 info->portwidth << CFI_FLASH_SHIFT_WIDTH, 1922 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 1923 1924 /* calculate command offsets as in the Linux driver */ 1925 info->addr_unlock1 = 0x555; 1926 info->addr_unlock2 = 0x2aa; 1927 1928 /* 1929 * modify the unlock address if we are 1930 * in compatibility mode 1931 */ 1932 if (/* x8/x16 in x8 mode */ 1933 (info->chipwidth == FLASH_CFI_BY8 && 1934 info->interface == FLASH_CFI_X8X16) || 1935 /* x16/x32 in x16 mode */ 1936 (info->chipwidth == FLASH_CFI_BY16 && 1937 info->interface == FLASH_CFI_X16X32)) { 1938 info->addr_unlock1 = 0xaaa; 1939 info->addr_unlock2 = 0x555; 1940 } 1941 1942 info->name = "CFI conformant"; 1943 return 1; 1944 } 1945 } 1946 1947 return 0; 1948 } 1949 1950 static int flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry) 1951 { 1952 debug("flash detect cfi\n"); 1953 1954 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; 1955 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { 1956 for (info->chipwidth = FLASH_CFI_BY8; 1957 info->chipwidth <= info->portwidth; 1958 info->chipwidth <<= 1) 1959 if (__flash_detect_cfi(info, qry)) 1960 return 1; 1961 } 1962 debug("not found\n"); 1963 return 0; 1964 } 1965 1966 /* 1967 * Manufacturer-specific quirks. Add workarounds for geometry 1968 * reversal, etc. here. 1969 */ 1970 static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) 1971 { 1972 /* check if flash geometry needs reversal */ 1973 if (qry->num_erase_regions > 1) { 1974 /* reverse geometry if top boot part */ 1975 if (info->cfi_version < 0x3131) { 1976 /* CFI < 1.1, try to guess from device id */ 1977 if ((info->device_id & 0x80) != 0) 1978 cfi_reverse_geometry(qry); 1979 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 1980 /* CFI >= 1.1, deduct from top/bottom flag */ 1981 /* note: ext_addr is valid since cfi_version > 0 */ 1982 cfi_reverse_geometry(qry); 1983 } 1984 } 1985 } 1986 1987 static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) 1988 { 1989 int reverse_geometry = 0; 1990 1991 /* Check the "top boot" bit in the PRI */ 1992 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) 1993 reverse_geometry = 1; 1994 1995 /* AT49BV6416(T) list the erase regions in the wrong order. 1996 * However, the device ID is identical with the non-broken 1997 * AT49BV642D they differ in the high byte. 1998 */ 1999 if (info->device_id == 0xd6 || info->device_id == 0xd2) 2000 reverse_geometry = !reverse_geometry; 2001 2002 if (reverse_geometry) 2003 cfi_reverse_geometry(qry); 2004 } 2005 2006 static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) 2007 { 2008 /* check if flash geometry needs reversal */ 2009 if (qry->num_erase_regions > 1) { 2010 /* reverse geometry if top boot part */ 2011 if (info->cfi_version < 0x3131) { 2012 /* CFI < 1.1, guess by device id */ 2013 if (info->device_id == 0x22CA || /* M29W320DT */ 2014 info->device_id == 0x2256 || /* M29W320ET */ 2015 info->device_id == 0x22D7) { /* M29W800DT */ 2016 cfi_reverse_geometry(qry); 2017 } 2018 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 2019 /* CFI >= 1.1, deduct from top/bottom flag */ 2020 /* note: ext_addr is valid since cfi_version > 0 */ 2021 cfi_reverse_geometry(qry); 2022 } 2023 } 2024 } 2025 2026 static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry) 2027 { 2028 /* 2029 * SST, for many recent nor parallel flashes, says they are 2030 * CFI-conformant. This is not true, since qry struct. 2031 * reports a std. AMD command set (0x0002), while SST allows to 2032 * erase two different sector sizes for the same memory. 2033 * 64KB sector (SST call it block) needs 0x30 to be erased. 2034 * 4KB sector (SST call it sector) needs 0x50 to be erased. 2035 * Since CFI query detect the 4KB number of sectors, users expects 2036 * a sector granularity of 4KB, and it is here set. 2037 */ 2038 if (info->device_id == 0x5D23 || /* SST39VF3201B */ 2039 info->device_id == 0x5C23) { /* SST39VF3202B */ 2040 /* set sector granularity to 4KB */ 2041 info->cmd_erase_sector = 0x50; 2042 } 2043 } 2044 2045 static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry) 2046 { 2047 /* 2048 * The M29EW devices seem to report the CFI information wrong 2049 * when it's in 8 bit mode. 2050 * There's an app note from Numonyx on this issue. 2051 * So adjust the buffer size for M29EW while operating in 8-bit mode 2052 */ 2053 if (qry->max_buf_write_size > 0x8 && 2054 info->device_id == 0x7E && 2055 (info->device_id2 == 0x2201 || 2056 info->device_id2 == 0x2301 || 2057 info->device_id2 == 0x2801 || 2058 info->device_id2 == 0x4801)) { 2059 debug("Adjusted buffer size on Numonyx flash"); 2060 debug(" M29EW family in 8 bit mode\n"); 2061 qry->max_buf_write_size = 0x8; 2062 } 2063 } 2064 2065 /* 2066 * The following code cannot be run from FLASH! 2067 * 2068 */ 2069 ulong flash_get_size(phys_addr_t base, int banknum) 2070 { 2071 flash_info_t *info = &flash_info[banknum]; 2072 int i, j; 2073 flash_sect_t sect_cnt; 2074 phys_addr_t sector; 2075 unsigned long tmp; 2076 int size_ratio; 2077 uchar num_erase_regions; 2078 int erase_region_size; 2079 int erase_region_count; 2080 struct cfi_qry qry; 2081 unsigned long max_size; 2082 2083 memset(&qry, 0, sizeof(qry)); 2084 2085 info->ext_addr = 0; 2086 info->cfi_version = 0; 2087 #ifdef CONFIG_SYS_FLASH_PROTECTION 2088 info->legacy_unlock = 0; 2089 #endif 2090 2091 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE); 2092 2093 if (flash_detect_cfi(info, &qry)) { 2094 info->vendor = le16_to_cpu(get_unaligned(&qry.p_id)); 2095 info->ext_addr = le16_to_cpu(get_unaligned(&qry.p_adr)); 2096 num_erase_regions = qry.num_erase_regions; 2097 2098 if (info->ext_addr) { 2099 info->cfi_version = (ushort)flash_read_uchar(info, 2100 info->ext_addr + 3) << 8; 2101 info->cfi_version |= (ushort)flash_read_uchar(info, 2102 info->ext_addr + 4); 2103 } 2104 2105 #ifdef DEBUG 2106 flash_printqry(&qry); 2107 #endif 2108 2109 switch (info->vendor) { 2110 case CFI_CMDSET_INTEL_PROG_REGIONS: 2111 case CFI_CMDSET_INTEL_STANDARD: 2112 case CFI_CMDSET_INTEL_EXTENDED: 2113 cmdset_intel_init(info, &qry); 2114 break; 2115 case CFI_CMDSET_AMD_STANDARD: 2116 case CFI_CMDSET_AMD_EXTENDED: 2117 cmdset_amd_init(info, &qry); 2118 break; 2119 default: 2120 printf("CFI: Unknown command set 0x%x\n", 2121 info->vendor); 2122 /* 2123 * Unfortunately, this means we don't know how 2124 * to get the chip back to Read mode. Might 2125 * as well try an Intel-style reset... 2126 */ 2127 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 2128 return 0; 2129 } 2130 2131 /* Do manufacturer-specific fixups */ 2132 switch (info->manufacturer_id) { 2133 case 0x0001: /* AMD */ 2134 case 0x0037: /* AMIC */ 2135 flash_fixup_amd(info, &qry); 2136 break; 2137 case 0x001f: 2138 flash_fixup_atmel(info, &qry); 2139 break; 2140 case 0x0020: 2141 flash_fixup_stm(info, &qry); 2142 break; 2143 case 0x00bf: /* SST */ 2144 flash_fixup_sst(info, &qry); 2145 break; 2146 case 0x0089: /* Numonyx */ 2147 flash_fixup_num(info, &qry); 2148 break; 2149 } 2150 2151 debug("manufacturer is %d\n", info->vendor); 2152 debug("manufacturer id is 0x%x\n", info->manufacturer_id); 2153 debug("device id is 0x%x\n", info->device_id); 2154 debug("device id2 is 0x%x\n", info->device_id2); 2155 debug("cfi version is 0x%04x\n", info->cfi_version); 2156 2157 size_ratio = info->portwidth / info->chipwidth; 2158 /* if the chip is x8/x16 reduce the ratio by half */ 2159 if (info->interface == FLASH_CFI_X8X16 && 2160 info->chipwidth == FLASH_CFI_BY8) { 2161 size_ratio >>= 1; 2162 } 2163 debug("size_ratio %d port %d bits chip %d bits\n", 2164 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, 2165 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 2166 info->size = 1 << qry.dev_size; 2167 /* multiply the size by the number of chips */ 2168 info->size *= size_ratio; 2169 max_size = cfi_flash_bank_size(banknum); 2170 if (max_size && info->size > max_size) { 2171 debug("[truncated from %ldMiB]", info->size >> 20); 2172 info->size = max_size; 2173 } 2174 debug("found %d erase regions\n", num_erase_regions); 2175 sect_cnt = 0; 2176 sector = base; 2177 for (i = 0; i < num_erase_regions; i++) { 2178 if (i > NUM_ERASE_REGIONS) { 2179 printf("%d erase regions found, only %d used\n", 2180 num_erase_regions, NUM_ERASE_REGIONS); 2181 break; 2182 } 2183 2184 tmp = le32_to_cpu(get_unaligned( 2185 &qry.erase_region_info[i])); 2186 debug("erase region %u: 0x%08lx\n", i, tmp); 2187 2188 erase_region_count = (tmp & 0xffff) + 1; 2189 tmp >>= 16; 2190 erase_region_size = 2191 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; 2192 debug("erase_region_count = %d ", erase_region_count); 2193 debug("erase_region_size = %d\n", erase_region_size); 2194 for (j = 0; j < erase_region_count; j++) { 2195 if (sector - base >= info->size) 2196 break; 2197 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { 2198 printf("ERROR: too many flash sectors\n"); 2199 break; 2200 } 2201 info->start[sect_cnt] = 2202 (ulong)map_physmem(sector, 2203 info->portwidth, 2204 MAP_NOCACHE); 2205 sector += (erase_region_size * size_ratio); 2206 2207 /* 2208 * Only read protection status from 2209 * supported devices (intel...) 2210 */ 2211 switch (info->vendor) { 2212 case CFI_CMDSET_INTEL_PROG_REGIONS: 2213 case CFI_CMDSET_INTEL_EXTENDED: 2214 case CFI_CMDSET_INTEL_STANDARD: 2215 /* 2216 * Set flash to read-id mode. Otherwise 2217 * reading protected status is not 2218 * guaranteed. 2219 */ 2220 flash_write_cmd(info, sect_cnt, 0, 2221 FLASH_CMD_READ_ID); 2222 info->protect[sect_cnt] = 2223 flash_isset(info, sect_cnt, 2224 FLASH_OFFSET_PROTECT, 2225 FLASH_STATUS_PROTECT); 2226 flash_write_cmd(info, sect_cnt, 0, 2227 FLASH_CMD_RESET); 2228 break; 2229 case CFI_CMDSET_AMD_EXTENDED: 2230 case CFI_CMDSET_AMD_STANDARD: 2231 if (!info->legacy_unlock) { 2232 /* default: not protected */ 2233 info->protect[sect_cnt] = 0; 2234 break; 2235 } 2236 2237 /* Read protection (PPB) from sector */ 2238 flash_write_cmd(info, 0, 0, 2239 info->cmd_reset); 2240 flash_unlock_seq(info, 0); 2241 flash_write_cmd(info, 0, 2242 info->addr_unlock1, 2243 FLASH_CMD_READ_ID); 2244 info->protect[sect_cnt] = 2245 flash_isset( 2246 info, sect_cnt, 2247 FLASH_OFFSET_PROTECT, 2248 FLASH_STATUS_PROTECT); 2249 break; 2250 default: 2251 /* default: not protected */ 2252 info->protect[sect_cnt] = 0; 2253 } 2254 2255 sect_cnt++; 2256 } 2257 } 2258 2259 info->sector_count = sect_cnt; 2260 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); 2261 tmp = 1 << qry.block_erase_timeout_typ; 2262 info->erase_blk_tout = tmp * 2263 (1 << qry.block_erase_timeout_max); 2264 tmp = (1 << qry.buf_write_timeout_typ) * 2265 (1 << qry.buf_write_timeout_max); 2266 2267 /* round up when converting to ms */ 2268 info->buffer_write_tout = (tmp + 999) / 1000; 2269 tmp = (1 << qry.word_write_timeout_typ) * 2270 (1 << qry.word_write_timeout_max); 2271 /* round up when converting to ms */ 2272 info->write_tout = (tmp + 999) / 1000; 2273 info->flash_id = FLASH_MAN_CFI; 2274 if (info->interface == FLASH_CFI_X8X16 && 2275 info->chipwidth == FLASH_CFI_BY8) { 2276 /* XXX - Need to test on x8/x16 in parallel. */ 2277 info->portwidth >>= 1; 2278 } 2279 2280 flash_write_cmd(info, 0, 0, info->cmd_reset); 2281 } 2282 2283 return (info->size); 2284 } 2285 2286 #ifdef CONFIG_FLASH_CFI_MTD 2287 void flash_set_verbose(uint v) 2288 { 2289 flash_verbose = v; 2290 } 2291 #endif 2292 2293 static void cfi_flash_set_config_reg(u32 base, u16 val) 2294 { 2295 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS 2296 /* 2297 * Only set this config register if really defined 2298 * to a valid value (0xffff is invalid) 2299 */ 2300 if (val == 0xffff) 2301 return; 2302 2303 /* 2304 * Set configuration register. Data is "encrypted" in the 16 lower 2305 * address bits. 2306 */ 2307 flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1))); 2308 flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1))); 2309 2310 /* 2311 * Finally issue reset-command to bring device back to 2312 * read-array mode 2313 */ 2314 flash_write16(FLASH_CMD_RESET, (void *)base); 2315 #endif 2316 } 2317 2318 /*----------------------------------------------------------------------- 2319 */ 2320 2321 static void flash_protect_default(void) 2322 { 2323 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) 2324 int i; 2325 struct apl_s { 2326 ulong start; 2327 ulong size; 2328 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST; 2329 #endif 2330 2331 /* Monitor protection ON by default */ 2332 #if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ 2333 (!defined(CONFIG_MONITOR_IS_IN_RAM)) 2334 flash_protect(FLAG_PROTECT_SET, 2335 CONFIG_SYS_MONITOR_BASE, 2336 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, 2337 flash_get_info(CONFIG_SYS_MONITOR_BASE)); 2338 #endif 2339 2340 /* Environment protection ON by default */ 2341 #ifdef CONFIG_ENV_IS_IN_FLASH 2342 flash_protect(FLAG_PROTECT_SET, 2343 CONFIG_ENV_ADDR, 2344 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, 2345 flash_get_info(CONFIG_ENV_ADDR)); 2346 #endif 2347 2348 /* Redundant environment protection ON by default */ 2349 #ifdef CONFIG_ENV_ADDR_REDUND 2350 flash_protect(FLAG_PROTECT_SET, 2351 CONFIG_ENV_ADDR_REDUND, 2352 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, 2353 flash_get_info(CONFIG_ENV_ADDR_REDUND)); 2354 #endif 2355 2356 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) 2357 for (i = 0; i < ARRAY_SIZE(apl); i++) { 2358 debug("autoprotecting from %08lx to %08lx\n", 2359 apl[i].start, apl[i].start + apl[i].size - 1); 2360 flash_protect(FLAG_PROTECT_SET, 2361 apl[i].start, 2362 apl[i].start + apl[i].size - 1, 2363 flash_get_info(apl[i].start)); 2364 } 2365 #endif 2366 } 2367 2368 unsigned long flash_init(void) 2369 { 2370 unsigned long size = 0; 2371 int i; 2372 2373 #ifdef CONFIG_SYS_FLASH_PROTECTION 2374 /* read environment from EEPROM */ 2375 char s[64]; 2376 2377 env_get_f("unlock", s, sizeof(s)); 2378 #endif 2379 2380 #ifdef CONFIG_CFI_FLASH /* for driver model */ 2381 cfi_flash_init_dm(); 2382 #endif 2383 2384 /* Init: no FLASHes known */ 2385 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { 2386 flash_info[i].flash_id = FLASH_UNKNOWN; 2387 2388 /* Optionally write flash configuration register */ 2389 cfi_flash_set_config_reg(cfi_flash_bank_addr(i), 2390 cfi_flash_config_reg(i)); 2391 2392 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) 2393 flash_get_size(cfi_flash_bank_addr(i), i); 2394 size += flash_info[i].size; 2395 if (flash_info[i].flash_id == FLASH_UNKNOWN) { 2396 #ifndef CONFIG_SYS_FLASH_QUIET_TEST 2397 printf("## Unknown flash on Bank %d ", i + 1); 2398 printf("- Size = 0x%08lx = %ld MB\n", 2399 flash_info[i].size, 2400 flash_info[i].size >> 20); 2401 #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ 2402 } 2403 #ifdef CONFIG_SYS_FLASH_PROTECTION 2404 else if (strcmp(s, "yes") == 0) { 2405 /* 2406 * Only the U-Boot image and it's environment 2407 * is protected, all other sectors are 2408 * unprotected (unlocked) if flash hardware 2409 * protection is used (CONFIG_SYS_FLASH_PROTECTION) 2410 * and the environment variable "unlock" is 2411 * set to "yes". 2412 */ 2413 if (flash_info[i].legacy_unlock) { 2414 int k; 2415 2416 /* 2417 * Disable legacy_unlock temporarily, 2418 * since flash_real_protect would 2419 * relock all other sectors again 2420 * otherwise. 2421 */ 2422 flash_info[i].legacy_unlock = 0; 2423 2424 /* 2425 * Legacy unlocking (e.g. Intel J3) -> 2426 * unlock only one sector. This will 2427 * unlock all sectors. 2428 */ 2429 flash_real_protect(&flash_info[i], 0, 0); 2430 2431 flash_info[i].legacy_unlock = 1; 2432 2433 /* 2434 * Manually mark other sectors as 2435 * unlocked (unprotected) 2436 */ 2437 for (k = 1; k < flash_info[i].sector_count; k++) 2438 flash_info[i].protect[k] = 0; 2439 } else { 2440 /* 2441 * No legancy unlocking -> unlock all sectors 2442 */ 2443 flash_protect(FLAG_PROTECT_CLEAR, 2444 flash_info[i].start[0], 2445 flash_info[i].start[0] 2446 + flash_info[i].size - 1, 2447 &flash_info[i]); 2448 } 2449 } 2450 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 2451 } 2452 2453 flash_protect_default(); 2454 #ifdef CONFIG_FLASH_CFI_MTD 2455 cfi_mtd_init(); 2456 #endif 2457 2458 return (size); 2459 } 2460 2461 #ifdef CONFIG_CFI_FLASH /* for driver model */ 2462 static int cfi_flash_probe(struct udevice *dev) 2463 { 2464 void *blob = (void *)gd->fdt_blob; 2465 int node = dev_of_offset(dev); 2466 const fdt32_t *cell; 2467 phys_addr_t addr; 2468 int parent, addrc, sizec; 2469 int len, idx; 2470 2471 parent = fdt_parent_offset(blob, node); 2472 fdt_support_default_count_cells(blob, parent, &addrc, &sizec); 2473 /* decode regs, there may be multiple reg tuples. */ 2474 cell = fdt_getprop(blob, node, "reg", &len); 2475 if (!cell) 2476 return -ENOENT; 2477 idx = 0; 2478 len /= sizeof(fdt32_t); 2479 while (idx < len) { 2480 addr = fdt_translate_address((void *)blob, 2481 node, cell + idx); 2482 flash_info[cfi_flash_num_flash_banks].dev = dev; 2483 flash_info[cfi_flash_num_flash_banks].base = addr; 2484 cfi_flash_num_flash_banks++; 2485 idx += addrc + sizec; 2486 } 2487 gd->bd->bi_flashstart = flash_info[0].base; 2488 2489 return 0; 2490 } 2491 2492 static const struct udevice_id cfi_flash_ids[] = { 2493 { .compatible = "cfi-flash" }, 2494 { .compatible = "jedec-flash" }, 2495 {} 2496 }; 2497 2498 U_BOOT_DRIVER(cfi_flash) = { 2499 .name = "cfi_flash", 2500 .id = UCLASS_MTD, 2501 .of_match = cfi_flash_ids, 2502 .probe = cfi_flash_probe, 2503 }; 2504 #endif /* CONFIG_CFI_FLASH */ 2505