1 /* 2 * (C) Copyright 2002-2004 3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com 4 * 5 * Copyright (C) 2003 Arabella Software Ltd. 6 * Yuli Barcohen <yuli@arabellasw.com> 7 * 8 * Copyright (C) 2004 9 * Ed Okerson 10 * 11 * Copyright (C) 2006 12 * Tolunay Orkun <listmember@orkun.us> 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 * 32 */ 33 34 /* The DEBUG define must be before common to enable debugging */ 35 /* #define DEBUG */ 36 37 #include <common.h> 38 #include <asm/processor.h> 39 #include <asm/io.h> 40 #include <asm/byteorder.h> 41 #include <environment.h> 42 #include <mtd/cfi_flash.h> 43 44 /* 45 * This file implements a Common Flash Interface (CFI) driver for 46 * U-Boot. 47 * 48 * The width of the port and the width of the chips are determined at 49 * initialization. These widths are used to calculate the address for 50 * access CFI data structures. 51 * 52 * References 53 * JEDEC Standard JESD68 - Common Flash Interface (CFI) 54 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes 55 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets 56 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet 57 * AMD CFI Specification, Release 2.0 December 1, 2001 58 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte 59 * Device IDs, Publication Number 25538 Revision A, November 8, 2001 60 * 61 * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between 62 * reading and writing ... (yes there is such a Hardware). 63 */ 64 65 static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; 66 #ifdef CONFIG_FLASH_CFI_MTD 67 static uint flash_verbose = 1; 68 #else 69 #define flash_verbose 1 70 #endif 71 72 flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ 73 74 /* 75 * Check if chip width is defined. If not, start detecting with 8bit. 76 */ 77 #ifndef CONFIG_SYS_FLASH_CFI_WIDTH 78 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT 79 #endif 80 81 /* 82 * 0xffff is an undefined value for the configuration register. When 83 * this value is returned, the configuration register shall not be 84 * written at all (default mode). 85 */ 86 static u16 cfi_flash_config_reg(int i) 87 { 88 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS 89 return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i]; 90 #else 91 return 0xffff; 92 #endif 93 } 94 95 #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) 96 int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; 97 #endif 98 99 static phys_addr_t __cfi_flash_bank_addr(int i) 100 { 101 return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; 102 } 103 phys_addr_t cfi_flash_bank_addr(int i) 104 __attribute__((weak, alias("__cfi_flash_bank_addr"))); 105 106 static unsigned long __cfi_flash_bank_size(int i) 107 { 108 #ifdef CONFIG_SYS_FLASH_BANKS_SIZES 109 return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; 110 #else 111 return 0; 112 #endif 113 } 114 unsigned long cfi_flash_bank_size(int i) 115 __attribute__((weak, alias("__cfi_flash_bank_size"))); 116 117 static void __flash_write8(u8 value, void *addr) 118 { 119 __raw_writeb(value, addr); 120 } 121 122 static void __flash_write16(u16 value, void *addr) 123 { 124 __raw_writew(value, addr); 125 } 126 127 static void __flash_write32(u32 value, void *addr) 128 { 129 __raw_writel(value, addr); 130 } 131 132 static void __flash_write64(u64 value, void *addr) 133 { 134 /* No architectures currently implement __raw_writeq() */ 135 *(volatile u64 *)addr = value; 136 } 137 138 static u8 __flash_read8(void *addr) 139 { 140 return __raw_readb(addr); 141 } 142 143 static u16 __flash_read16(void *addr) 144 { 145 return __raw_readw(addr); 146 } 147 148 static u32 __flash_read32(void *addr) 149 { 150 return __raw_readl(addr); 151 } 152 153 static u64 __flash_read64(void *addr) 154 { 155 /* No architectures currently implement __raw_readq() */ 156 return *(volatile u64 *)addr; 157 } 158 159 #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 160 void flash_write8(u8 value, void *addr)__attribute__((weak, alias("__flash_write8"))); 161 void flash_write16(u16 value, void *addr)__attribute__((weak, alias("__flash_write16"))); 162 void flash_write32(u32 value, void *addr)__attribute__((weak, alias("__flash_write32"))); 163 void flash_write64(u64 value, void *addr)__attribute__((weak, alias("__flash_write64"))); 164 u8 flash_read8(void *addr)__attribute__((weak, alias("__flash_read8"))); 165 u16 flash_read16(void *addr)__attribute__((weak, alias("__flash_read16"))); 166 u32 flash_read32(void *addr)__attribute__((weak, alias("__flash_read32"))); 167 u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64"))); 168 #else 169 #define flash_write8 __flash_write8 170 #define flash_write16 __flash_write16 171 #define flash_write32 __flash_write32 172 #define flash_write64 __flash_write64 173 #define flash_read8 __flash_read8 174 #define flash_read16 __flash_read16 175 #define flash_read32 __flash_read32 176 #define flash_read64 __flash_read64 177 #endif 178 179 /*----------------------------------------------------------------------- 180 */ 181 #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) 182 flash_info_t *flash_get_info(ulong base) 183 { 184 int i; 185 flash_info_t *info = NULL; 186 187 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { 188 info = & flash_info[i]; 189 if (info->size && info->start[0] <= base && 190 base <= info->start[0] + info->size - 1) 191 break; 192 } 193 194 return info; 195 } 196 #endif 197 198 unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) 199 { 200 if (sect != (info->sector_count - 1)) 201 return info->start[sect + 1] - info->start[sect]; 202 else 203 return info->start[0] + info->size - info->start[sect]; 204 } 205 206 /*----------------------------------------------------------------------- 207 * create an address based on the offset and the port width 208 */ 209 static inline void * 210 flash_map (flash_info_t * info, flash_sect_t sect, uint offset) 211 { 212 unsigned int byte_offset = offset * info->portwidth; 213 214 return (void *)(info->start[sect] + byte_offset); 215 } 216 217 static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, 218 unsigned int offset, void *addr) 219 { 220 } 221 222 /*----------------------------------------------------------------------- 223 * make a proper sized command based on the port and chip widths 224 */ 225 static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) 226 { 227 int i; 228 int cword_offset; 229 int cp_offset; 230 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 231 u32 cmd_le = cpu_to_le32(cmd); 232 #endif 233 uchar val; 234 uchar *cp = (uchar *) cmdbuf; 235 236 for (i = info->portwidth; i > 0; i--){ 237 cword_offset = (info->portwidth-i)%info->chipwidth; 238 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 239 cp_offset = info->portwidth - i; 240 val = *((uchar*)&cmd_le + cword_offset); 241 #else 242 cp_offset = i - 1; 243 val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1); 244 #endif 245 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val; 246 } 247 } 248 249 #ifdef DEBUG 250 /*----------------------------------------------------------------------- 251 * Debug support 252 */ 253 static void print_longlong (char *str, unsigned long long data) 254 { 255 int i; 256 char *cp; 257 258 cp = (char *) &data; 259 for (i = 0; i < 8; i++) 260 sprintf (&str[i * 2], "%2.2x", *cp++); 261 } 262 263 static void flash_printqry (struct cfi_qry *qry) 264 { 265 u8 *p = (u8 *)qry; 266 int x, y; 267 268 for (x = 0; x < sizeof(struct cfi_qry); x += 16) { 269 debug("%02x : ", x); 270 for (y = 0; y < 16; y++) 271 debug("%2.2x ", p[x + y]); 272 debug(" "); 273 for (y = 0; y < 16; y++) { 274 unsigned char c = p[x + y]; 275 if (c >= 0x20 && c <= 0x7e) 276 debug("%c", c); 277 else 278 debug("."); 279 } 280 debug("\n"); 281 } 282 } 283 #endif 284 285 286 /*----------------------------------------------------------------------- 287 * read a character at a port width address 288 */ 289 static inline uchar flash_read_uchar (flash_info_t * info, uint offset) 290 { 291 uchar *cp; 292 uchar retval; 293 294 cp = flash_map (info, 0, offset); 295 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 296 retval = flash_read8(cp); 297 #else 298 retval = flash_read8(cp + info->portwidth - 1); 299 #endif 300 flash_unmap (info, 0, offset, cp); 301 return retval; 302 } 303 304 /*----------------------------------------------------------------------- 305 * read a word at a port width address, assume 16bit bus 306 */ 307 static inline ushort flash_read_word (flash_info_t * info, uint offset) 308 { 309 ushort *addr, retval; 310 311 addr = flash_map (info, 0, offset); 312 retval = flash_read16 (addr); 313 flash_unmap (info, 0, offset, addr); 314 return retval; 315 } 316 317 318 /*----------------------------------------------------------------------- 319 * read a long word by picking the least significant byte of each maximum 320 * port size word. Swap for ppc format. 321 */ 322 static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, 323 uint offset) 324 { 325 uchar *addr; 326 ulong retval; 327 328 #ifdef DEBUG 329 int x; 330 #endif 331 addr = flash_map (info, sect, offset); 332 333 #ifdef DEBUG 334 debug ("long addr is at %p info->portwidth = %d\n", addr, 335 info->portwidth); 336 for (x = 0; x < 4 * info->portwidth; x++) { 337 debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); 338 } 339 #endif 340 #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 341 retval = ((flash_read8(addr) << 16) | 342 (flash_read8(addr + info->portwidth) << 24) | 343 (flash_read8(addr + 2 * info->portwidth)) | 344 (flash_read8(addr + 3 * info->portwidth) << 8)); 345 #else 346 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | 347 (flash_read8(addr + info->portwidth - 1) << 16) | 348 (flash_read8(addr + 4 * info->portwidth - 1) << 8) | 349 (flash_read8(addr + 3 * info->portwidth - 1))); 350 #endif 351 flash_unmap(info, sect, offset, addr); 352 353 return retval; 354 } 355 356 /* 357 * Write a proper sized command to the correct address 358 */ 359 void flash_write_cmd (flash_info_t * info, flash_sect_t sect, 360 uint offset, u32 cmd) 361 { 362 363 void *addr; 364 cfiword_t cword; 365 366 addr = flash_map (info, sect, offset); 367 flash_make_cmd (info, cmd, &cword); 368 switch (info->portwidth) { 369 case FLASH_CFI_8BIT: 370 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, 371 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 372 flash_write8(cword.c, addr); 373 break; 374 case FLASH_CFI_16BIT: 375 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, 376 cmd, cword.w, 377 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 378 flash_write16(cword.w, addr); 379 break; 380 case FLASH_CFI_32BIT: 381 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr, 382 cmd, cword.l, 383 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 384 flash_write32(cword.l, addr); 385 break; 386 case FLASH_CFI_64BIT: 387 #ifdef DEBUG 388 { 389 char str[20]; 390 391 print_longlong (str, cword.ll); 392 393 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n", 394 addr, cmd, str, 395 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 396 } 397 #endif 398 flash_write64(cword.ll, addr); 399 break; 400 } 401 402 /* Ensure all the instructions are fully finished */ 403 sync(); 404 405 flash_unmap(info, sect, offset, addr); 406 } 407 408 static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect) 409 { 410 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); 411 flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); 412 } 413 414 /*----------------------------------------------------------------------- 415 */ 416 static int flash_isequal (flash_info_t * info, flash_sect_t sect, 417 uint offset, uchar cmd) 418 { 419 void *addr; 420 cfiword_t cword; 421 int retval; 422 423 addr = flash_map (info, sect, offset); 424 flash_make_cmd (info, cmd, &cword); 425 426 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); 427 switch (info->portwidth) { 428 case FLASH_CFI_8BIT: 429 debug ("is= %x %x\n", flash_read8(addr), cword.c); 430 retval = (flash_read8(addr) == cword.c); 431 break; 432 case FLASH_CFI_16BIT: 433 debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w); 434 retval = (flash_read16(addr) == cword.w); 435 break; 436 case FLASH_CFI_32BIT: 437 debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l); 438 retval = (flash_read32(addr) == cword.l); 439 break; 440 case FLASH_CFI_64BIT: 441 #ifdef DEBUG 442 { 443 char str1[20]; 444 char str2[20]; 445 446 print_longlong (str1, flash_read64(addr)); 447 print_longlong (str2, cword.ll); 448 debug ("is= %s %s\n", str1, str2); 449 } 450 #endif 451 retval = (flash_read64(addr) == cword.ll); 452 break; 453 default: 454 retval = 0; 455 break; 456 } 457 flash_unmap(info, sect, offset, addr); 458 459 return retval; 460 } 461 462 /*----------------------------------------------------------------------- 463 */ 464 static int flash_isset (flash_info_t * info, flash_sect_t sect, 465 uint offset, uchar cmd) 466 { 467 void *addr; 468 cfiword_t cword; 469 int retval; 470 471 addr = flash_map (info, sect, offset); 472 flash_make_cmd (info, cmd, &cword); 473 switch (info->portwidth) { 474 case FLASH_CFI_8BIT: 475 retval = ((flash_read8(addr) & cword.c) == cword.c); 476 break; 477 case FLASH_CFI_16BIT: 478 retval = ((flash_read16(addr) & cword.w) == cword.w); 479 break; 480 case FLASH_CFI_32BIT: 481 retval = ((flash_read32(addr) & cword.l) == cword.l); 482 break; 483 case FLASH_CFI_64BIT: 484 retval = ((flash_read64(addr) & cword.ll) == cword.ll); 485 break; 486 default: 487 retval = 0; 488 break; 489 } 490 flash_unmap(info, sect, offset, addr); 491 492 return retval; 493 } 494 495 /*----------------------------------------------------------------------- 496 */ 497 static int flash_toggle (flash_info_t * info, flash_sect_t sect, 498 uint offset, uchar cmd) 499 { 500 void *addr; 501 cfiword_t cword; 502 int retval; 503 504 addr = flash_map (info, sect, offset); 505 flash_make_cmd (info, cmd, &cword); 506 switch (info->portwidth) { 507 case FLASH_CFI_8BIT: 508 retval = flash_read8(addr) != flash_read8(addr); 509 break; 510 case FLASH_CFI_16BIT: 511 retval = flash_read16(addr) != flash_read16(addr); 512 break; 513 case FLASH_CFI_32BIT: 514 retval = flash_read32(addr) != flash_read32(addr); 515 break; 516 case FLASH_CFI_64BIT: 517 retval = ( (flash_read32( addr ) != flash_read32( addr )) || 518 (flash_read32(addr+4) != flash_read32(addr+4)) ); 519 break; 520 default: 521 retval = 0; 522 break; 523 } 524 flash_unmap(info, sect, offset, addr); 525 526 return retval; 527 } 528 529 /* 530 * flash_is_busy - check to see if the flash is busy 531 * 532 * This routine checks the status of the chip and returns true if the 533 * chip is busy. 534 */ 535 static int flash_is_busy (flash_info_t * info, flash_sect_t sect) 536 { 537 int retval; 538 539 switch (info->vendor) { 540 case CFI_CMDSET_INTEL_PROG_REGIONS: 541 case CFI_CMDSET_INTEL_STANDARD: 542 case CFI_CMDSET_INTEL_EXTENDED: 543 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE); 544 break; 545 case CFI_CMDSET_AMD_STANDARD: 546 case CFI_CMDSET_AMD_EXTENDED: 547 #ifdef CONFIG_FLASH_CFI_LEGACY 548 case CFI_CMDSET_AMD_LEGACY: 549 #endif 550 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE); 551 break; 552 default: 553 retval = 0; 554 } 555 debug ("flash_is_busy: %d\n", retval); 556 return retval; 557 } 558 559 /*----------------------------------------------------------------------- 560 * wait for XSR.7 to be set. Time out with an error if it does not. 561 * This routine does not set the flash to read-array mode. 562 */ 563 static int flash_status_check (flash_info_t * info, flash_sect_t sector, 564 ulong tout, char *prompt) 565 { 566 ulong start; 567 568 #if CONFIG_SYS_HZ != 1000 569 if ((ulong)CONFIG_SYS_HZ > 100000) 570 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ 571 else 572 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); 573 #endif 574 575 /* Wait for command completion */ 576 #ifdef CONFIG_SYS_LOW_RES_TIMER 577 reset_timer(); 578 #endif 579 start = get_timer (0); 580 while (flash_is_busy (info, sector)) { 581 if (get_timer (start) > tout) { 582 printf ("Flash %s timeout at address %lx data %lx\n", 583 prompt, info->start[sector], 584 flash_read_long (info, sector, 0)); 585 flash_write_cmd (info, sector, 0, info->cmd_reset); 586 udelay(1); 587 return ERR_TIMOUT; 588 } 589 udelay (1); /* also triggers watchdog */ 590 } 591 return ERR_OK; 592 } 593 594 /*----------------------------------------------------------------------- 595 * Wait for XSR.7 to be set, if it times out print an error, otherwise 596 * do a full status check. 597 * 598 * This routine sets the flash to read-array mode. 599 */ 600 static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, 601 ulong tout, char *prompt) 602 { 603 int retcode; 604 605 retcode = flash_status_check (info, sector, tout, prompt); 606 switch (info->vendor) { 607 case CFI_CMDSET_INTEL_PROG_REGIONS: 608 case CFI_CMDSET_INTEL_EXTENDED: 609 case CFI_CMDSET_INTEL_STANDARD: 610 if ((retcode != ERR_OK) 611 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { 612 retcode = ERR_INVAL; 613 printf ("Flash %s error at address %lx\n", prompt, 614 info->start[sector]); 615 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | 616 FLASH_STATUS_PSLBS)) { 617 puts ("Command Sequence Error.\n"); 618 } else if (flash_isset (info, sector, 0, 619 FLASH_STATUS_ECLBS)) { 620 puts ("Block Erase Error.\n"); 621 retcode = ERR_NOT_ERASED; 622 } else if (flash_isset (info, sector, 0, 623 FLASH_STATUS_PSLBS)) { 624 puts ("Locking Error\n"); 625 } 626 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) { 627 puts ("Block locked.\n"); 628 retcode = ERR_PROTECTED; 629 } 630 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS)) 631 puts ("Vpp Low Error.\n"); 632 } 633 flash_write_cmd (info, sector, 0, info->cmd_reset); 634 udelay(1); 635 break; 636 default: 637 break; 638 } 639 return retcode; 640 } 641 642 static int use_flash_status_poll(flash_info_t *info) 643 { 644 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL 645 if (info->vendor == CFI_CMDSET_AMD_EXTENDED || 646 info->vendor == CFI_CMDSET_AMD_STANDARD) 647 return 1; 648 #endif 649 return 0; 650 } 651 652 static int flash_status_poll(flash_info_t *info, void *src, void *dst, 653 ulong tout, char *prompt) 654 { 655 #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL 656 ulong start; 657 int ready; 658 659 #if CONFIG_SYS_HZ != 1000 660 if ((ulong)CONFIG_SYS_HZ > 100000) 661 tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ 662 else 663 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); 664 #endif 665 666 /* Wait for command completion */ 667 #ifdef CONFIG_SYS_LOW_RES_TIMER 668 reset_timer(); 669 #endif 670 start = get_timer(0); 671 while (1) { 672 switch (info->portwidth) { 673 case FLASH_CFI_8BIT: 674 ready = flash_read8(dst) == flash_read8(src); 675 break; 676 case FLASH_CFI_16BIT: 677 ready = flash_read16(dst) == flash_read16(src); 678 break; 679 case FLASH_CFI_32BIT: 680 ready = flash_read32(dst) == flash_read32(src); 681 break; 682 case FLASH_CFI_64BIT: 683 ready = flash_read64(dst) == flash_read64(src); 684 break; 685 default: 686 ready = 0; 687 break; 688 } 689 if (ready) 690 break; 691 if (get_timer(start) > tout) { 692 printf("Flash %s timeout at address %lx data %lx\n", 693 prompt, (ulong)dst, (ulong)flash_read8(dst)); 694 return ERR_TIMOUT; 695 } 696 udelay(1); /* also triggers watchdog */ 697 } 698 #endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */ 699 return ERR_OK; 700 } 701 702 /*----------------------------------------------------------------------- 703 */ 704 static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) 705 { 706 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 707 unsigned short w; 708 unsigned int l; 709 unsigned long long ll; 710 #endif 711 712 switch (info->portwidth) { 713 case FLASH_CFI_8BIT: 714 cword->c = c; 715 break; 716 case FLASH_CFI_16BIT: 717 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 718 w = c; 719 w <<= 8; 720 cword->w = (cword->w >> 8) | w; 721 #else 722 cword->w = (cword->w << 8) | c; 723 #endif 724 break; 725 case FLASH_CFI_32BIT: 726 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 727 l = c; 728 l <<= 24; 729 cword->l = (cword->l >> 8) | l; 730 #else 731 cword->l = (cword->l << 8) | c; 732 #endif 733 break; 734 case FLASH_CFI_64BIT: 735 #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) 736 ll = c; 737 ll <<= 56; 738 cword->ll = (cword->ll >> 8) | ll; 739 #else 740 cword->ll = (cword->ll << 8) | c; 741 #endif 742 break; 743 } 744 } 745 746 /* 747 * Loop through the sector table starting from the previously found sector. 748 * Searches forwards or backwards, dependent on the passed address. 749 */ 750 static flash_sect_t find_sector (flash_info_t * info, ulong addr) 751 { 752 static flash_sect_t saved_sector = 0; /* previously found sector */ 753 static flash_info_t *saved_info = 0; /* previously used flash bank */ 754 flash_sect_t sector = saved_sector; 755 756 if ((info != saved_info) || (sector >= info->sector_count)) 757 sector = 0; 758 759 while ((info->start[sector] < addr) 760 && (sector < info->sector_count - 1)) 761 sector++; 762 while ((info->start[sector] > addr) && (sector > 0)) 763 /* 764 * also decrements the sector in case of an overshot 765 * in the first loop 766 */ 767 sector--; 768 769 saved_sector = sector; 770 saved_info = info; 771 return sector; 772 } 773 774 /*----------------------------------------------------------------------- 775 */ 776 static int flash_write_cfiword (flash_info_t * info, ulong dest, 777 cfiword_t cword) 778 { 779 void *dstaddr = (void *)dest; 780 int flag; 781 flash_sect_t sect = 0; 782 char sect_found = 0; 783 784 /* Check if Flash is (sufficiently) erased */ 785 switch (info->portwidth) { 786 case FLASH_CFI_8BIT: 787 flag = ((flash_read8(dstaddr) & cword.c) == cword.c); 788 break; 789 case FLASH_CFI_16BIT: 790 flag = ((flash_read16(dstaddr) & cword.w) == cword.w); 791 break; 792 case FLASH_CFI_32BIT: 793 flag = ((flash_read32(dstaddr) & cword.l) == cword.l); 794 break; 795 case FLASH_CFI_64BIT: 796 flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll); 797 break; 798 default: 799 flag = 0; 800 break; 801 } 802 if (!flag) 803 return ERR_NOT_ERASED; 804 805 /* Disable interrupts which might cause a timeout here */ 806 flag = disable_interrupts (); 807 808 switch (info->vendor) { 809 case CFI_CMDSET_INTEL_PROG_REGIONS: 810 case CFI_CMDSET_INTEL_EXTENDED: 811 case CFI_CMDSET_INTEL_STANDARD: 812 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS); 813 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE); 814 break; 815 case CFI_CMDSET_AMD_EXTENDED: 816 case CFI_CMDSET_AMD_STANDARD: 817 sect = find_sector(info, dest); 818 flash_unlock_seq (info, sect); 819 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE); 820 sect_found = 1; 821 break; 822 #ifdef CONFIG_FLASH_CFI_LEGACY 823 case CFI_CMDSET_AMD_LEGACY: 824 sect = find_sector(info, dest); 825 flash_unlock_seq (info, 0); 826 flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE); 827 sect_found = 1; 828 break; 829 #endif 830 } 831 832 switch (info->portwidth) { 833 case FLASH_CFI_8BIT: 834 flash_write8(cword.c, dstaddr); 835 break; 836 case FLASH_CFI_16BIT: 837 flash_write16(cword.w, dstaddr); 838 break; 839 case FLASH_CFI_32BIT: 840 flash_write32(cword.l, dstaddr); 841 break; 842 case FLASH_CFI_64BIT: 843 flash_write64(cword.ll, dstaddr); 844 break; 845 } 846 847 /* re-enable interrupts if necessary */ 848 if (flag) 849 enable_interrupts (); 850 851 if (!sect_found) 852 sect = find_sector (info, dest); 853 854 if (use_flash_status_poll(info)) 855 return flash_status_poll(info, &cword, dstaddr, 856 info->write_tout, "write"); 857 else 858 return flash_full_status_check(info, sect, 859 info->write_tout, "write"); 860 } 861 862 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 863 864 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, 865 int len) 866 { 867 flash_sect_t sector; 868 int cnt; 869 int retcode; 870 void *src = cp; 871 void *dst = (void *)dest; 872 void *dst2 = dst; 873 int flag = 0; 874 uint offset = 0; 875 unsigned int shift; 876 uchar write_cmd; 877 878 switch (info->portwidth) { 879 case FLASH_CFI_8BIT: 880 shift = 0; 881 break; 882 case FLASH_CFI_16BIT: 883 shift = 1; 884 break; 885 case FLASH_CFI_32BIT: 886 shift = 2; 887 break; 888 case FLASH_CFI_64BIT: 889 shift = 3; 890 break; 891 default: 892 retcode = ERR_INVAL; 893 goto out_unmap; 894 } 895 896 cnt = len >> shift; 897 898 while ((cnt-- > 0) && (flag == 0)) { 899 switch (info->portwidth) { 900 case FLASH_CFI_8BIT: 901 flag = ((flash_read8(dst2) & flash_read8(src)) == 902 flash_read8(src)); 903 src += 1, dst2 += 1; 904 break; 905 case FLASH_CFI_16BIT: 906 flag = ((flash_read16(dst2) & flash_read16(src)) == 907 flash_read16(src)); 908 src += 2, dst2 += 2; 909 break; 910 case FLASH_CFI_32BIT: 911 flag = ((flash_read32(dst2) & flash_read32(src)) == 912 flash_read32(src)); 913 src += 4, dst2 += 4; 914 break; 915 case FLASH_CFI_64BIT: 916 flag = ((flash_read64(dst2) & flash_read64(src)) == 917 flash_read64(src)); 918 src += 8, dst2 += 8; 919 break; 920 } 921 } 922 if (!flag) { 923 retcode = ERR_NOT_ERASED; 924 goto out_unmap; 925 } 926 927 src = cp; 928 sector = find_sector (info, dest); 929 930 switch (info->vendor) { 931 case CFI_CMDSET_INTEL_PROG_REGIONS: 932 case CFI_CMDSET_INTEL_STANDARD: 933 case CFI_CMDSET_INTEL_EXTENDED: 934 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? 935 FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER; 936 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); 937 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS); 938 flash_write_cmd (info, sector, 0, write_cmd); 939 retcode = flash_status_check (info, sector, 940 info->buffer_write_tout, 941 "write to buffer"); 942 if (retcode == ERR_OK) { 943 /* reduce the number of loops by the width of 944 * the port */ 945 cnt = len >> shift; 946 flash_write_cmd (info, sector, 0, cnt - 1); 947 while (cnt-- > 0) { 948 switch (info->portwidth) { 949 case FLASH_CFI_8BIT: 950 flash_write8(flash_read8(src), dst); 951 src += 1, dst += 1; 952 break; 953 case FLASH_CFI_16BIT: 954 flash_write16(flash_read16(src), dst); 955 src += 2, dst += 2; 956 break; 957 case FLASH_CFI_32BIT: 958 flash_write32(flash_read32(src), dst); 959 src += 4, dst += 4; 960 break; 961 case FLASH_CFI_64BIT: 962 flash_write64(flash_read64(src), dst); 963 src += 8, dst += 8; 964 break; 965 default: 966 retcode = ERR_INVAL; 967 goto out_unmap; 968 } 969 } 970 flash_write_cmd (info, sector, 0, 971 FLASH_CMD_WRITE_BUFFER_CONFIRM); 972 retcode = flash_full_status_check ( 973 info, sector, info->buffer_write_tout, 974 "buffer write"); 975 } 976 977 break; 978 979 case CFI_CMDSET_AMD_STANDARD: 980 case CFI_CMDSET_AMD_EXTENDED: 981 flash_unlock_seq(info,0); 982 983 #ifdef CONFIG_FLASH_SPANSION_S29WS_N 984 offset = ((unsigned long)dst - info->start[sector]) >> shift; 985 #endif 986 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); 987 cnt = len >> shift; 988 flash_write_cmd(info, sector, offset, cnt - 1); 989 990 switch (info->portwidth) { 991 case FLASH_CFI_8BIT: 992 while (cnt-- > 0) { 993 flash_write8(flash_read8(src), dst); 994 src += 1, dst += 1; 995 } 996 break; 997 case FLASH_CFI_16BIT: 998 while (cnt-- > 0) { 999 flash_write16(flash_read16(src), dst); 1000 src += 2, dst += 2; 1001 } 1002 break; 1003 case FLASH_CFI_32BIT: 1004 while (cnt-- > 0) { 1005 flash_write32(flash_read32(src), dst); 1006 src += 4, dst += 4; 1007 } 1008 break; 1009 case FLASH_CFI_64BIT: 1010 while (cnt-- > 0) { 1011 flash_write64(flash_read64(src), dst); 1012 src += 8, dst += 8; 1013 } 1014 break; 1015 default: 1016 retcode = ERR_INVAL; 1017 goto out_unmap; 1018 } 1019 1020 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); 1021 if (use_flash_status_poll(info)) 1022 retcode = flash_status_poll(info, src - (1 << shift), 1023 dst - (1 << shift), 1024 info->buffer_write_tout, 1025 "buffer write"); 1026 else 1027 retcode = flash_full_status_check(info, sector, 1028 info->buffer_write_tout, 1029 "buffer write"); 1030 break; 1031 1032 default: 1033 debug ("Unknown Command Set\n"); 1034 retcode = ERR_INVAL; 1035 break; 1036 } 1037 1038 out_unmap: 1039 return retcode; 1040 } 1041 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 1042 1043 1044 /*----------------------------------------------------------------------- 1045 */ 1046 int flash_erase (flash_info_t * info, int s_first, int s_last) 1047 { 1048 int rcode = 0; 1049 int prot; 1050 flash_sect_t sect; 1051 int st; 1052 1053 if (info->flash_id != FLASH_MAN_CFI) { 1054 puts ("Can't erase unknown flash type - aborted\n"); 1055 return 1; 1056 } 1057 if ((s_first < 0) || (s_first > s_last)) { 1058 puts ("- no sectors to erase\n"); 1059 return 1; 1060 } 1061 1062 prot = 0; 1063 for (sect = s_first; sect <= s_last; ++sect) { 1064 if (info->protect[sect]) { 1065 prot++; 1066 } 1067 } 1068 if (prot) { 1069 printf ("- Warning: %d protected sectors will not be erased!\n", 1070 prot); 1071 } else if (flash_verbose) { 1072 putc ('\n'); 1073 } 1074 1075 1076 for (sect = s_first; sect <= s_last; sect++) { 1077 if (info->protect[sect] == 0) { /* not protected */ 1078 switch (info->vendor) { 1079 case CFI_CMDSET_INTEL_PROG_REGIONS: 1080 case CFI_CMDSET_INTEL_STANDARD: 1081 case CFI_CMDSET_INTEL_EXTENDED: 1082 flash_write_cmd (info, sect, 0, 1083 FLASH_CMD_CLEAR_STATUS); 1084 flash_write_cmd (info, sect, 0, 1085 FLASH_CMD_BLOCK_ERASE); 1086 flash_write_cmd (info, sect, 0, 1087 FLASH_CMD_ERASE_CONFIRM); 1088 break; 1089 case CFI_CMDSET_AMD_STANDARD: 1090 case CFI_CMDSET_AMD_EXTENDED: 1091 flash_unlock_seq (info, sect); 1092 flash_write_cmd (info, sect, 1093 info->addr_unlock1, 1094 AMD_CMD_ERASE_START); 1095 flash_unlock_seq (info, sect); 1096 flash_write_cmd (info, sect, 0, 1097 AMD_CMD_ERASE_SECTOR); 1098 break; 1099 #ifdef CONFIG_FLASH_CFI_LEGACY 1100 case CFI_CMDSET_AMD_LEGACY: 1101 flash_unlock_seq (info, 0); 1102 flash_write_cmd (info, 0, info->addr_unlock1, 1103 AMD_CMD_ERASE_START); 1104 flash_unlock_seq (info, 0); 1105 flash_write_cmd (info, sect, 0, 1106 AMD_CMD_ERASE_SECTOR); 1107 break; 1108 #endif 1109 default: 1110 debug ("Unkown flash vendor %d\n", 1111 info->vendor); 1112 break; 1113 } 1114 1115 if (use_flash_status_poll(info)) { 1116 cfiword_t cword = (cfiword_t)0xffffffffffffffffULL; 1117 void *dest; 1118 dest = flash_map(info, sect, 0); 1119 st = flash_status_poll(info, &cword, dest, 1120 info->erase_blk_tout, "erase"); 1121 flash_unmap(info, sect, 0, dest); 1122 } else 1123 st = flash_full_status_check(info, sect, 1124 info->erase_blk_tout, 1125 "erase"); 1126 if (st) 1127 rcode = 1; 1128 else if (flash_verbose) 1129 putc ('.'); 1130 } 1131 } 1132 1133 if (flash_verbose) 1134 puts (" done\n"); 1135 1136 return rcode; 1137 } 1138 1139 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 1140 static int sector_erased(flash_info_t *info, int i) 1141 { 1142 int k; 1143 int size; 1144 u32 *flash; 1145 1146 /* 1147 * Check if whole sector is erased 1148 */ 1149 size = flash_sector_size(info, i); 1150 flash = (u32 *)info->start[i]; 1151 /* divide by 4 for longword access */ 1152 size = size >> 2; 1153 1154 for (k = 0; k < size; k++) { 1155 if (flash_read32(flash++) != 0xffffffff) 1156 return 0; /* not erased */ 1157 } 1158 1159 return 1; /* erased */ 1160 } 1161 #endif /* CONFIG_SYS_FLASH_EMPTY_INFO */ 1162 1163 void flash_print_info (flash_info_t * info) 1164 { 1165 int i; 1166 1167 if (info->flash_id != FLASH_MAN_CFI) { 1168 puts ("missing or unknown FLASH type\n"); 1169 return; 1170 } 1171 1172 printf ("%s flash (%d x %d)", 1173 info->name, 1174 (info->portwidth << 3), (info->chipwidth << 3)); 1175 if (info->size < 1024*1024) 1176 printf (" Size: %ld kB in %d Sectors\n", 1177 info->size >> 10, info->sector_count); 1178 else 1179 printf (" Size: %ld MB in %d Sectors\n", 1180 info->size >> 20, info->sector_count); 1181 printf (" "); 1182 switch (info->vendor) { 1183 case CFI_CMDSET_INTEL_PROG_REGIONS: 1184 printf ("Intel Prog Regions"); 1185 break; 1186 case CFI_CMDSET_INTEL_STANDARD: 1187 printf ("Intel Standard"); 1188 break; 1189 case CFI_CMDSET_INTEL_EXTENDED: 1190 printf ("Intel Extended"); 1191 break; 1192 case CFI_CMDSET_AMD_STANDARD: 1193 printf ("AMD Standard"); 1194 break; 1195 case CFI_CMDSET_AMD_EXTENDED: 1196 printf ("AMD Extended"); 1197 break; 1198 #ifdef CONFIG_FLASH_CFI_LEGACY 1199 case CFI_CMDSET_AMD_LEGACY: 1200 printf ("AMD Legacy"); 1201 break; 1202 #endif 1203 default: 1204 printf ("Unknown (%d)", info->vendor); 1205 break; 1206 } 1207 printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x", 1208 info->manufacturer_id); 1209 printf (info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", 1210 info->device_id); 1211 if ((info->device_id & 0xff) == 0x7E) { 1212 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", 1213 info->device_id2); 1214 } 1215 printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n", 1216 info->erase_blk_tout, 1217 info->write_tout); 1218 if (info->buffer_size > 1) { 1219 printf (" Buffer write timeout: %ld ms, " 1220 "buffer size: %d bytes\n", 1221 info->buffer_write_tout, 1222 info->buffer_size); 1223 } 1224 1225 puts ("\n Sector Start Addresses:"); 1226 for (i = 0; i < info->sector_count; ++i) { 1227 if (ctrlc()) 1228 break; 1229 if ((i % 5) == 0) 1230 putc('\n'); 1231 #ifdef CONFIG_SYS_FLASH_EMPTY_INFO 1232 /* print empty and read-only info */ 1233 printf (" %08lX %c %s ", 1234 info->start[i], 1235 sector_erased(info, i) ? 'E' : ' ', 1236 info->protect[i] ? "RO" : " "); 1237 #else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */ 1238 printf (" %08lX %s ", 1239 info->start[i], 1240 info->protect[i] ? "RO" : " "); 1241 #endif 1242 } 1243 putc ('\n'); 1244 return; 1245 } 1246 1247 /*----------------------------------------------------------------------- 1248 * This is used in a few places in write_buf() to show programming 1249 * progress. Making it a function is nasty because it needs to do side 1250 * effect updates to digit and dots. Repeated code is nasty too, so 1251 * we define it once here. 1252 */ 1253 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1254 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ 1255 if (flash_verbose) { \ 1256 dots -= dots_sub; \ 1257 if ((scale > 0) && (dots <= 0)) { \ 1258 if ((digit % 5) == 0) \ 1259 printf ("%d", digit / 5); \ 1260 else \ 1261 putc ('.'); \ 1262 digit--; \ 1263 dots += scale; \ 1264 } \ 1265 } 1266 #else 1267 #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) 1268 #endif 1269 1270 /*----------------------------------------------------------------------- 1271 * Copy memory to flash, returns: 1272 * 0 - OK 1273 * 1 - write timeout 1274 * 2 - Flash not erased 1275 */ 1276 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) 1277 { 1278 ulong wp; 1279 uchar *p; 1280 int aln; 1281 cfiword_t cword; 1282 int i, rc; 1283 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1284 int buffered_size; 1285 #endif 1286 #ifdef CONFIG_FLASH_SHOW_PROGRESS 1287 int digit = CONFIG_FLASH_SHOW_PROGRESS; 1288 int scale = 0; 1289 int dots = 0; 1290 1291 /* 1292 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. 1293 */ 1294 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { 1295 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / 1296 CONFIG_FLASH_SHOW_PROGRESS); 1297 } 1298 #endif 1299 1300 /* get lower aligned address */ 1301 wp = (addr & ~(info->portwidth - 1)); 1302 1303 /* handle unaligned start */ 1304 if ((aln = addr - wp) != 0) { 1305 cword.l = 0; 1306 p = (uchar *)wp; 1307 for (i = 0; i < aln; ++i) 1308 flash_add_byte (info, &cword, flash_read8(p + i)); 1309 1310 for (; (i < info->portwidth) && (cnt > 0); i++) { 1311 flash_add_byte (info, &cword, *src++); 1312 cnt--; 1313 } 1314 for (; (cnt == 0) && (i < info->portwidth); ++i) 1315 flash_add_byte (info, &cword, flash_read8(p + i)); 1316 1317 rc = flash_write_cfiword (info, wp, cword); 1318 if (rc != 0) 1319 return rc; 1320 1321 wp += i; 1322 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1323 } 1324 1325 /* handle the aligned part */ 1326 #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1327 buffered_size = (info->portwidth / info->chipwidth); 1328 buffered_size *= info->buffer_size; 1329 while (cnt >= info->portwidth) { 1330 /* prohibit buffer write when buffer_size is 1 */ 1331 if (info->buffer_size == 1) { 1332 cword.l = 0; 1333 for (i = 0; i < info->portwidth; i++) 1334 flash_add_byte (info, &cword, *src++); 1335 if ((rc = flash_write_cfiword (info, wp, cword)) != 0) 1336 return rc; 1337 wp += info->portwidth; 1338 cnt -= info->portwidth; 1339 continue; 1340 } 1341 1342 /* write buffer until next buffered_size aligned boundary */ 1343 i = buffered_size - (wp % buffered_size); 1344 if (i > cnt) 1345 i = cnt; 1346 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) 1347 return rc; 1348 i -= i & (info->portwidth - 1); 1349 wp += i; 1350 src += i; 1351 cnt -= i; 1352 FLASH_SHOW_PROGRESS(scale, dots, digit, i); 1353 } 1354 #else 1355 while (cnt >= info->portwidth) { 1356 cword.l = 0; 1357 for (i = 0; i < info->portwidth; i++) { 1358 flash_add_byte (info, &cword, *src++); 1359 } 1360 if ((rc = flash_write_cfiword (info, wp, cword)) != 0) 1361 return rc; 1362 wp += info->portwidth; 1363 cnt -= info->portwidth; 1364 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); 1365 } 1366 #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 1367 1368 if (cnt == 0) { 1369 return (0); 1370 } 1371 1372 /* 1373 * handle unaligned tail bytes 1374 */ 1375 cword.l = 0; 1376 p = (uchar *)wp; 1377 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { 1378 flash_add_byte (info, &cword, *src++); 1379 --cnt; 1380 } 1381 for (; i < info->portwidth; ++i) 1382 flash_add_byte (info, &cword, flash_read8(p + i)); 1383 1384 return flash_write_cfiword (info, wp, cword); 1385 } 1386 1387 /*----------------------------------------------------------------------- 1388 */ 1389 #ifdef CONFIG_SYS_FLASH_PROTECTION 1390 1391 int flash_real_protect (flash_info_t * info, long sector, int prot) 1392 { 1393 int retcode = 0; 1394 1395 switch (info->vendor) { 1396 case CFI_CMDSET_INTEL_PROG_REGIONS: 1397 case CFI_CMDSET_INTEL_STANDARD: 1398 case CFI_CMDSET_INTEL_EXTENDED: 1399 /* 1400 * see errata called 1401 * "Numonyx Axcell P33/P30 Specification Update" :) 1402 */ 1403 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID); 1404 if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT, 1405 prot)) { 1406 /* 1407 * cmd must come before FLASH_CMD_PROTECT + 20us 1408 * Disable interrupts which might cause a timeout here. 1409 */ 1410 int flag = disable_interrupts (); 1411 unsigned short cmd; 1412 1413 if (prot) 1414 cmd = FLASH_CMD_PROTECT_SET; 1415 else 1416 cmd = FLASH_CMD_PROTECT_CLEAR; 1417 1418 flash_write_cmd (info, sector, 0, 1419 FLASH_CMD_PROTECT); 1420 flash_write_cmd (info, sector, 0, cmd); 1421 /* re-enable interrupts if necessary */ 1422 if (flag) 1423 enable_interrupts (); 1424 } 1425 break; 1426 case CFI_CMDSET_AMD_EXTENDED: 1427 case CFI_CMDSET_AMD_STANDARD: 1428 /* U-Boot only checks the first byte */ 1429 if (info->manufacturer_id == (uchar)ATM_MANUFACT) { 1430 if (prot) { 1431 flash_unlock_seq (info, 0); 1432 flash_write_cmd (info, 0, 1433 info->addr_unlock1, 1434 ATM_CMD_SOFTLOCK_START); 1435 flash_unlock_seq (info, 0); 1436 flash_write_cmd (info, sector, 0, 1437 ATM_CMD_LOCK_SECT); 1438 } else { 1439 flash_write_cmd (info, 0, 1440 info->addr_unlock1, 1441 AMD_CMD_UNLOCK_START); 1442 if (info->device_id == ATM_ID_BV6416) 1443 flash_write_cmd (info, sector, 1444 0, ATM_CMD_UNLOCK_SECT); 1445 } 1446 } 1447 break; 1448 #ifdef CONFIG_FLASH_CFI_LEGACY 1449 case CFI_CMDSET_AMD_LEGACY: 1450 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); 1451 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); 1452 if (prot) 1453 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); 1454 else 1455 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); 1456 #endif 1457 }; 1458 1459 /* 1460 * Flash needs to be in status register read mode for 1461 * flash_full_status_check() to work correctly 1462 */ 1463 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); 1464 if ((retcode = 1465 flash_full_status_check (info, sector, info->erase_blk_tout, 1466 prot ? "protect" : "unprotect")) == 0) { 1467 1468 info->protect[sector] = prot; 1469 1470 /* 1471 * On some of Intel's flash chips (marked via legacy_unlock) 1472 * unprotect unprotects all locking. 1473 */ 1474 if ((prot == 0) && (info->legacy_unlock)) { 1475 flash_sect_t i; 1476 1477 for (i = 0; i < info->sector_count; i++) { 1478 if (info->protect[i]) 1479 flash_real_protect (info, i, 1); 1480 } 1481 } 1482 } 1483 return retcode; 1484 } 1485 1486 /*----------------------------------------------------------------------- 1487 * flash_read_user_serial - read the OneTimeProgramming cells 1488 */ 1489 void flash_read_user_serial (flash_info_t * info, void *buffer, int offset, 1490 int len) 1491 { 1492 uchar *src; 1493 uchar *dst; 1494 1495 dst = buffer; 1496 src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION); 1497 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); 1498 memcpy (dst, src + offset, len); 1499 flash_write_cmd (info, 0, 0, info->cmd_reset); 1500 udelay(1); 1501 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); 1502 } 1503 1504 /* 1505 * flash_read_factory_serial - read the device Id from the protection area 1506 */ 1507 void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset, 1508 int len) 1509 { 1510 uchar *src; 1511 1512 src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION); 1513 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID); 1514 memcpy (buffer, src + offset, len); 1515 flash_write_cmd (info, 0, 0, info->cmd_reset); 1516 udelay(1); 1517 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); 1518 } 1519 1520 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 1521 1522 /*----------------------------------------------------------------------- 1523 * Reverse the order of the erase regions in the CFI QRY structure. 1524 * This is needed for chips that are either a) correctly detected as 1525 * top-boot, or b) buggy. 1526 */ 1527 static void cfi_reverse_geometry(struct cfi_qry *qry) 1528 { 1529 unsigned int i, j; 1530 u32 tmp; 1531 1532 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { 1533 tmp = qry->erase_region_info[i]; 1534 qry->erase_region_info[i] = qry->erase_region_info[j]; 1535 qry->erase_region_info[j] = tmp; 1536 } 1537 } 1538 1539 /*----------------------------------------------------------------------- 1540 * read jedec ids from device and set corresponding fields in info struct 1541 * 1542 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct 1543 * 1544 */ 1545 static void cmdset_intel_read_jedec_ids(flash_info_t *info) 1546 { 1547 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1548 udelay(1); 1549 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); 1550 udelay(1000); /* some flash are slow to respond */ 1551 info->manufacturer_id = flash_read_uchar (info, 1552 FLASH_OFFSET_MANUFACTURER_ID); 1553 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ? 1554 flash_read_word (info, FLASH_OFFSET_DEVICE_ID) : 1555 flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID); 1556 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1557 } 1558 1559 static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) 1560 { 1561 info->cmd_reset = FLASH_CMD_RESET; 1562 1563 cmdset_intel_read_jedec_ids(info); 1564 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1565 1566 #ifdef CONFIG_SYS_FLASH_PROTECTION 1567 /* read legacy lock/unlock bit from intel flash */ 1568 if (info->ext_addr) { 1569 info->legacy_unlock = flash_read_uchar (info, 1570 info->ext_addr + 5) & 0x08; 1571 } 1572 #endif 1573 1574 return 0; 1575 } 1576 1577 static void cmdset_amd_read_jedec_ids(flash_info_t *info) 1578 { 1579 ushort bankId = 0; 1580 uchar manuId; 1581 1582 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1583 flash_unlock_seq(info, 0); 1584 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); 1585 udelay(1000); /* some flash are slow to respond */ 1586 1587 manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID); 1588 /* JEDEC JEP106Z specifies ID codes up to bank 7 */ 1589 while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { 1590 bankId += 0x100; 1591 manuId = flash_read_uchar (info, 1592 bankId | FLASH_OFFSET_MANUFACTURER_ID); 1593 } 1594 info->manufacturer_id = manuId; 1595 1596 switch (info->chipwidth){ 1597 case FLASH_CFI_8BIT: 1598 info->device_id = flash_read_uchar (info, 1599 FLASH_OFFSET_DEVICE_ID); 1600 if (info->device_id == 0x7E) { 1601 /* AMD 3-byte (expanded) device ids */ 1602 info->device_id2 = flash_read_uchar (info, 1603 FLASH_OFFSET_DEVICE_ID2); 1604 info->device_id2 <<= 8; 1605 info->device_id2 |= flash_read_uchar (info, 1606 FLASH_OFFSET_DEVICE_ID3); 1607 } 1608 break; 1609 case FLASH_CFI_16BIT: 1610 info->device_id = flash_read_word (info, 1611 FLASH_OFFSET_DEVICE_ID); 1612 if ((info->device_id & 0xff) == 0x7E) { 1613 /* AMD 3-byte (expanded) device ids */ 1614 info->device_id2 = flash_read_uchar (info, 1615 FLASH_OFFSET_DEVICE_ID2); 1616 info->device_id2 <<= 8; 1617 info->device_id2 |= flash_read_uchar (info, 1618 FLASH_OFFSET_DEVICE_ID3); 1619 } 1620 break; 1621 default: 1622 break; 1623 } 1624 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1625 udelay(1); 1626 } 1627 1628 static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) 1629 { 1630 info->cmd_reset = AMD_CMD_RESET; 1631 1632 cmdset_amd_read_jedec_ids(info); 1633 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); 1634 1635 return 0; 1636 } 1637 1638 #ifdef CONFIG_FLASH_CFI_LEGACY 1639 static void flash_read_jedec_ids (flash_info_t * info) 1640 { 1641 info->manufacturer_id = 0; 1642 info->device_id = 0; 1643 info->device_id2 = 0; 1644 1645 switch (info->vendor) { 1646 case CFI_CMDSET_INTEL_PROG_REGIONS: 1647 case CFI_CMDSET_INTEL_STANDARD: 1648 case CFI_CMDSET_INTEL_EXTENDED: 1649 cmdset_intel_read_jedec_ids(info); 1650 break; 1651 case CFI_CMDSET_AMD_STANDARD: 1652 case CFI_CMDSET_AMD_EXTENDED: 1653 cmdset_amd_read_jedec_ids(info); 1654 break; 1655 default: 1656 break; 1657 } 1658 } 1659 1660 /*----------------------------------------------------------------------- 1661 * Call board code to request info about non-CFI flash. 1662 * board_flash_get_legacy needs to fill in at least: 1663 * info->portwidth, info->chipwidth and info->interface for Jedec probing. 1664 */ 1665 static int flash_detect_legacy(phys_addr_t base, int banknum) 1666 { 1667 flash_info_t *info = &flash_info[banknum]; 1668 1669 if (board_flash_get_legacy(base, banknum, info)) { 1670 /* board code may have filled info completely. If not, we 1671 use JEDEC ID probing. */ 1672 if (!info->vendor) { 1673 int modes[] = { 1674 CFI_CMDSET_AMD_STANDARD, 1675 CFI_CMDSET_INTEL_STANDARD 1676 }; 1677 int i; 1678 1679 for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) { 1680 info->vendor = modes[i]; 1681 info->start[0] = 1682 (ulong)map_physmem(base, 1683 info->portwidth, 1684 MAP_NOCACHE); 1685 if (info->portwidth == FLASH_CFI_8BIT 1686 && info->interface == FLASH_CFI_X8X16) { 1687 info->addr_unlock1 = 0x2AAA; 1688 info->addr_unlock2 = 0x5555; 1689 } else { 1690 info->addr_unlock1 = 0x5555; 1691 info->addr_unlock2 = 0x2AAA; 1692 } 1693 flash_read_jedec_ids(info); 1694 debug("JEDEC PROBE: ID %x %x %x\n", 1695 info->manufacturer_id, 1696 info->device_id, 1697 info->device_id2); 1698 if (jedec_flash_match(info, info->start[0])) 1699 break; 1700 else 1701 unmap_physmem((void *)info->start[0], 1702 MAP_NOCACHE); 1703 } 1704 } 1705 1706 switch(info->vendor) { 1707 case CFI_CMDSET_INTEL_PROG_REGIONS: 1708 case CFI_CMDSET_INTEL_STANDARD: 1709 case CFI_CMDSET_INTEL_EXTENDED: 1710 info->cmd_reset = FLASH_CMD_RESET; 1711 break; 1712 case CFI_CMDSET_AMD_STANDARD: 1713 case CFI_CMDSET_AMD_EXTENDED: 1714 case CFI_CMDSET_AMD_LEGACY: 1715 info->cmd_reset = AMD_CMD_RESET; 1716 break; 1717 } 1718 info->flash_id = FLASH_MAN_CFI; 1719 return 1; 1720 } 1721 return 0; /* use CFI */ 1722 } 1723 #else 1724 static inline int flash_detect_legacy(phys_addr_t base, int banknum) 1725 { 1726 return 0; /* use CFI */ 1727 } 1728 #endif 1729 1730 /*----------------------------------------------------------------------- 1731 * detect if flash is compatible with the Common Flash Interface (CFI) 1732 * http://www.jedec.org/download/search/jesd68.pdf 1733 */ 1734 static void flash_read_cfi (flash_info_t *info, void *buf, 1735 unsigned int start, size_t len) 1736 { 1737 u8 *p = buf; 1738 unsigned int i; 1739 1740 for (i = 0; i < len; i++) 1741 p[i] = flash_read_uchar(info, start + i); 1742 } 1743 1744 void __flash_cmd_reset(flash_info_t *info) 1745 { 1746 /* 1747 * We do not yet know what kind of commandset to use, so we issue 1748 * the reset command in both Intel and AMD variants, in the hope 1749 * that AMD flash roms ignore the Intel command. 1750 */ 1751 flash_write_cmd(info, 0, 0, AMD_CMD_RESET); 1752 udelay(1); 1753 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1754 } 1755 void flash_cmd_reset(flash_info_t *info) 1756 __attribute__((weak,alias("__flash_cmd_reset"))); 1757 1758 static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) 1759 { 1760 int cfi_offset; 1761 1762 /* Issue FLASH reset command */ 1763 flash_cmd_reset(info); 1764 1765 for (cfi_offset=0; 1766 cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); 1767 cfi_offset++) { 1768 flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], 1769 FLASH_CMD_CFI); 1770 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') 1771 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') 1772 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { 1773 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, 1774 sizeof(struct cfi_qry)); 1775 info->interface = le16_to_cpu(qry->interface_desc); 1776 1777 info->cfi_offset = flash_offset_cfi[cfi_offset]; 1778 debug ("device interface is %d\n", 1779 info->interface); 1780 debug ("found port %d chip %d ", 1781 info->portwidth, info->chipwidth); 1782 debug ("port %d bits chip %d bits\n", 1783 info->portwidth << CFI_FLASH_SHIFT_WIDTH, 1784 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 1785 1786 /* calculate command offsets as in the Linux driver */ 1787 info->addr_unlock1 = 0x555; 1788 info->addr_unlock2 = 0x2aa; 1789 1790 /* 1791 * modify the unlock address if we are 1792 * in compatibility mode 1793 */ 1794 if ( /* x8/x16 in x8 mode */ 1795 ((info->chipwidth == FLASH_CFI_BY8) && 1796 (info->interface == FLASH_CFI_X8X16)) || 1797 /* x16/x32 in x16 mode */ 1798 ((info->chipwidth == FLASH_CFI_BY16) && 1799 (info->interface == FLASH_CFI_X16X32))) 1800 { 1801 info->addr_unlock1 = 0xaaa; 1802 info->addr_unlock2 = 0x555; 1803 } 1804 1805 info->name = "CFI conformant"; 1806 return 1; 1807 } 1808 } 1809 1810 return 0; 1811 } 1812 1813 static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) 1814 { 1815 debug ("flash detect cfi\n"); 1816 1817 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; 1818 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { 1819 for (info->chipwidth = FLASH_CFI_BY8; 1820 info->chipwidth <= info->portwidth; 1821 info->chipwidth <<= 1) 1822 if (__flash_detect_cfi(info, qry)) 1823 return 1; 1824 } 1825 debug ("not found\n"); 1826 return 0; 1827 } 1828 1829 /* 1830 * Manufacturer-specific quirks. Add workarounds for geometry 1831 * reversal, etc. here. 1832 */ 1833 static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) 1834 { 1835 /* check if flash geometry needs reversal */ 1836 if (qry->num_erase_regions > 1) { 1837 /* reverse geometry if top boot part */ 1838 if (info->cfi_version < 0x3131) { 1839 /* CFI < 1.1, try to guess from device id */ 1840 if ((info->device_id & 0x80) != 0) 1841 cfi_reverse_geometry(qry); 1842 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 1843 /* CFI >= 1.1, deduct from top/bottom flag */ 1844 /* note: ext_addr is valid since cfi_version > 0 */ 1845 cfi_reverse_geometry(qry); 1846 } 1847 } 1848 } 1849 1850 static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) 1851 { 1852 int reverse_geometry = 0; 1853 1854 /* Check the "top boot" bit in the PRI */ 1855 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) 1856 reverse_geometry = 1; 1857 1858 /* AT49BV6416(T) list the erase regions in the wrong order. 1859 * However, the device ID is identical with the non-broken 1860 * AT49BV642D they differ in the high byte. 1861 */ 1862 if (info->device_id == 0xd6 || info->device_id == 0xd2) 1863 reverse_geometry = !reverse_geometry; 1864 1865 if (reverse_geometry) 1866 cfi_reverse_geometry(qry); 1867 } 1868 1869 static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) 1870 { 1871 /* check if flash geometry needs reversal */ 1872 if (qry->num_erase_regions > 1) { 1873 /* reverse geometry if top boot part */ 1874 if (info->cfi_version < 0x3131) { 1875 /* CFI < 1.1, guess by device id */ 1876 if (info->device_id == 0x22CA || /* M29W320DT */ 1877 info->device_id == 0x2256 || /* M29W320ET */ 1878 info->device_id == 0x22D7) { /* M29W800DT */ 1879 cfi_reverse_geometry(qry); 1880 } 1881 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { 1882 /* CFI >= 1.1, deduct from top/bottom flag */ 1883 /* note: ext_addr is valid since cfi_version > 0 */ 1884 cfi_reverse_geometry(qry); 1885 } 1886 } 1887 } 1888 1889 /* 1890 * The following code cannot be run from FLASH! 1891 * 1892 */ 1893 ulong flash_get_size (phys_addr_t base, int banknum) 1894 { 1895 flash_info_t *info = &flash_info[banknum]; 1896 int i, j; 1897 flash_sect_t sect_cnt; 1898 phys_addr_t sector; 1899 unsigned long tmp; 1900 int size_ratio; 1901 uchar num_erase_regions; 1902 int erase_region_size; 1903 int erase_region_count; 1904 struct cfi_qry qry; 1905 unsigned long max_size; 1906 1907 memset(&qry, 0, sizeof(qry)); 1908 1909 info->ext_addr = 0; 1910 info->cfi_version = 0; 1911 #ifdef CONFIG_SYS_FLASH_PROTECTION 1912 info->legacy_unlock = 0; 1913 #endif 1914 1915 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE); 1916 1917 if (flash_detect_cfi (info, &qry)) { 1918 info->vendor = le16_to_cpu(qry.p_id); 1919 info->ext_addr = le16_to_cpu(qry.p_adr); 1920 num_erase_regions = qry.num_erase_regions; 1921 1922 if (info->ext_addr) { 1923 info->cfi_version = (ushort) flash_read_uchar (info, 1924 info->ext_addr + 3) << 8; 1925 info->cfi_version |= (ushort) flash_read_uchar (info, 1926 info->ext_addr + 4); 1927 } 1928 1929 #ifdef DEBUG 1930 flash_printqry (&qry); 1931 #endif 1932 1933 switch (info->vendor) { 1934 case CFI_CMDSET_INTEL_PROG_REGIONS: 1935 case CFI_CMDSET_INTEL_STANDARD: 1936 case CFI_CMDSET_INTEL_EXTENDED: 1937 cmdset_intel_init(info, &qry); 1938 break; 1939 case CFI_CMDSET_AMD_STANDARD: 1940 case CFI_CMDSET_AMD_EXTENDED: 1941 cmdset_amd_init(info, &qry); 1942 break; 1943 default: 1944 printf("CFI: Unknown command set 0x%x\n", 1945 info->vendor); 1946 /* 1947 * Unfortunately, this means we don't know how 1948 * to get the chip back to Read mode. Might 1949 * as well try an Intel-style reset... 1950 */ 1951 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); 1952 return 0; 1953 } 1954 1955 /* Do manufacturer-specific fixups */ 1956 switch (info->manufacturer_id) { 1957 case 0x0001: /* AMD */ 1958 case 0x0037: /* AMIC */ 1959 flash_fixup_amd(info, &qry); 1960 break; 1961 case 0x001f: 1962 flash_fixup_atmel(info, &qry); 1963 break; 1964 case 0x0020: 1965 flash_fixup_stm(info, &qry); 1966 break; 1967 } 1968 1969 debug ("manufacturer is %d\n", info->vendor); 1970 debug ("manufacturer id is 0x%x\n", info->manufacturer_id); 1971 debug ("device id is 0x%x\n", info->device_id); 1972 debug ("device id2 is 0x%x\n", info->device_id2); 1973 debug ("cfi version is 0x%04x\n", info->cfi_version); 1974 1975 size_ratio = info->portwidth / info->chipwidth; 1976 /* if the chip is x8/x16 reduce the ratio by half */ 1977 if ((info->interface == FLASH_CFI_X8X16) 1978 && (info->chipwidth == FLASH_CFI_BY8)) { 1979 size_ratio >>= 1; 1980 } 1981 debug ("size_ratio %d port %d bits chip %d bits\n", 1982 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, 1983 info->chipwidth << CFI_FLASH_SHIFT_WIDTH); 1984 info->size = 1 << qry.dev_size; 1985 /* multiply the size by the number of chips */ 1986 info->size *= size_ratio; 1987 max_size = cfi_flash_bank_size(banknum); 1988 if (max_size && (info->size > max_size)) { 1989 debug("[truncated from %ldMiB]", info->size >> 20); 1990 info->size = max_size; 1991 } 1992 debug ("found %d erase regions\n", num_erase_regions); 1993 sect_cnt = 0; 1994 sector = base; 1995 for (i = 0; i < num_erase_regions; i++) { 1996 if (i > NUM_ERASE_REGIONS) { 1997 printf ("%d erase regions found, only %d used\n", 1998 num_erase_regions, NUM_ERASE_REGIONS); 1999 break; 2000 } 2001 2002 tmp = le32_to_cpu(qry.erase_region_info[i]); 2003 debug("erase region %u: 0x%08lx\n", i, tmp); 2004 2005 erase_region_count = (tmp & 0xffff) + 1; 2006 tmp >>= 16; 2007 erase_region_size = 2008 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; 2009 debug ("erase_region_count = %d erase_region_size = %d\n", 2010 erase_region_count, erase_region_size); 2011 for (j = 0; j < erase_region_count; j++) { 2012 if (sector - base >= info->size) 2013 break; 2014 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { 2015 printf("ERROR: too many flash sectors\n"); 2016 break; 2017 } 2018 info->start[sect_cnt] = 2019 (ulong)map_physmem(sector, 2020 info->portwidth, 2021 MAP_NOCACHE); 2022 sector += (erase_region_size * size_ratio); 2023 2024 /* 2025 * Only read protection status from 2026 * supported devices (intel...) 2027 */ 2028 switch (info->vendor) { 2029 case CFI_CMDSET_INTEL_PROG_REGIONS: 2030 case CFI_CMDSET_INTEL_EXTENDED: 2031 case CFI_CMDSET_INTEL_STANDARD: 2032 /* 2033 * Set flash to read-id mode. Otherwise 2034 * reading protected status is not 2035 * guaranteed. 2036 */ 2037 flash_write_cmd(info, sect_cnt, 0, 2038 FLASH_CMD_READ_ID); 2039 info->protect[sect_cnt] = 2040 flash_isset (info, sect_cnt, 2041 FLASH_OFFSET_PROTECT, 2042 FLASH_STATUS_PROTECT); 2043 break; 2044 default: 2045 /* default: not protected */ 2046 info->protect[sect_cnt] = 0; 2047 } 2048 2049 sect_cnt++; 2050 } 2051 } 2052 2053 info->sector_count = sect_cnt; 2054 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); 2055 tmp = 1 << qry.block_erase_timeout_typ; 2056 info->erase_blk_tout = tmp * 2057 (1 << qry.block_erase_timeout_max); 2058 tmp = (1 << qry.buf_write_timeout_typ) * 2059 (1 << qry.buf_write_timeout_max); 2060 2061 /* round up when converting to ms */ 2062 info->buffer_write_tout = (tmp + 999) / 1000; 2063 tmp = (1 << qry.word_write_timeout_typ) * 2064 (1 << qry.word_write_timeout_max); 2065 /* round up when converting to ms */ 2066 info->write_tout = (tmp + 999) / 1000; 2067 info->flash_id = FLASH_MAN_CFI; 2068 if ((info->interface == FLASH_CFI_X8X16) && 2069 (info->chipwidth == FLASH_CFI_BY8)) { 2070 /* XXX - Need to test on x8/x16 in parallel. */ 2071 info->portwidth >>= 1; 2072 } 2073 2074 flash_write_cmd (info, 0, 0, info->cmd_reset); 2075 } 2076 2077 return (info->size); 2078 } 2079 2080 #ifdef CONFIG_FLASH_CFI_MTD 2081 void flash_set_verbose(uint v) 2082 { 2083 flash_verbose = v; 2084 } 2085 #endif 2086 2087 static void cfi_flash_set_config_reg(u32 base, u16 val) 2088 { 2089 #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS 2090 /* 2091 * Only set this config register if really defined 2092 * to a valid value (0xffff is invalid) 2093 */ 2094 if (val == 0xffff) 2095 return; 2096 2097 /* 2098 * Set configuration register. Data is "encrypted" in the 16 lower 2099 * address bits. 2100 */ 2101 flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1))); 2102 flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1))); 2103 2104 /* 2105 * Finally issue reset-command to bring device back to 2106 * read-array mode 2107 */ 2108 flash_write16(FLASH_CMD_RESET, (void *)base); 2109 #endif 2110 } 2111 2112 /*----------------------------------------------------------------------- 2113 */ 2114 2115 void flash_protect_default(void) 2116 { 2117 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) 2118 int i; 2119 struct apl_s { 2120 ulong start; 2121 ulong size; 2122 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST; 2123 #endif 2124 2125 /* Monitor protection ON by default */ 2126 #if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ 2127 (!defined(CONFIG_MONITOR_IS_IN_RAM)) 2128 flash_protect(FLAG_PROTECT_SET, 2129 CONFIG_SYS_MONITOR_BASE, 2130 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, 2131 flash_get_info(CONFIG_SYS_MONITOR_BASE)); 2132 #endif 2133 2134 /* Environment protection ON by default */ 2135 #ifdef CONFIG_ENV_IS_IN_FLASH 2136 flash_protect(FLAG_PROTECT_SET, 2137 CONFIG_ENV_ADDR, 2138 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, 2139 flash_get_info(CONFIG_ENV_ADDR)); 2140 #endif 2141 2142 /* Redundant environment protection ON by default */ 2143 #ifdef CONFIG_ENV_ADDR_REDUND 2144 flash_protect(FLAG_PROTECT_SET, 2145 CONFIG_ENV_ADDR_REDUND, 2146 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, 2147 flash_get_info(CONFIG_ENV_ADDR_REDUND)); 2148 #endif 2149 2150 #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) 2151 for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) { 2152 debug("autoprotecting from %08x to %08x\n", 2153 apl[i].start, apl[i].start + apl[i].size - 1); 2154 flash_protect(FLAG_PROTECT_SET, 2155 apl[i].start, 2156 apl[i].start + apl[i].size - 1, 2157 flash_get_info(apl[i].start)); 2158 } 2159 #endif 2160 } 2161 2162 unsigned long flash_init (void) 2163 { 2164 unsigned long size = 0; 2165 int i; 2166 2167 #ifdef CONFIG_SYS_FLASH_PROTECTION 2168 /* read environment from EEPROM */ 2169 char s[64]; 2170 getenv_f("unlock", s, sizeof(s)); 2171 #endif 2172 2173 /* Init: no FLASHes known */ 2174 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { 2175 flash_info[i].flash_id = FLASH_UNKNOWN; 2176 2177 /* Optionally write flash configuration register */ 2178 cfi_flash_set_config_reg(cfi_flash_bank_addr(i), 2179 cfi_flash_config_reg(i)); 2180 2181 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) 2182 flash_get_size(cfi_flash_bank_addr(i), i); 2183 size += flash_info[i].size; 2184 if (flash_info[i].flash_id == FLASH_UNKNOWN) { 2185 #ifndef CONFIG_SYS_FLASH_QUIET_TEST 2186 printf ("## Unknown flash on Bank %d " 2187 "- Size = 0x%08lx = %ld MB\n", 2188 i+1, flash_info[i].size, 2189 flash_info[i].size >> 20); 2190 #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ 2191 } 2192 #ifdef CONFIG_SYS_FLASH_PROTECTION 2193 else if ((s != NULL) && (strcmp(s, "yes") == 0)) { 2194 /* 2195 * Only the U-Boot image and it's environment 2196 * is protected, all other sectors are 2197 * unprotected (unlocked) if flash hardware 2198 * protection is used (CONFIG_SYS_FLASH_PROTECTION) 2199 * and the environment variable "unlock" is 2200 * set to "yes". 2201 */ 2202 if (flash_info[i].legacy_unlock) { 2203 int k; 2204 2205 /* 2206 * Disable legacy_unlock temporarily, 2207 * since flash_real_protect would 2208 * relock all other sectors again 2209 * otherwise. 2210 */ 2211 flash_info[i].legacy_unlock = 0; 2212 2213 /* 2214 * Legacy unlocking (e.g. Intel J3) -> 2215 * unlock only one sector. This will 2216 * unlock all sectors. 2217 */ 2218 flash_real_protect (&flash_info[i], 0, 0); 2219 2220 flash_info[i].legacy_unlock = 1; 2221 2222 /* 2223 * Manually mark other sectors as 2224 * unlocked (unprotected) 2225 */ 2226 for (k = 1; k < flash_info[i].sector_count; k++) 2227 flash_info[i].protect[k] = 0; 2228 } else { 2229 /* 2230 * No legancy unlocking -> unlock all sectors 2231 */ 2232 flash_protect (FLAG_PROTECT_CLEAR, 2233 flash_info[i].start[0], 2234 flash_info[i].start[0] 2235 + flash_info[i].size - 1, 2236 &flash_info[i]); 2237 } 2238 } 2239 #endif /* CONFIG_SYS_FLASH_PROTECTION */ 2240 } 2241 2242 flash_protect_default(); 2243 #ifdef CONFIG_FLASH_CFI_MTD 2244 cfi_mtd_init(); 2245 #endif 2246 2247 return (size); 2248 } 2249