1 /* 2 * Copyright (C) 2016 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <fdtdec.h> 11 #include <mmc.h> 12 #include <dm.h> 13 #include <linux/compat.h> 14 #include <linux/dma-direction.h> 15 #include <linux/io.h> 16 #include <linux/sizes.h> 17 #include <asm/unaligned.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #define UNIPHIER_SD_CMD 0x000 /* command */ 22 #define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ 23 #define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */ 24 #define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */ 25 #define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */ 26 #define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ 27 #define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */ 28 #define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */ 29 #define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */ 30 #define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */ 31 #define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */ 32 #define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */ 33 #define UNIPHIER_SD_ARG 0x008 /* command argument */ 34 #define UNIPHIER_SD_STOP 0x010 /* stop action control */ 35 #define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */ 36 #define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */ 37 #define UNIPHIER_SD_SECCNT 0x014 /* sector counter */ 38 #define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */ 39 #define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */ 40 #define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */ 41 #define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */ 42 #define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */ 43 #define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */ 44 #define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */ 45 #define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */ 46 #define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */ 47 #define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */ 48 #define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */ 49 #define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ 50 #define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */ 51 #define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */ 52 #define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */ 53 #define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */ 54 #define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */ 55 #define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */ 56 #define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */ 57 #define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */ 58 #define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */ 59 #define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */ 60 #define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */ 61 #define UNIPHIER_SD_INFO1_MASK 0x040 62 #define UNIPHIER_SD_INFO2_MASK 0x044 63 #define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */ 64 #define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff 65 #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */ 66 #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ 67 #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ 68 #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ 69 #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ 70 #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ 71 #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ 72 #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ 73 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ 74 #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ 75 #define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ 76 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ 77 #define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ 78 #define UNIPHIER_SD_SIZE 0x04c /* block size */ 79 #define UNIPHIER_SD_OPTION 0x050 80 #define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13) 81 #define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13) 82 #define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13) 83 #define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13) 84 #define UNIPHIER_SD_BUF 0x060 /* read/write buffer */ 85 #define UNIPHIER_SD_EXTMODE 0x1b0 86 #define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ 87 #define UNIPHIER_SD_SOFT_RST 0x1c0 88 #define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */ 89 #define UNIPHIER_SD_VERSION 0x1c4 /* version register */ 90 #define UNIPHIER_SD_VERSION_IP 0xff /* IP version */ 91 #define UNIPHIER_SD_HOST_MODE 0x1c8 92 #define UNIPHIER_SD_IF_MODE 0x1cc 93 #define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */ 94 #define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */ 95 #define UNIPHIER_SD_VOLT_MASK (3 << 0) 96 #define UNIPHIER_SD_VOLT_OFF (0 << 0) 97 #define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */ 98 #define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */ 99 #define UNIPHIER_SD_DMA_MODE 0x410 100 #define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ 101 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ 102 #define UNIPHIER_SD_DMA_CTL 0x414 103 #define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ 104 #define UNIPHIER_SD_DMA_RST 0x418 105 #define UNIPHIER_SD_DMA_RST_RD BIT(9) 106 #define UNIPHIER_SD_DMA_RST_WR BIT(8) 107 #define UNIPHIER_SD_DMA_INFO1 0x420 108 #define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/ 109 #define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */ 110 #define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ 111 #define UNIPHIER_SD_DMA_INFO1_MASK 0x424 112 #define UNIPHIER_SD_DMA_INFO2 0x428 113 #define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17) 114 #define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16) 115 #define UNIPHIER_SD_DMA_INFO2_MASK 0x42c 116 #define UNIPHIER_SD_DMA_ADDR_L 0x440 117 #define UNIPHIER_SD_DMA_ADDR_H 0x444 118 119 /* alignment required by the DMA engine of this controller */ 120 #define UNIPHIER_SD_DMA_MINALIGN 0x10 121 122 struct uniphier_sd_plat { 123 struct mmc_config cfg; 124 struct mmc mmc; 125 }; 126 127 struct uniphier_sd_priv { 128 void __iomem *regbase; 129 unsigned long mclk; 130 unsigned int version; 131 u32 caps; 132 #define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ 133 #define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ 134 #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ 135 #define UNIPHIER_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ 136 }; 137 138 static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, unsigned int reg) 139 { 140 if (priv->caps & UNIPHIER_SD_CAP_64BIT) 141 return readq(priv->regbase + (reg << 1)); 142 else 143 return readq(priv->regbase + reg); 144 } 145 146 static void uniphier_sd_writeq(struct uniphier_sd_priv *priv, 147 u64 val, unsigned int reg) 148 { 149 if (priv->caps & UNIPHIER_SD_CAP_64BIT) 150 writeq(val, priv->regbase + (reg << 1)); 151 else 152 writeq(val, priv->regbase + reg); 153 } 154 155 static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg) 156 { 157 if (priv->caps & UNIPHIER_SD_CAP_64BIT) 158 return readl(priv->regbase + (reg << 1)); 159 else 160 return readl(priv->regbase + reg); 161 } 162 163 static void uniphier_sd_writel(struct uniphier_sd_priv *priv, 164 u32 val, unsigned int reg) 165 { 166 if (priv->caps & UNIPHIER_SD_CAP_64BIT) 167 writel(val, priv->regbase + (reg << 1)); 168 else 169 writel(val, priv->regbase + reg); 170 } 171 172 static dma_addr_t __dma_map_single(void *ptr, size_t size, 173 enum dma_data_direction dir) 174 { 175 unsigned long addr = (unsigned long)ptr; 176 177 if (dir == DMA_FROM_DEVICE) 178 invalidate_dcache_range(addr, addr + size); 179 else 180 flush_dcache_range(addr, addr + size); 181 182 return addr; 183 } 184 185 static void __dma_unmap_single(dma_addr_t addr, size_t size, 186 enum dma_data_direction dir) 187 { 188 if (dir != DMA_TO_DEVICE) 189 invalidate_dcache_range(addr, addr + size); 190 } 191 192 static int uniphier_sd_check_error(struct udevice *dev) 193 { 194 struct uniphier_sd_priv *priv = dev_get_priv(dev); 195 u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2); 196 197 if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) { 198 /* 199 * TIMEOUT must be returned for unsupported command. Do not 200 * display error log since this might be a part of sequence to 201 * distinguish between SD and MMC. 202 */ 203 return -ETIMEDOUT; 204 } 205 206 if (info2 & UNIPHIER_SD_INFO2_ERR_TO) { 207 dev_err(dev, "timeout error\n"); 208 return -ETIMEDOUT; 209 } 210 211 if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC | 212 UNIPHIER_SD_INFO2_ERR_IDX)) { 213 dev_err(dev, "communication out of sync\n"); 214 return -EILSEQ; 215 } 216 217 if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR | 218 UNIPHIER_SD_INFO2_ERR_ILW)) { 219 dev_err(dev, "illegal access\n"); 220 return -EIO; 221 } 222 223 return 0; 224 } 225 226 static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg, 227 u32 flag) 228 { 229 struct uniphier_sd_priv *priv = dev_get_priv(dev); 230 long wait = 1000000; 231 int ret; 232 233 while (!(uniphier_sd_readl(priv, reg) & flag)) { 234 if (wait-- < 0) { 235 dev_err(dev, "timeout\n"); 236 return -ETIMEDOUT; 237 } 238 239 ret = uniphier_sd_check_error(dev); 240 if (ret) 241 return ret; 242 243 udelay(1); 244 } 245 246 return 0; 247 } 248 249 static int uniphier_sd_pio_read_one_block(struct udevice *dev, char *pbuf, 250 uint blocksize) 251 { 252 struct uniphier_sd_priv *priv = dev_get_priv(dev); 253 int i, ret; 254 255 /* wait until the buffer is filled with data */ 256 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2, 257 UNIPHIER_SD_INFO2_BRE); 258 if (ret) 259 return ret; 260 261 /* 262 * Clear the status flag _before_ read the buffer out because 263 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered. 264 */ 265 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); 266 267 if (priv->caps & UNIPHIER_SD_CAP_64BIT) { 268 u64 *buf = (u64 *)pbuf; 269 if (likely(IS_ALIGNED((uintptr_t)buf, 8))) { 270 for (i = 0; i < blocksize / 8; i++) { 271 *buf++ = uniphier_sd_readq(priv, 272 UNIPHIER_SD_BUF); 273 } 274 } else { 275 for (i = 0; i < blocksize / 8; i++) { 276 u64 data; 277 data = uniphier_sd_readq(priv, 278 UNIPHIER_SD_BUF); 279 put_unaligned(data, buf++); 280 } 281 } 282 } else { 283 u32 *buf = (u32 *)pbuf; 284 if (likely(IS_ALIGNED((uintptr_t)buf, 4))) { 285 for (i = 0; i < blocksize / 4; i++) { 286 *buf++ = uniphier_sd_readl(priv, 287 UNIPHIER_SD_BUF); 288 } 289 } else { 290 for (i = 0; i < blocksize / 4; i++) { 291 u32 data; 292 data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF); 293 put_unaligned(data, buf++); 294 } 295 } 296 } 297 298 return 0; 299 } 300 301 static int uniphier_sd_pio_write_one_block(struct udevice *dev, 302 const char *pbuf, uint blocksize) 303 { 304 struct uniphier_sd_priv *priv = dev_get_priv(dev); 305 int i, ret; 306 307 /* wait until the buffer becomes empty */ 308 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2, 309 UNIPHIER_SD_INFO2_BWE); 310 if (ret) 311 return ret; 312 313 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); 314 315 if (priv->caps & UNIPHIER_SD_CAP_64BIT) { 316 const u64 *buf = (const u64 *)pbuf; 317 if (likely(IS_ALIGNED((uintptr_t)buf, 8))) { 318 for (i = 0; i < blocksize / 8; i++) { 319 uniphier_sd_writeq(priv, *buf++, 320 UNIPHIER_SD_BUF); 321 } 322 } else { 323 for (i = 0; i < blocksize / 8; i++) { 324 u64 data = get_unaligned(buf++); 325 uniphier_sd_writeq(priv, data, 326 UNIPHIER_SD_BUF); 327 } 328 } 329 } else { 330 const u32 *buf = (const u32 *)pbuf; 331 if (likely(IS_ALIGNED((uintptr_t)buf, 4))) { 332 for (i = 0; i < blocksize / 4; i++) { 333 uniphier_sd_writel(priv, *buf++, 334 UNIPHIER_SD_BUF); 335 } 336 } else { 337 for (i = 0; i < blocksize / 4; i++) { 338 u32 data = get_unaligned(buf++); 339 uniphier_sd_writel(priv, data, 340 UNIPHIER_SD_BUF); 341 } 342 } 343 } 344 345 return 0; 346 } 347 348 static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data) 349 { 350 const char *src = data->src; 351 char *dest = data->dest; 352 int i, ret; 353 354 for (i = 0; i < data->blocks; i++) { 355 if (data->flags & MMC_DATA_READ) 356 ret = uniphier_sd_pio_read_one_block(dev, dest, 357 data->blocksize); 358 else 359 ret = uniphier_sd_pio_write_one_block(dev, src, 360 data->blocksize); 361 if (ret) 362 return ret; 363 364 if (data->flags & MMC_DATA_READ) 365 dest += data->blocksize; 366 else 367 src += data->blocksize; 368 } 369 370 return 0; 371 } 372 373 static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv, 374 dma_addr_t dma_addr) 375 { 376 u32 tmp; 377 378 uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1); 379 uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2); 380 381 /* enable DMA */ 382 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); 383 tmp |= UNIPHIER_SD_EXTMODE_DMA_EN; 384 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); 385 386 uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L); 387 388 /* suppress the warning "right shift count >= width of type" */ 389 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); 390 391 uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H); 392 393 uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL); 394 } 395 396 static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, 397 unsigned int blocks) 398 { 399 struct uniphier_sd_priv *priv = dev_get_priv(dev); 400 long wait = 1000000 + 10 * blocks; 401 402 while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) { 403 if (wait-- < 0) { 404 dev_err(dev, "timeout during DMA\n"); 405 return -ETIMEDOUT; 406 } 407 408 udelay(10); 409 } 410 411 if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) { 412 dev_err(dev, "error during DMA\n"); 413 return -EIO; 414 } 415 416 return 0; 417 } 418 419 static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) 420 { 421 struct uniphier_sd_priv *priv = dev_get_priv(dev); 422 size_t len = data->blocks * data->blocksize; 423 void *buf; 424 enum dma_data_direction dir; 425 dma_addr_t dma_addr; 426 u32 poll_flag, tmp; 427 int ret; 428 429 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); 430 431 if (data->flags & MMC_DATA_READ) { 432 buf = data->dest; 433 dir = DMA_FROM_DEVICE; 434 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2; 435 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD; 436 } else { 437 buf = (void *)data->src; 438 dir = DMA_TO_DEVICE; 439 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR; 440 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD; 441 } 442 443 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); 444 445 dma_addr = __dma_map_single(buf, len, dir); 446 447 uniphier_sd_dma_start(priv, dma_addr); 448 449 ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); 450 451 __dma_unmap_single(dma_addr, len, dir); 452 453 return ret; 454 } 455 456 /* check if the address is DMA'able */ 457 static bool uniphier_sd_addr_is_dmaable(unsigned long addr) 458 { 459 if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN)) 460 return false; 461 462 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ 463 defined(CONFIG_SPL_BUILD) 464 /* 465 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways 466 * of L2, which is unreachable from the DMA engine. 467 */ 468 if (addr < CONFIG_SPL_STACK) 469 return false; 470 #endif 471 472 return true; 473 } 474 475 static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 476 struct mmc_data *data) 477 { 478 struct uniphier_sd_priv *priv = dev_get_priv(dev); 479 int ret; 480 u32 tmp; 481 482 if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { 483 dev_err(dev, "command busy\n"); 484 return -EBUSY; 485 } 486 487 /* clear all status flags */ 488 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1); 489 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); 490 491 /* disable DMA once */ 492 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); 493 tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN; 494 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); 495 496 uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG); 497 498 tmp = cmd->cmdidx; 499 500 if (data) { 501 uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE); 502 uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT); 503 504 /* Do not send CMD12 automatically */ 505 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA; 506 507 if (data->blocks > 1) 508 tmp |= UNIPHIER_SD_CMD_MULTI; 509 510 if (data->flags & MMC_DATA_READ) 511 tmp |= UNIPHIER_SD_CMD_RD; 512 } 513 514 /* 515 * Do not use the response type auto-detection on this hardware. 516 * CMD8, for example, has different response types on SD and eMMC, 517 * while this controller always assumes the response type for SD. 518 * Set the response type manually. 519 */ 520 switch (cmd->resp_type) { 521 case MMC_RSP_NONE: 522 tmp |= UNIPHIER_SD_CMD_RSP_NONE; 523 break; 524 case MMC_RSP_R1: 525 tmp |= UNIPHIER_SD_CMD_RSP_R1; 526 break; 527 case MMC_RSP_R1b: 528 tmp |= UNIPHIER_SD_CMD_RSP_R1B; 529 break; 530 case MMC_RSP_R2: 531 tmp |= UNIPHIER_SD_CMD_RSP_R2; 532 break; 533 case MMC_RSP_R3: 534 tmp |= UNIPHIER_SD_CMD_RSP_R3; 535 break; 536 default: 537 dev_err(dev, "unknown response type\n"); 538 return -EINVAL; 539 } 540 541 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", 542 cmd->cmdidx, tmp, cmd->cmdarg); 543 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD); 544 545 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, 546 UNIPHIER_SD_INFO1_RSP); 547 if (ret) 548 return ret; 549 550 if (cmd->resp_type & MMC_RSP_136) { 551 u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76); 552 u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54); 553 u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32); 554 u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); 555 556 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) | 557 ((rsp_103_72 & 0xff000000) >> 24); 558 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) | 559 ((rsp_71_40 & 0xff000000) >> 24); 560 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) | 561 ((rsp_39_8 & 0xff000000) >> 24); 562 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; 563 } else { 564 /* bit 39-8 */ 565 cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); 566 } 567 568 if (data) { 569 /* use DMA if the HW supports it and the buffer is aligned */ 570 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL && 571 uniphier_sd_addr_is_dmaable((long)data->src)) 572 ret = uniphier_sd_dma_xfer(dev, data); 573 else 574 ret = uniphier_sd_pio_xfer(dev, data); 575 576 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, 577 UNIPHIER_SD_INFO1_CMP); 578 if (ret) 579 return ret; 580 } 581 582 return ret; 583 } 584 585 static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv, 586 struct mmc *mmc) 587 { 588 u32 val, tmp; 589 590 switch (mmc->bus_width) { 591 case 1: 592 val = UNIPHIER_SD_OPTION_WIDTH_1; 593 break; 594 case 4: 595 val = UNIPHIER_SD_OPTION_WIDTH_4; 596 break; 597 case 8: 598 val = UNIPHIER_SD_OPTION_WIDTH_8; 599 break; 600 default: 601 return -EINVAL; 602 } 603 604 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION); 605 tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK; 606 tmp |= val; 607 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION); 608 609 return 0; 610 } 611 612 static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv, 613 struct mmc *mmc) 614 { 615 u32 tmp; 616 617 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE); 618 if (mmc->ddr_mode) 619 tmp |= UNIPHIER_SD_IF_MODE_DDR; 620 else 621 tmp &= ~UNIPHIER_SD_IF_MODE_DDR; 622 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE); 623 } 624 625 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, 626 struct mmc *mmc) 627 { 628 unsigned int divisor; 629 u32 val, tmp; 630 631 if (!mmc->clock) 632 return; 633 634 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); 635 636 if (divisor <= 1) 637 val = UNIPHIER_SD_CLKCTL_DIV1; 638 else if (divisor <= 2) 639 val = UNIPHIER_SD_CLKCTL_DIV2; 640 else if (divisor <= 4) 641 val = UNIPHIER_SD_CLKCTL_DIV4; 642 else if (divisor <= 8) 643 val = UNIPHIER_SD_CLKCTL_DIV8; 644 else if (divisor <= 16) 645 val = UNIPHIER_SD_CLKCTL_DIV16; 646 else if (divisor <= 32) 647 val = UNIPHIER_SD_CLKCTL_DIV32; 648 else if (divisor <= 64) 649 val = UNIPHIER_SD_CLKCTL_DIV64; 650 else if (divisor <= 128) 651 val = UNIPHIER_SD_CLKCTL_DIV128; 652 else if (divisor <= 256) 653 val = UNIPHIER_SD_CLKCTL_DIV256; 654 else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024)) 655 val = UNIPHIER_SD_CLKCTL_DIV512; 656 else 657 val = UNIPHIER_SD_CLKCTL_DIV1024; 658 659 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL); 660 if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN && 661 (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val) 662 return; 663 664 /* stop the clock before changing its rate to avoid a glitch signal */ 665 tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN; 666 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); 667 668 tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK; 669 tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN; 670 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); 671 672 tmp |= UNIPHIER_SD_CLKCTL_SCLKEN; 673 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); 674 675 udelay(1000); 676 } 677 678 static int uniphier_sd_set_ios(struct udevice *dev) 679 { 680 struct uniphier_sd_priv *priv = dev_get_priv(dev); 681 struct mmc *mmc = mmc_get_mmc_dev(dev); 682 int ret; 683 684 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n", 685 mmc->clock, mmc->ddr_mode, mmc->bus_width); 686 687 ret = uniphier_sd_set_bus_width(priv, mmc); 688 if (ret) 689 return ret; 690 uniphier_sd_set_ddr_mode(priv, mmc); 691 uniphier_sd_set_clk_rate(priv, mmc); 692 693 return 0; 694 } 695 696 static int uniphier_sd_get_cd(struct udevice *dev) 697 { 698 struct uniphier_sd_priv *priv = dev_get_priv(dev); 699 700 if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE) 701 return 1; 702 703 return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) & 704 UNIPHIER_SD_INFO1_CD); 705 } 706 707 static const struct dm_mmc_ops uniphier_sd_ops = { 708 .send_cmd = uniphier_sd_send_cmd, 709 .set_ios = uniphier_sd_set_ios, 710 .get_cd = uniphier_sd_get_cd, 711 }; 712 713 static void uniphier_sd_host_init(struct uniphier_sd_priv *priv) 714 { 715 u32 tmp; 716 717 /* soft reset of the host */ 718 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST); 719 tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX; 720 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); 721 tmp |= UNIPHIER_SD_SOFT_RST_RSTX; 722 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); 723 724 /* FIXME: implement eMMC hw_reset */ 725 726 uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP); 727 728 /* 729 * Connected to 32bit AXI. 730 * This register dropped backward compatibility at version 0x10. 731 * Write an appropriate value depending on the IP version. 732 */ 733 uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000, 734 UNIPHIER_SD_HOST_MODE); 735 736 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) { 737 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); 738 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC; 739 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); 740 } 741 } 742 743 static int uniphier_sd_bind(struct udevice *dev) 744 { 745 struct uniphier_sd_plat *plat = dev_get_platdata(dev); 746 747 return mmc_bind(dev, &plat->mmc, &plat->cfg); 748 } 749 750 static int uniphier_sd_probe(struct udevice *dev) 751 { 752 struct uniphier_sd_plat *plat = dev_get_platdata(dev); 753 struct uniphier_sd_priv *priv = dev_get_priv(dev); 754 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 755 const u32 quirks = dev_get_driver_data(dev); 756 fdt_addr_t base; 757 struct clk clk; 758 int ret; 759 760 base = devfdt_get_addr(dev); 761 if (base == FDT_ADDR_T_NONE) 762 return -EINVAL; 763 764 priv->regbase = devm_ioremap(dev, base, SZ_2K); 765 if (!priv->regbase) 766 return -ENOMEM; 767 768 ret = clk_get_by_index(dev, 0, &clk); 769 if (ret < 0) { 770 dev_err(dev, "failed to get host clock\n"); 771 return ret; 772 } 773 774 /* set to max rate */ 775 priv->mclk = clk_set_rate(&clk, ULONG_MAX); 776 if (IS_ERR_VALUE(priv->mclk)) { 777 dev_err(dev, "failed to set rate for host clock\n"); 778 clk_free(&clk); 779 return priv->mclk; 780 } 781 782 ret = clk_enable(&clk); 783 clk_free(&clk); 784 if (ret) { 785 dev_err(dev, "failed to enable host clock\n"); 786 return ret; 787 } 788 789 plat->cfg.name = dev->name; 790 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; 791 792 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", 793 1)) { 794 case 8: 795 plat->cfg.host_caps |= MMC_MODE_8BIT; 796 break; 797 case 4: 798 plat->cfg.host_caps |= MMC_MODE_4BIT; 799 break; 800 case 1: 801 break; 802 default: 803 dev_err(dev, "Invalid \"bus-width\" value\n"); 804 return -EINVAL; 805 } 806 807 if (quirks) { 808 priv->caps = quirks; 809 } else { 810 priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) & 811 UNIPHIER_SD_VERSION_IP; 812 dev_dbg(dev, "version %x\n", priv->version); 813 if (priv->version >= 0x10) { 814 priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL; 815 priv->caps |= UNIPHIER_SD_CAP_DIV1024; 816 } 817 } 818 819 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable", 820 NULL)) 821 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE; 822 823 uniphier_sd_host_init(priv); 824 825 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; 826 plat->cfg.f_min = priv->mclk / 827 (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512); 828 plat->cfg.f_max = priv->mclk; 829 plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */ 830 831 upriv->mmc = &plat->mmc; 832 833 return 0; 834 } 835 836 static const struct udevice_id uniphier_sd_match[] = { 837 { .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT }, 838 { .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT }, 839 { .compatible = "socionext,uniphier-sdhc", .data = 0 }, 840 { /* sentinel */ } 841 }; 842 843 U_BOOT_DRIVER(uniphier_mmc) = { 844 .name = "uniphier-mmc", 845 .id = UCLASS_MMC, 846 .of_match = uniphier_sd_match, 847 .bind = uniphier_sd_bind, 848 .probe = uniphier_sd_probe, 849 .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv), 850 .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat), 851 .ops = &uniphier_sd_ops, 852 }; 853