1 /* 2 * Copyright (C) 2016 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <fdtdec.h> 11 #include <mmc.h> 12 #include <dm.h> 13 #include <linux/compat.h> 14 #include <linux/io.h> 15 #include <linux/sizes.h> 16 #include <asm/unaligned.h> 17 #include <asm/dma-mapping.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #define UNIPHIER_SD_CMD 0x000 /* command */ 22 #define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ 23 #define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */ 24 #define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */ 25 #define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */ 26 #define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ 27 #define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */ 28 #define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */ 29 #define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */ 30 #define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */ 31 #define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */ 32 #define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */ 33 #define UNIPHIER_SD_ARG 0x008 /* command argument */ 34 #define UNIPHIER_SD_STOP 0x010 /* stop action control */ 35 #define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */ 36 #define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */ 37 #define UNIPHIER_SD_SECCNT 0x014 /* sector counter */ 38 #define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */ 39 #define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */ 40 #define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */ 41 #define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */ 42 #define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */ 43 #define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */ 44 #define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */ 45 #define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */ 46 #define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */ 47 #define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */ 48 #define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */ 49 #define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ 50 #define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */ 51 #define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */ 52 #define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */ 53 #define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */ 54 #define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */ 55 #define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */ 56 #define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */ 57 #define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */ 58 #define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */ 59 #define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */ 60 #define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */ 61 #define UNIPHIER_SD_INFO1_MASK 0x040 62 #define UNIPHIER_SD_INFO2_MASK 0x044 63 #define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */ 64 #define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff 65 #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */ 66 #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ 67 #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ 68 #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ 69 #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ 70 #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ 71 #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ 72 #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ 73 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ 74 #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ 75 #define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ 76 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ 77 #define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ 78 #define UNIPHIER_SD_SIZE 0x04c /* block size */ 79 #define UNIPHIER_SD_OPTION 0x050 80 #define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13) 81 #define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13) 82 #define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13) 83 #define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13) 84 #define UNIPHIER_SD_BUF 0x060 /* read/write buffer */ 85 #define UNIPHIER_SD_EXTMODE 0x1b0 86 #define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ 87 #define UNIPHIER_SD_SOFT_RST 0x1c0 88 #define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */ 89 #define UNIPHIER_SD_VERSION 0x1c4 /* version register */ 90 #define UNIPHIER_SD_VERSION_IP 0xff /* IP version */ 91 #define UNIPHIER_SD_HOST_MODE 0x1c8 92 #define UNIPHIER_SD_IF_MODE 0x1cc 93 #define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */ 94 #define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */ 95 #define UNIPHIER_SD_VOLT_MASK (3 << 0) 96 #define UNIPHIER_SD_VOLT_OFF (0 << 0) 97 #define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */ 98 #define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */ 99 #define UNIPHIER_SD_DMA_MODE 0x410 100 #define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ 101 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ 102 #define UNIPHIER_SD_DMA_CTL 0x414 103 #define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ 104 #define UNIPHIER_SD_DMA_RST 0x418 105 #define UNIPHIER_SD_DMA_RST_RD BIT(9) 106 #define UNIPHIER_SD_DMA_RST_WR BIT(8) 107 #define UNIPHIER_SD_DMA_INFO1 0x420 108 #define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/ 109 #define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */ 110 #define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ 111 #define UNIPHIER_SD_DMA_INFO1_MASK 0x424 112 #define UNIPHIER_SD_DMA_INFO2 0x428 113 #define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17) 114 #define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16) 115 #define UNIPHIER_SD_DMA_INFO2_MASK 0x42c 116 #define UNIPHIER_SD_DMA_ADDR_L 0x440 117 #define UNIPHIER_SD_DMA_ADDR_H 0x444 118 119 /* alignment required by the DMA engine of this controller */ 120 #define UNIPHIER_SD_DMA_MINALIGN 0x10 121 122 struct uniphier_sd_plat { 123 struct mmc_config cfg; 124 struct mmc mmc; 125 }; 126 127 struct uniphier_sd_priv { 128 void __iomem *regbase; 129 unsigned long mclk; 130 unsigned int version; 131 u32 caps; 132 #define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ 133 #define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ 134 #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ 135 }; 136 137 static dma_addr_t __dma_map_single(void *ptr, size_t size, 138 enum dma_data_direction dir) 139 { 140 unsigned long addr = (unsigned long)ptr; 141 142 if (dir == DMA_FROM_DEVICE) 143 invalidate_dcache_range(addr, addr + size); 144 else 145 flush_dcache_range(addr, addr + size); 146 147 return addr; 148 } 149 150 static void __dma_unmap_single(dma_addr_t addr, size_t size, 151 enum dma_data_direction dir) 152 { 153 if (dir != DMA_TO_DEVICE) 154 invalidate_dcache_range(addr, addr + size); 155 } 156 157 static int uniphier_sd_check_error(struct udevice *dev) 158 { 159 struct uniphier_sd_priv *priv = dev_get_priv(dev); 160 u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2); 161 162 if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) { 163 /* 164 * TIMEOUT must be returned for unsupported command. Do not 165 * display error log since this might be a part of sequence to 166 * distinguish between SD and MMC. 167 */ 168 return -ETIMEDOUT; 169 } 170 171 if (info2 & UNIPHIER_SD_INFO2_ERR_TO) { 172 dev_err(dev, "timeout error\n"); 173 return -ETIMEDOUT; 174 } 175 176 if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC | 177 UNIPHIER_SD_INFO2_ERR_IDX)) { 178 dev_err(dev, "communication out of sync\n"); 179 return -EILSEQ; 180 } 181 182 if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR | 183 UNIPHIER_SD_INFO2_ERR_ILW)) { 184 dev_err(dev, "illegal access\n"); 185 return -EIO; 186 } 187 188 return 0; 189 } 190 191 static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg, 192 u32 flag) 193 { 194 struct uniphier_sd_priv *priv = dev_get_priv(dev); 195 long wait = 1000000; 196 int ret; 197 198 while (!(readl(priv->regbase + reg) & flag)) { 199 if (wait-- < 0) { 200 dev_err(dev, "timeout\n"); 201 return -ETIMEDOUT; 202 } 203 204 ret = uniphier_sd_check_error(dev); 205 if (ret) 206 return ret; 207 208 udelay(1); 209 } 210 211 return 0; 212 } 213 214 static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf, 215 uint blocksize) 216 { 217 struct uniphier_sd_priv *priv = dev_get_priv(dev); 218 int i, ret; 219 220 /* wait until the buffer is filled with data */ 221 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2, 222 UNIPHIER_SD_INFO2_BRE); 223 if (ret) 224 return ret; 225 226 /* 227 * Clear the status flag _before_ read the buffer out because 228 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered. 229 */ 230 writel(0, priv->regbase + UNIPHIER_SD_INFO2); 231 232 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { 233 for (i = 0; i < blocksize / 4; i++) 234 *(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF); 235 } else { 236 for (i = 0; i < blocksize / 4; i++) 237 put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF), 238 (*pbuf)++); 239 } 240 241 return 0; 242 } 243 244 static int uniphier_sd_pio_write_one_block(struct udevice *dev, 245 const u32 **pbuf, uint blocksize) 246 { 247 struct uniphier_sd_priv *priv = dev_get_priv(dev); 248 int i, ret; 249 250 /* wait until the buffer becomes empty */ 251 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2, 252 UNIPHIER_SD_INFO2_BWE); 253 if (ret) 254 return ret; 255 256 writel(0, priv->regbase + UNIPHIER_SD_INFO2); 257 258 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { 259 for (i = 0; i < blocksize / 4; i++) 260 writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF); 261 } else { 262 for (i = 0; i < blocksize / 4; i++) 263 writel(get_unaligned((*pbuf)++), 264 priv->regbase + UNIPHIER_SD_BUF); 265 } 266 267 return 0; 268 } 269 270 static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data) 271 { 272 u32 *dest = (u32 *)data->dest; 273 const u32 *src = (const u32 *)data->src; 274 int i, ret; 275 276 for (i = 0; i < data->blocks; i++) { 277 if (data->flags & MMC_DATA_READ) 278 ret = uniphier_sd_pio_read_one_block(dev, &dest, 279 data->blocksize); 280 else 281 ret = uniphier_sd_pio_write_one_block(dev, &src, 282 data->blocksize); 283 if (ret) 284 return ret; 285 } 286 287 return 0; 288 } 289 290 static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv, 291 dma_addr_t dma_addr) 292 { 293 u32 tmp; 294 295 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1); 296 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2); 297 298 /* enable DMA */ 299 tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE); 300 tmp |= UNIPHIER_SD_EXTMODE_DMA_EN; 301 writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE); 302 303 writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L); 304 305 /* suppress the warning "right shift count >= width of type" */ 306 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); 307 308 writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H); 309 310 writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL); 311 } 312 313 static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, 314 unsigned int blocks) 315 { 316 struct uniphier_sd_priv *priv = dev_get_priv(dev); 317 long wait = 1000000 + 10 * blocks; 318 319 while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) { 320 if (wait-- < 0) { 321 dev_err(dev, "timeout during DMA\n"); 322 return -ETIMEDOUT; 323 } 324 325 udelay(10); 326 } 327 328 if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) { 329 dev_err(dev, "error during DMA\n"); 330 return -EIO; 331 } 332 333 return 0; 334 } 335 336 static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) 337 { 338 struct uniphier_sd_priv *priv = dev_get_priv(dev); 339 size_t len = data->blocks * data->blocksize; 340 void *buf; 341 enum dma_data_direction dir; 342 dma_addr_t dma_addr; 343 u32 poll_flag, tmp; 344 int ret; 345 346 tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE); 347 348 if (data->flags & MMC_DATA_READ) { 349 buf = data->dest; 350 dir = DMA_FROM_DEVICE; 351 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2; 352 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD; 353 } else { 354 buf = (void *)data->src; 355 dir = DMA_TO_DEVICE; 356 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR; 357 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD; 358 } 359 360 writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE); 361 362 dma_addr = __dma_map_single(buf, len, dir); 363 364 uniphier_sd_dma_start(priv, dma_addr); 365 366 ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); 367 368 __dma_unmap_single(dma_addr, len, dir); 369 370 return ret; 371 } 372 373 /* check if the address is DMA'able */ 374 static bool uniphier_sd_addr_is_dmaable(unsigned long addr) 375 { 376 if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN)) 377 return false; 378 379 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ 380 defined(CONFIG_SPL_BUILD) 381 /* 382 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways 383 * of L2, which is unreachable from the DMA engine. 384 */ 385 if (addr < CONFIG_SPL_STACK) 386 return false; 387 #endif 388 389 return true; 390 } 391 392 static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 393 struct mmc_data *data) 394 { 395 struct uniphier_sd_priv *priv = dev_get_priv(dev); 396 int ret; 397 u32 tmp; 398 399 if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { 400 dev_err(dev, "command busy\n"); 401 return -EBUSY; 402 } 403 404 /* clear all status flags */ 405 writel(0, priv->regbase + UNIPHIER_SD_INFO1); 406 writel(0, priv->regbase + UNIPHIER_SD_INFO2); 407 408 /* disable DMA once */ 409 tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE); 410 tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN; 411 writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE); 412 413 writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG); 414 415 tmp = cmd->cmdidx; 416 417 if (data) { 418 writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE); 419 writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT); 420 421 /* Do not send CMD12 automatically */ 422 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA; 423 424 if (data->blocks > 1) 425 tmp |= UNIPHIER_SD_CMD_MULTI; 426 427 if (data->flags & MMC_DATA_READ) 428 tmp |= UNIPHIER_SD_CMD_RD; 429 } 430 431 /* 432 * Do not use the response type auto-detection on this hardware. 433 * CMD8, for example, has different response types on SD and eMMC, 434 * while this controller always assumes the response type for SD. 435 * Set the response type manually. 436 */ 437 switch (cmd->resp_type) { 438 case MMC_RSP_NONE: 439 tmp |= UNIPHIER_SD_CMD_RSP_NONE; 440 break; 441 case MMC_RSP_R1: 442 tmp |= UNIPHIER_SD_CMD_RSP_R1; 443 break; 444 case MMC_RSP_R1b: 445 tmp |= UNIPHIER_SD_CMD_RSP_R1B; 446 break; 447 case MMC_RSP_R2: 448 tmp |= UNIPHIER_SD_CMD_RSP_R2; 449 break; 450 case MMC_RSP_R3: 451 tmp |= UNIPHIER_SD_CMD_RSP_R3; 452 break; 453 default: 454 dev_err(dev, "unknown response type\n"); 455 return -EINVAL; 456 } 457 458 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", 459 cmd->cmdidx, tmp, cmd->cmdarg); 460 writel(tmp, priv->regbase + UNIPHIER_SD_CMD); 461 462 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, 463 UNIPHIER_SD_INFO1_RSP); 464 if (ret) 465 return ret; 466 467 if (cmd->resp_type & MMC_RSP_136) { 468 u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76); 469 u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54); 470 u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32); 471 u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10); 472 473 cmd->response[0] = (rsp_127_104 & 0xffffff) << 8 | 474 (rsp_103_72 & 0xff); 475 cmd->response[1] = (rsp_103_72 & 0xffffff) << 8 | 476 (rsp_71_40 & 0xff); 477 cmd->response[2] = (rsp_71_40 & 0xffffff) << 8 | 478 (rsp_39_8 & 0xff); 479 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; 480 } else { 481 /* bit 39-8 */ 482 cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10); 483 } 484 485 if (data) { 486 /* use DMA if the HW supports it and the buffer is aligned */ 487 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL && 488 uniphier_sd_addr_is_dmaable((long)data->src)) 489 ret = uniphier_sd_dma_xfer(dev, data); 490 else 491 ret = uniphier_sd_pio_xfer(dev, data); 492 493 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, 494 UNIPHIER_SD_INFO1_CMP); 495 if (ret) 496 return ret; 497 } 498 499 return ret; 500 } 501 502 static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv, 503 struct mmc *mmc) 504 { 505 u32 val, tmp; 506 507 switch (mmc->bus_width) { 508 case 1: 509 val = UNIPHIER_SD_OPTION_WIDTH_1; 510 break; 511 case 4: 512 val = UNIPHIER_SD_OPTION_WIDTH_4; 513 break; 514 case 8: 515 val = UNIPHIER_SD_OPTION_WIDTH_8; 516 break; 517 default: 518 return -EINVAL; 519 } 520 521 tmp = readl(priv->regbase + UNIPHIER_SD_OPTION); 522 tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK; 523 tmp |= val; 524 writel(tmp, priv->regbase + UNIPHIER_SD_OPTION); 525 526 return 0; 527 } 528 529 static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv, 530 struct mmc *mmc) 531 { 532 u32 tmp; 533 534 tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE); 535 if (mmc->ddr_mode) 536 tmp |= UNIPHIER_SD_IF_MODE_DDR; 537 else 538 tmp &= ~UNIPHIER_SD_IF_MODE_DDR; 539 writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE); 540 } 541 542 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, 543 struct mmc *mmc) 544 { 545 unsigned int divisor; 546 u32 val, tmp; 547 548 if (!mmc->clock) 549 return; 550 551 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); 552 553 if (divisor <= 1) 554 val = UNIPHIER_SD_CLKCTL_DIV1; 555 else if (divisor <= 2) 556 val = UNIPHIER_SD_CLKCTL_DIV2; 557 else if (divisor <= 4) 558 val = UNIPHIER_SD_CLKCTL_DIV4; 559 else if (divisor <= 8) 560 val = UNIPHIER_SD_CLKCTL_DIV8; 561 else if (divisor <= 16) 562 val = UNIPHIER_SD_CLKCTL_DIV16; 563 else if (divisor <= 32) 564 val = UNIPHIER_SD_CLKCTL_DIV32; 565 else if (divisor <= 64) 566 val = UNIPHIER_SD_CLKCTL_DIV64; 567 else if (divisor <= 128) 568 val = UNIPHIER_SD_CLKCTL_DIV128; 569 else if (divisor <= 256) 570 val = UNIPHIER_SD_CLKCTL_DIV256; 571 else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024)) 572 val = UNIPHIER_SD_CLKCTL_DIV512; 573 else 574 val = UNIPHIER_SD_CLKCTL_DIV1024; 575 576 tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL); 577 if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN && 578 (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val) 579 return; 580 581 /* stop the clock before changing its rate to avoid a glitch signal */ 582 tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN; 583 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); 584 585 tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK; 586 tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN; 587 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); 588 589 tmp |= UNIPHIER_SD_CLKCTL_SCLKEN; 590 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); 591 592 udelay(1000); 593 } 594 595 static int uniphier_sd_set_ios(struct udevice *dev) 596 { 597 struct uniphier_sd_priv *priv = dev_get_priv(dev); 598 struct mmc *mmc = mmc_get_mmc_dev(dev); 599 int ret; 600 601 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n", 602 mmc->clock, mmc->ddr_mode, mmc->bus_width); 603 604 ret = uniphier_sd_set_bus_width(priv, mmc); 605 if (ret) 606 return ret; 607 uniphier_sd_set_ddr_mode(priv, mmc); 608 uniphier_sd_set_clk_rate(priv, mmc); 609 610 return 0; 611 } 612 613 static int uniphier_sd_get_cd(struct udevice *dev) 614 { 615 struct uniphier_sd_priv *priv = dev_get_priv(dev); 616 617 if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE) 618 return 1; 619 620 return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) & 621 UNIPHIER_SD_INFO1_CD); 622 } 623 624 static const struct dm_mmc_ops uniphier_sd_ops = { 625 .send_cmd = uniphier_sd_send_cmd, 626 .set_ios = uniphier_sd_set_ios, 627 .get_cd = uniphier_sd_get_cd, 628 }; 629 630 static void uniphier_sd_host_init(struct uniphier_sd_priv *priv) 631 { 632 u32 tmp; 633 634 /* soft reset of the host */ 635 tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST); 636 tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX; 637 writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST); 638 tmp |= UNIPHIER_SD_SOFT_RST_RSTX; 639 writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST); 640 641 /* FIXME: implement eMMC hw_reset */ 642 643 writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP); 644 645 /* 646 * Connected to 32bit AXI. 647 * This register dropped backward compatibility at version 0x10. 648 * Write an appropriate value depending on the IP version. 649 */ 650 writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000, 651 priv->regbase + UNIPHIER_SD_HOST_MODE); 652 653 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) { 654 tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE); 655 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC; 656 writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE); 657 } 658 } 659 660 static int uniphier_sd_bind(struct udevice *dev) 661 { 662 struct uniphier_sd_plat *plat = dev_get_platdata(dev); 663 664 return mmc_bind(dev, &plat->mmc, &plat->cfg); 665 } 666 667 static int uniphier_sd_probe(struct udevice *dev) 668 { 669 struct uniphier_sd_plat *plat = dev_get_platdata(dev); 670 struct uniphier_sd_priv *priv = dev_get_priv(dev); 671 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 672 fdt_addr_t base; 673 struct clk clk; 674 int ret; 675 676 base = devfdt_get_addr(dev); 677 if (base == FDT_ADDR_T_NONE) 678 return -EINVAL; 679 680 priv->regbase = devm_ioremap(dev, base, SZ_2K); 681 if (!priv->regbase) 682 return -ENOMEM; 683 684 ret = clk_get_by_index(dev, 0, &clk); 685 if (ret < 0) { 686 dev_err(dev, "failed to get host clock\n"); 687 return ret; 688 } 689 690 /* set to max rate */ 691 priv->mclk = clk_set_rate(&clk, ULONG_MAX); 692 if (IS_ERR_VALUE(priv->mclk)) { 693 dev_err(dev, "failed to set rate for host clock\n"); 694 clk_free(&clk); 695 return priv->mclk; 696 } 697 698 ret = clk_enable(&clk); 699 clk_free(&clk); 700 if (ret) { 701 dev_err(dev, "failed to enable host clock\n"); 702 return ret; 703 } 704 705 plat->cfg.name = dev->name; 706 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; 707 708 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", 709 1)) { 710 case 8: 711 plat->cfg.host_caps |= MMC_MODE_8BIT; 712 break; 713 case 4: 714 plat->cfg.host_caps |= MMC_MODE_4BIT; 715 break; 716 case 1: 717 break; 718 default: 719 dev_err(dev, "Invalid \"bus-width\" value\n"); 720 return -EINVAL; 721 } 722 723 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable", 724 NULL)) 725 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE; 726 727 priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) & 728 UNIPHIER_SD_VERSION_IP; 729 dev_dbg(dev, "version %x\n", priv->version); 730 if (priv->version >= 0x10) { 731 priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL; 732 priv->caps |= UNIPHIER_SD_CAP_DIV1024; 733 } 734 735 uniphier_sd_host_init(priv); 736 737 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; 738 plat->cfg.f_min = priv->mclk / 739 (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512); 740 plat->cfg.f_max = priv->mclk; 741 plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */ 742 743 upriv->mmc = &plat->mmc; 744 745 return 0; 746 } 747 748 static const struct udevice_id uniphier_sd_match[] = { 749 { .compatible = "socionext,uniphier-sdhc" }, 750 { /* sentinel */ } 751 }; 752 753 U_BOOT_DRIVER(uniphier_mmc) = { 754 .name = "uniphier-mmc", 755 .id = UCLASS_MMC, 756 .of_match = uniphier_sd_match, 757 .bind = uniphier_sd_bind, 758 .probe = uniphier_sd_probe, 759 .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv), 760 .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat), 761 .ops = &uniphier_sd_ops, 762 }; 763