1 /* 2 * Copyright (C) 2016 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <fdtdec.h> 11 #include <mmc.h> 12 #include <dm.h> 13 #include <linux/compat.h> 14 #include <linux/dma-direction.h> 15 #include <linux/io.h> 16 #include <linux/sizes.h> 17 #include <power/regulator.h> 18 #include <asm/unaligned.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #define UNIPHIER_SD_CMD 0x000 /* command */ 23 #define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ 24 #define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */ 25 #define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */ 26 #define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */ 27 #define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ 28 #define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */ 29 #define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */ 30 #define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */ 31 #define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */ 32 #define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */ 33 #define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */ 34 #define UNIPHIER_SD_ARG 0x008 /* command argument */ 35 #define UNIPHIER_SD_STOP 0x010 /* stop action control */ 36 #define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */ 37 #define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */ 38 #define UNIPHIER_SD_SECCNT 0x014 /* sector counter */ 39 #define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */ 40 #define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */ 41 #define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */ 42 #define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */ 43 #define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */ 44 #define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */ 45 #define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */ 46 #define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */ 47 #define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */ 48 #define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */ 49 #define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */ 50 #define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ 51 #define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */ 52 #define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */ 53 #define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */ 54 #define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */ 55 #define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */ 56 #define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */ 57 #define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */ 58 #define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */ 59 #define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */ 60 #define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */ 61 #define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */ 62 #define UNIPHIER_SD_INFO1_MASK 0x040 63 #define UNIPHIER_SD_INFO2_MASK 0x044 64 #define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */ 65 #define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff 66 #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */ 67 #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ 68 #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ 69 #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ 70 #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ 71 #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ 72 #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ 73 #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ 74 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ 75 #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ 76 #define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ 77 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ 78 #define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ 79 #define UNIPHIER_SD_SIZE 0x04c /* block size */ 80 #define UNIPHIER_SD_OPTION 0x050 81 #define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13) 82 #define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13) 83 #define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13) 84 #define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13) 85 #define UNIPHIER_SD_BUF 0x060 /* read/write buffer */ 86 #define UNIPHIER_SD_EXTMODE 0x1b0 87 #define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ 88 #define UNIPHIER_SD_SOFT_RST 0x1c0 89 #define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */ 90 #define UNIPHIER_SD_VERSION 0x1c4 /* version register */ 91 #define UNIPHIER_SD_VERSION_IP 0xff /* IP version */ 92 #define UNIPHIER_SD_HOST_MODE 0x1c8 93 #define UNIPHIER_SD_IF_MODE 0x1cc 94 #define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */ 95 #define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */ 96 #define UNIPHIER_SD_VOLT_MASK (3 << 0) 97 #define UNIPHIER_SD_VOLT_OFF (0 << 0) 98 #define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */ 99 #define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */ 100 #define UNIPHIER_SD_DMA_MODE 0x410 101 #define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ 102 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ 103 #define UNIPHIER_SD_DMA_CTL 0x414 104 #define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ 105 #define UNIPHIER_SD_DMA_RST 0x418 106 #define UNIPHIER_SD_DMA_RST_RD BIT(9) 107 #define UNIPHIER_SD_DMA_RST_WR BIT(8) 108 #define UNIPHIER_SD_DMA_INFO1 0x420 109 #define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/ 110 #define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */ 111 #define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ 112 #define UNIPHIER_SD_DMA_INFO1_MASK 0x424 113 #define UNIPHIER_SD_DMA_INFO2 0x428 114 #define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17) 115 #define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16) 116 #define UNIPHIER_SD_DMA_INFO2_MASK 0x42c 117 #define UNIPHIER_SD_DMA_ADDR_L 0x440 118 #define UNIPHIER_SD_DMA_ADDR_H 0x444 119 120 /* alignment required by the DMA engine of this controller */ 121 #define UNIPHIER_SD_DMA_MINALIGN 0x10 122 123 struct uniphier_sd_plat { 124 struct mmc_config cfg; 125 struct mmc mmc; 126 }; 127 128 struct uniphier_sd_priv { 129 void __iomem *regbase; 130 unsigned long mclk; 131 unsigned int version; 132 u32 caps; 133 #define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ 134 #define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ 135 #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ 136 #define UNIPHIER_SD_CAP_64BIT BIT(3) /* Controller is 64bit */ 137 }; 138 139 static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, unsigned int reg) 140 { 141 if (priv->caps & UNIPHIER_SD_CAP_64BIT) 142 return readq(priv->regbase + (reg << 1)); 143 else 144 return readq(priv->regbase + reg); 145 } 146 147 static void uniphier_sd_writeq(struct uniphier_sd_priv *priv, 148 u64 val, unsigned int reg) 149 { 150 if (priv->caps & UNIPHIER_SD_CAP_64BIT) 151 writeq(val, priv->regbase + (reg << 1)); 152 else 153 writeq(val, priv->regbase + reg); 154 } 155 156 static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg) 157 { 158 if (priv->caps & UNIPHIER_SD_CAP_64BIT) 159 return readl(priv->regbase + (reg << 1)); 160 else 161 return readl(priv->regbase + reg); 162 } 163 164 static void uniphier_sd_writel(struct uniphier_sd_priv *priv, 165 u32 val, unsigned int reg) 166 { 167 if (priv->caps & UNIPHIER_SD_CAP_64BIT) 168 writel(val, priv->regbase + (reg << 1)); 169 else 170 writel(val, priv->regbase + reg); 171 } 172 173 static dma_addr_t __dma_map_single(void *ptr, size_t size, 174 enum dma_data_direction dir) 175 { 176 unsigned long addr = (unsigned long)ptr; 177 178 if (dir == DMA_FROM_DEVICE) 179 invalidate_dcache_range(addr, addr + size); 180 else 181 flush_dcache_range(addr, addr + size); 182 183 return addr; 184 } 185 186 static void __dma_unmap_single(dma_addr_t addr, size_t size, 187 enum dma_data_direction dir) 188 { 189 if (dir != DMA_TO_DEVICE) 190 invalidate_dcache_range(addr, addr + size); 191 } 192 193 static int uniphier_sd_check_error(struct udevice *dev) 194 { 195 struct uniphier_sd_priv *priv = dev_get_priv(dev); 196 u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2); 197 198 if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) { 199 /* 200 * TIMEOUT must be returned for unsupported command. Do not 201 * display error log since this might be a part of sequence to 202 * distinguish between SD and MMC. 203 */ 204 return -ETIMEDOUT; 205 } 206 207 if (info2 & UNIPHIER_SD_INFO2_ERR_TO) { 208 dev_err(dev, "timeout error\n"); 209 return -ETIMEDOUT; 210 } 211 212 if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC | 213 UNIPHIER_SD_INFO2_ERR_IDX)) { 214 dev_err(dev, "communication out of sync\n"); 215 return -EILSEQ; 216 } 217 218 if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR | 219 UNIPHIER_SD_INFO2_ERR_ILW)) { 220 dev_err(dev, "illegal access\n"); 221 return -EIO; 222 } 223 224 return 0; 225 } 226 227 static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg, 228 u32 flag) 229 { 230 struct uniphier_sd_priv *priv = dev_get_priv(dev); 231 long wait = 1000000; 232 int ret; 233 234 while (!(uniphier_sd_readl(priv, reg) & flag)) { 235 if (wait-- < 0) { 236 dev_err(dev, "timeout\n"); 237 return -ETIMEDOUT; 238 } 239 240 ret = uniphier_sd_check_error(dev); 241 if (ret) 242 return ret; 243 244 udelay(1); 245 } 246 247 return 0; 248 } 249 250 static int uniphier_sd_pio_read_one_block(struct udevice *dev, char *pbuf, 251 uint blocksize) 252 { 253 struct uniphier_sd_priv *priv = dev_get_priv(dev); 254 int i, ret; 255 256 /* wait until the buffer is filled with data */ 257 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2, 258 UNIPHIER_SD_INFO2_BRE); 259 if (ret) 260 return ret; 261 262 /* 263 * Clear the status flag _before_ read the buffer out because 264 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered. 265 */ 266 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); 267 268 if (priv->caps & UNIPHIER_SD_CAP_64BIT) { 269 u64 *buf = (u64 *)pbuf; 270 if (likely(IS_ALIGNED((uintptr_t)buf, 8))) { 271 for (i = 0; i < blocksize / 8; i++) { 272 *buf++ = uniphier_sd_readq(priv, 273 UNIPHIER_SD_BUF); 274 } 275 } else { 276 for (i = 0; i < blocksize / 8; i++) { 277 u64 data; 278 data = uniphier_sd_readq(priv, 279 UNIPHIER_SD_BUF); 280 put_unaligned(data, buf++); 281 } 282 } 283 } else { 284 u32 *buf = (u32 *)pbuf; 285 if (likely(IS_ALIGNED((uintptr_t)buf, 4))) { 286 for (i = 0; i < blocksize / 4; i++) { 287 *buf++ = uniphier_sd_readl(priv, 288 UNIPHIER_SD_BUF); 289 } 290 } else { 291 for (i = 0; i < blocksize / 4; i++) { 292 u32 data; 293 data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF); 294 put_unaligned(data, buf++); 295 } 296 } 297 } 298 299 return 0; 300 } 301 302 static int uniphier_sd_pio_write_one_block(struct udevice *dev, 303 const char *pbuf, uint blocksize) 304 { 305 struct uniphier_sd_priv *priv = dev_get_priv(dev); 306 int i, ret; 307 308 /* wait until the buffer becomes empty */ 309 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2, 310 UNIPHIER_SD_INFO2_BWE); 311 if (ret) 312 return ret; 313 314 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); 315 316 if (priv->caps & UNIPHIER_SD_CAP_64BIT) { 317 const u64 *buf = (const u64 *)pbuf; 318 if (likely(IS_ALIGNED((uintptr_t)buf, 8))) { 319 for (i = 0; i < blocksize / 8; i++) { 320 uniphier_sd_writeq(priv, *buf++, 321 UNIPHIER_SD_BUF); 322 } 323 } else { 324 for (i = 0; i < blocksize / 8; i++) { 325 u64 data = get_unaligned(buf++); 326 uniphier_sd_writeq(priv, data, 327 UNIPHIER_SD_BUF); 328 } 329 } 330 } else { 331 const u32 *buf = (const u32 *)pbuf; 332 if (likely(IS_ALIGNED((uintptr_t)buf, 4))) { 333 for (i = 0; i < blocksize / 4; i++) { 334 uniphier_sd_writel(priv, *buf++, 335 UNIPHIER_SD_BUF); 336 } 337 } else { 338 for (i = 0; i < blocksize / 4; i++) { 339 u32 data = get_unaligned(buf++); 340 uniphier_sd_writel(priv, data, 341 UNIPHIER_SD_BUF); 342 } 343 } 344 } 345 346 return 0; 347 } 348 349 static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data) 350 { 351 const char *src = data->src; 352 char *dest = data->dest; 353 int i, ret; 354 355 for (i = 0; i < data->blocks; i++) { 356 if (data->flags & MMC_DATA_READ) 357 ret = uniphier_sd_pio_read_one_block(dev, dest, 358 data->blocksize); 359 else 360 ret = uniphier_sd_pio_write_one_block(dev, src, 361 data->blocksize); 362 if (ret) 363 return ret; 364 365 if (data->flags & MMC_DATA_READ) 366 dest += data->blocksize; 367 else 368 src += data->blocksize; 369 } 370 371 return 0; 372 } 373 374 static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv, 375 dma_addr_t dma_addr) 376 { 377 u32 tmp; 378 379 uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1); 380 uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2); 381 382 /* enable DMA */ 383 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); 384 tmp |= UNIPHIER_SD_EXTMODE_DMA_EN; 385 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); 386 387 uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L); 388 389 /* suppress the warning "right shift count >= width of type" */ 390 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); 391 392 uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H); 393 394 uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL); 395 } 396 397 static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, 398 unsigned int blocks) 399 { 400 struct uniphier_sd_priv *priv = dev_get_priv(dev); 401 long wait = 1000000 + 10 * blocks; 402 403 while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) { 404 if (wait-- < 0) { 405 dev_err(dev, "timeout during DMA\n"); 406 return -ETIMEDOUT; 407 } 408 409 udelay(10); 410 } 411 412 if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) { 413 dev_err(dev, "error during DMA\n"); 414 return -EIO; 415 } 416 417 return 0; 418 } 419 420 static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) 421 { 422 struct uniphier_sd_priv *priv = dev_get_priv(dev); 423 size_t len = data->blocks * data->blocksize; 424 void *buf; 425 enum dma_data_direction dir; 426 dma_addr_t dma_addr; 427 u32 poll_flag, tmp; 428 int ret; 429 430 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); 431 432 if (data->flags & MMC_DATA_READ) { 433 buf = data->dest; 434 dir = DMA_FROM_DEVICE; 435 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2; 436 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD; 437 } else { 438 buf = (void *)data->src; 439 dir = DMA_TO_DEVICE; 440 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR; 441 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD; 442 } 443 444 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); 445 446 dma_addr = __dma_map_single(buf, len, dir); 447 448 uniphier_sd_dma_start(priv, dma_addr); 449 450 ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); 451 452 __dma_unmap_single(dma_addr, len, dir); 453 454 return ret; 455 } 456 457 /* check if the address is DMA'able */ 458 static bool uniphier_sd_addr_is_dmaable(unsigned long addr) 459 { 460 if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN)) 461 return false; 462 463 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ 464 defined(CONFIG_SPL_BUILD) 465 /* 466 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways 467 * of L2, which is unreachable from the DMA engine. 468 */ 469 if (addr < CONFIG_SPL_STACK) 470 return false; 471 #endif 472 473 return true; 474 } 475 476 static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 477 struct mmc_data *data) 478 { 479 struct uniphier_sd_priv *priv = dev_get_priv(dev); 480 int ret; 481 u32 tmp; 482 483 if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { 484 dev_err(dev, "command busy\n"); 485 return -EBUSY; 486 } 487 488 /* clear all status flags */ 489 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1); 490 uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2); 491 492 /* disable DMA once */ 493 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE); 494 tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN; 495 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE); 496 497 uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG); 498 499 tmp = cmd->cmdidx; 500 501 if (data) { 502 uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE); 503 uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT); 504 505 /* Do not send CMD12 automatically */ 506 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA; 507 508 if (data->blocks > 1) 509 tmp |= UNIPHIER_SD_CMD_MULTI; 510 511 if (data->flags & MMC_DATA_READ) 512 tmp |= UNIPHIER_SD_CMD_RD; 513 } 514 515 /* 516 * Do not use the response type auto-detection on this hardware. 517 * CMD8, for example, has different response types on SD and eMMC, 518 * while this controller always assumes the response type for SD. 519 * Set the response type manually. 520 */ 521 switch (cmd->resp_type) { 522 case MMC_RSP_NONE: 523 tmp |= UNIPHIER_SD_CMD_RSP_NONE; 524 break; 525 case MMC_RSP_R1: 526 tmp |= UNIPHIER_SD_CMD_RSP_R1; 527 break; 528 case MMC_RSP_R1b: 529 tmp |= UNIPHIER_SD_CMD_RSP_R1B; 530 break; 531 case MMC_RSP_R2: 532 tmp |= UNIPHIER_SD_CMD_RSP_R2; 533 break; 534 case MMC_RSP_R3: 535 tmp |= UNIPHIER_SD_CMD_RSP_R3; 536 break; 537 default: 538 dev_err(dev, "unknown response type\n"); 539 return -EINVAL; 540 } 541 542 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", 543 cmd->cmdidx, tmp, cmd->cmdarg); 544 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD); 545 546 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, 547 UNIPHIER_SD_INFO1_RSP); 548 if (ret) 549 return ret; 550 551 if (cmd->resp_type & MMC_RSP_136) { 552 u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76); 553 u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54); 554 u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32); 555 u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); 556 557 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) | 558 ((rsp_103_72 & 0xff000000) >> 24); 559 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) | 560 ((rsp_71_40 & 0xff000000) >> 24); 561 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) | 562 ((rsp_39_8 & 0xff000000) >> 24); 563 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; 564 } else { 565 /* bit 39-8 */ 566 cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10); 567 } 568 569 if (data) { 570 /* use DMA if the HW supports it and the buffer is aligned */ 571 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL && 572 uniphier_sd_addr_is_dmaable((long)data->src)) 573 ret = uniphier_sd_dma_xfer(dev, data); 574 else 575 ret = uniphier_sd_pio_xfer(dev, data); 576 577 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1, 578 UNIPHIER_SD_INFO1_CMP); 579 if (ret) 580 return ret; 581 } 582 583 return ret; 584 } 585 586 static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv, 587 struct mmc *mmc) 588 { 589 u32 val, tmp; 590 591 switch (mmc->bus_width) { 592 case 1: 593 val = UNIPHIER_SD_OPTION_WIDTH_1; 594 break; 595 case 4: 596 val = UNIPHIER_SD_OPTION_WIDTH_4; 597 break; 598 case 8: 599 val = UNIPHIER_SD_OPTION_WIDTH_8; 600 break; 601 default: 602 return -EINVAL; 603 } 604 605 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION); 606 tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK; 607 tmp |= val; 608 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION); 609 610 return 0; 611 } 612 613 static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv, 614 struct mmc *mmc) 615 { 616 u32 tmp; 617 618 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE); 619 if (mmc->ddr_mode) 620 tmp |= UNIPHIER_SD_IF_MODE_DDR; 621 else 622 tmp &= ~UNIPHIER_SD_IF_MODE_DDR; 623 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE); 624 } 625 626 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, 627 struct mmc *mmc) 628 { 629 unsigned int divisor; 630 u32 val, tmp; 631 632 if (!mmc->clock) 633 return; 634 635 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); 636 637 if (divisor <= 1) 638 val = UNIPHIER_SD_CLKCTL_DIV1; 639 else if (divisor <= 2) 640 val = UNIPHIER_SD_CLKCTL_DIV2; 641 else if (divisor <= 4) 642 val = UNIPHIER_SD_CLKCTL_DIV4; 643 else if (divisor <= 8) 644 val = UNIPHIER_SD_CLKCTL_DIV8; 645 else if (divisor <= 16) 646 val = UNIPHIER_SD_CLKCTL_DIV16; 647 else if (divisor <= 32) 648 val = UNIPHIER_SD_CLKCTL_DIV32; 649 else if (divisor <= 64) 650 val = UNIPHIER_SD_CLKCTL_DIV64; 651 else if (divisor <= 128) 652 val = UNIPHIER_SD_CLKCTL_DIV128; 653 else if (divisor <= 256) 654 val = UNIPHIER_SD_CLKCTL_DIV256; 655 else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024)) 656 val = UNIPHIER_SD_CLKCTL_DIV512; 657 else 658 val = UNIPHIER_SD_CLKCTL_DIV1024; 659 660 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL); 661 if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN && 662 (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val) 663 return; 664 665 /* stop the clock before changing its rate to avoid a glitch signal */ 666 tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN; 667 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); 668 669 tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK; 670 tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN; 671 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); 672 673 tmp |= UNIPHIER_SD_CLKCTL_SCLKEN; 674 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL); 675 676 udelay(1000); 677 } 678 679 static int uniphier_sd_set_ios(struct udevice *dev) 680 { 681 struct uniphier_sd_priv *priv = dev_get_priv(dev); 682 struct mmc *mmc = mmc_get_mmc_dev(dev); 683 int ret; 684 685 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n", 686 mmc->clock, mmc->ddr_mode, mmc->bus_width); 687 688 ret = uniphier_sd_set_bus_width(priv, mmc); 689 if (ret) 690 return ret; 691 uniphier_sd_set_ddr_mode(priv, mmc); 692 uniphier_sd_set_clk_rate(priv, mmc); 693 694 return 0; 695 } 696 697 static int uniphier_sd_get_cd(struct udevice *dev) 698 { 699 struct uniphier_sd_priv *priv = dev_get_priv(dev); 700 701 if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE) 702 return 1; 703 704 return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) & 705 UNIPHIER_SD_INFO1_CD); 706 } 707 708 static const struct dm_mmc_ops uniphier_sd_ops = { 709 .send_cmd = uniphier_sd_send_cmd, 710 .set_ios = uniphier_sd_set_ios, 711 .get_cd = uniphier_sd_get_cd, 712 }; 713 714 static void uniphier_sd_host_init(struct uniphier_sd_priv *priv) 715 { 716 u32 tmp; 717 718 /* soft reset of the host */ 719 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST); 720 tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX; 721 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); 722 tmp |= UNIPHIER_SD_SOFT_RST_RSTX; 723 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST); 724 725 /* FIXME: implement eMMC hw_reset */ 726 727 uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP); 728 729 /* 730 * Connected to 32bit AXI. 731 * This register dropped backward compatibility at version 0x10. 732 * Write an appropriate value depending on the IP version. 733 */ 734 uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000, 735 UNIPHIER_SD_HOST_MODE); 736 737 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) { 738 tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE); 739 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC; 740 uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE); 741 } 742 } 743 744 static int uniphier_sd_bind(struct udevice *dev) 745 { 746 struct uniphier_sd_plat *plat = dev_get_platdata(dev); 747 748 return mmc_bind(dev, &plat->mmc, &plat->cfg); 749 } 750 751 static int uniphier_sd_probe(struct udevice *dev) 752 { 753 struct uniphier_sd_plat *plat = dev_get_platdata(dev); 754 struct uniphier_sd_priv *priv = dev_get_priv(dev); 755 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 756 const u32 quirks = dev_get_driver_data(dev); 757 fdt_addr_t base; 758 struct clk clk; 759 int ret; 760 #ifdef CONFIG_DM_REGULATOR 761 struct udevice *vqmmc_dev; 762 #endif 763 764 base = devfdt_get_addr(dev); 765 if (base == FDT_ADDR_T_NONE) 766 return -EINVAL; 767 768 priv->regbase = devm_ioremap(dev, base, SZ_2K); 769 if (!priv->regbase) 770 return -ENOMEM; 771 772 #ifdef CONFIG_DM_REGULATOR 773 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev); 774 if (!ret) { 775 /* Set the regulator to 3.3V until we support 1.8V modes */ 776 regulator_set_value(vqmmc_dev, 3300000); 777 regulator_set_enable(vqmmc_dev, true); 778 } 779 #endif 780 781 ret = clk_get_by_index(dev, 0, &clk); 782 if (ret < 0) { 783 dev_err(dev, "failed to get host clock\n"); 784 return ret; 785 } 786 787 /* set to max rate */ 788 priv->mclk = clk_set_rate(&clk, ULONG_MAX); 789 if (IS_ERR_VALUE(priv->mclk)) { 790 dev_err(dev, "failed to set rate for host clock\n"); 791 clk_free(&clk); 792 return priv->mclk; 793 } 794 795 ret = clk_enable(&clk); 796 clk_free(&clk); 797 if (ret) { 798 dev_err(dev, "failed to enable host clock\n"); 799 return ret; 800 } 801 802 plat->cfg.name = dev->name; 803 plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; 804 805 switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width", 806 1)) { 807 case 8: 808 plat->cfg.host_caps |= MMC_MODE_8BIT; 809 break; 810 case 4: 811 plat->cfg.host_caps |= MMC_MODE_4BIT; 812 break; 813 case 1: 814 break; 815 default: 816 dev_err(dev, "Invalid \"bus-width\" value\n"); 817 return -EINVAL; 818 } 819 820 if (quirks) { 821 priv->caps = quirks; 822 } else { 823 priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) & 824 UNIPHIER_SD_VERSION_IP; 825 dev_dbg(dev, "version %x\n", priv->version); 826 if (priv->version >= 0x10) { 827 priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL; 828 priv->caps |= UNIPHIER_SD_CAP_DIV1024; 829 } 830 } 831 832 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable", 833 NULL)) 834 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE; 835 836 uniphier_sd_host_init(priv); 837 838 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; 839 plat->cfg.f_min = priv->mclk / 840 (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512); 841 plat->cfg.f_max = priv->mclk; 842 plat->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */ 843 844 upriv->mmc = &plat->mmc; 845 846 return 0; 847 } 848 849 static const struct udevice_id uniphier_sd_match[] = { 850 { .compatible = "renesas,sdhi-r8a7790", .data = 0 }, 851 { .compatible = "renesas,sdhi-r8a7791", .data = 0 }, 852 { .compatible = "renesas,sdhi-r8a7792", .data = 0 }, 853 { .compatible = "renesas,sdhi-r8a7793", .data = 0 }, 854 { .compatible = "renesas,sdhi-r8a7794", .data = 0 }, 855 { .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT }, 856 { .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT }, 857 { .compatible = "renesas,sdhi-r8a77965", .data = UNIPHIER_SD_CAP_64BIT }, 858 { .compatible = "renesas,sdhi-r8a77970", .data = UNIPHIER_SD_CAP_64BIT }, 859 { .compatible = "renesas,sdhi-r8a77995", .data = UNIPHIER_SD_CAP_64BIT }, 860 { .compatible = "socionext,uniphier-sdhc", .data = 0 }, 861 { /* sentinel */ } 862 }; 863 864 U_BOOT_DRIVER(uniphier_mmc) = { 865 .name = "uniphier-mmc", 866 .id = UCLASS_MMC, 867 .of_match = uniphier_sd_match, 868 .bind = uniphier_sd_bind, 869 .probe = uniphier_sd_probe, 870 .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv), 871 .platdata_auto_alloc_size = sizeof(struct uniphier_sd_plat), 872 .ops = &uniphier_sd_ops, 873 }; 874