1 /* 2 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <fdtdec.h> 10 #include <mapmem.h> 11 #include <mmc.h> 12 #include <dm/device.h> 13 #include <linux/compat.h> 14 #include <linux/io.h> 15 #include <asm/unaligned.h> 16 #include <asm/dma-mapping.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define UNIPHIER_SD_CMD 0x000 /* command */ 21 #define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */ 22 #define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */ 23 #define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */ 24 #define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */ 25 #define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */ 26 #define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */ 27 #define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */ 28 #define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */ 29 #define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */ 30 #define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */ 31 #define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */ 32 #define UNIPHIER_SD_ARG 0x008 /* command argument */ 33 #define UNIPHIER_SD_STOP 0x010 /* stop action control */ 34 #define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */ 35 #define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */ 36 #define UNIPHIER_SD_SECCNT 0x014 /* sector counter */ 37 #define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */ 38 #define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */ 39 #define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */ 40 #define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */ 41 #define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */ 42 #define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */ 43 #define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */ 44 #define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */ 45 #define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */ 46 #define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */ 47 #define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */ 48 #define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */ 49 #define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */ 50 #define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */ 51 #define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */ 52 #define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */ 53 #define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */ 54 #define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */ 55 #define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */ 56 #define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */ 57 #define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */ 58 #define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */ 59 #define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */ 60 #define UNIPHIER_SD_INFO1_MASK 0x040 61 #define UNIPHIER_SD_INFO2_MASK 0x044 62 #define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */ 63 #define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff 64 #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */ 65 #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */ 66 #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */ 67 #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */ 68 #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */ 69 #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */ 70 #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */ 71 #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */ 72 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */ 73 #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */ 74 #define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */ 75 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */ 76 #define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */ 77 #define UNIPHIER_SD_SIZE 0x04c /* block size */ 78 #define UNIPHIER_SD_OPTION 0x050 79 #define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13) 80 #define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13) 81 #define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13) 82 #define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13) 83 #define UNIPHIER_SD_BUF 0x060 /* read/write buffer */ 84 #define UNIPHIER_SD_EXTMODE 0x1b0 85 #define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */ 86 #define UNIPHIER_SD_SOFT_RST 0x1c0 87 #define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */ 88 #define UNIPHIER_SD_VERSION 0x1c4 /* version register */ 89 #define UNIPHIER_SD_VERSION_IP 0xff /* IP version */ 90 #define UNIPHIER_SD_HOST_MODE 0x1c8 91 #define UNIPHIER_SD_IF_MODE 0x1cc 92 #define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */ 93 #define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */ 94 #define UNIPHIER_SD_VOLT_MASK (3 << 0) 95 #define UNIPHIER_SD_VOLT_OFF (0 << 0) 96 #define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */ 97 #define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */ 98 #define UNIPHIER_SD_DMA_MODE 0x410 99 #define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */ 100 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */ 101 #define UNIPHIER_SD_DMA_CTL 0x414 102 #define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */ 103 #define UNIPHIER_SD_DMA_RST 0x418 104 #define UNIPHIER_SD_DMA_RST_RD BIT(9) 105 #define UNIPHIER_SD_DMA_RST_WR BIT(8) 106 #define UNIPHIER_SD_DMA_INFO1 0x420 107 #define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/ 108 #define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */ 109 #define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */ 110 #define UNIPHIER_SD_DMA_INFO1_MASK 0x424 111 #define UNIPHIER_SD_DMA_INFO2 0x428 112 #define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17) 113 #define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16) 114 #define UNIPHIER_SD_DMA_INFO2_MASK 0x42c 115 #define UNIPHIER_SD_DMA_ADDR_L 0x440 116 #define UNIPHIER_SD_DMA_ADDR_H 0x444 117 118 /* alignment required by the DMA engine of this controller */ 119 #define UNIPHIER_SD_DMA_MINALIGN 0x10 120 121 struct uniphier_sd_priv { 122 struct mmc_config cfg; 123 struct mmc *mmc; 124 struct udevice *dev; 125 void __iomem *regbase; 126 unsigned long mclk; 127 unsigned int version; 128 u32 caps; 129 #define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */ 130 #define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */ 131 #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */ 132 }; 133 134 static dma_addr_t __dma_map_single(void *ptr, size_t size, 135 enum dma_data_direction dir) 136 { 137 unsigned long addr = (unsigned long)ptr; 138 139 if (dir == DMA_FROM_DEVICE) 140 invalidate_dcache_range(addr, addr + size); 141 else 142 flush_dcache_range(addr, addr + size); 143 144 return addr; 145 } 146 147 static void __dma_unmap_single(dma_addr_t addr, size_t size, 148 enum dma_data_direction dir) 149 { 150 if (dir != DMA_TO_DEVICE) 151 invalidate_dcache_range(addr, addr + size); 152 } 153 154 static int uniphier_sd_check_error(struct uniphier_sd_priv *priv) 155 { 156 u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2); 157 158 if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) { 159 /* 160 * TIMEOUT must be returned for unsupported command. Do not 161 * display error log since this might be a part of sequence to 162 * distinguish between SD and MMC. 163 */ 164 return TIMEOUT; 165 } 166 167 if (info2 & UNIPHIER_SD_INFO2_ERR_TO) { 168 dev_err(priv->dev, "timeout error\n"); 169 return -ETIMEDOUT; 170 } 171 172 if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC | 173 UNIPHIER_SD_INFO2_ERR_IDX)) { 174 dev_err(priv->dev, "communication out of sync\n"); 175 return -EILSEQ; 176 } 177 178 if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR | 179 UNIPHIER_SD_INFO2_ERR_ILW)) { 180 dev_err(priv->dev, "illegal access\n"); 181 return -EIO; 182 } 183 184 return 0; 185 } 186 187 static int uniphier_sd_wait_for_irq(struct uniphier_sd_priv *priv, 188 unsigned int reg, u32 flag) 189 { 190 long wait = 1000000; 191 int ret; 192 193 while (!(readl(priv->regbase + reg) & flag)) { 194 if (wait-- < 0) { 195 dev_err(priv->dev, "timeout\n"); 196 return -ETIMEDOUT; 197 } 198 199 ret = uniphier_sd_check_error(priv); 200 if (ret) 201 return ret; 202 203 udelay(1); 204 } 205 206 return 0; 207 } 208 209 static int uniphier_sd_pio_read_one_block(struct mmc *mmc, u32 **pbuf, 210 uint blocksize) 211 { 212 struct uniphier_sd_priv *priv = mmc->priv; 213 int i, ret; 214 215 /* wait until the buffer is filled with data */ 216 ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO2, 217 UNIPHIER_SD_INFO2_BRE); 218 if (ret) 219 return ret; 220 221 /* 222 * Clear the status flag _before_ read the buffer out because 223 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered. 224 */ 225 writel(0, priv->regbase + UNIPHIER_SD_INFO2); 226 227 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { 228 for (i = 0; i < blocksize / 4; i++) 229 *(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF); 230 } else { 231 for (i = 0; i < blocksize / 4; i++) 232 put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF), 233 (*pbuf)++); 234 } 235 236 return 0; 237 } 238 239 static int uniphier_sd_pio_write_one_block(struct mmc *mmc, const u32 **pbuf, 240 uint blocksize) 241 { 242 struct uniphier_sd_priv *priv = mmc->priv; 243 int i, ret; 244 245 /* wait until the buffer becomes empty */ 246 ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO2, 247 UNIPHIER_SD_INFO2_BWE); 248 if (ret) 249 return ret; 250 251 writel(0, priv->regbase + UNIPHIER_SD_INFO2); 252 253 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) { 254 for (i = 0; i < blocksize / 4; i++) 255 writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF); 256 } else { 257 for (i = 0; i < blocksize / 4; i++) 258 writel(get_unaligned((*pbuf)++), 259 priv->regbase + UNIPHIER_SD_BUF); 260 } 261 262 return 0; 263 } 264 265 static int uniphier_sd_pio_xfer(struct mmc *mmc, struct mmc_data *data) 266 { 267 u32 *dest = (u32 *)data->dest; 268 const u32 *src = (const u32 *)data->src; 269 int i, ret; 270 271 for (i = 0; i < data->blocks; i++) { 272 if (data->flags & MMC_DATA_READ) 273 ret = uniphier_sd_pio_read_one_block(mmc, &dest, 274 data->blocksize); 275 else 276 ret = uniphier_sd_pio_write_one_block(mmc, &src, 277 data->blocksize); 278 if (ret) 279 return ret; 280 } 281 282 return 0; 283 } 284 285 static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv, 286 dma_addr_t dma_addr) 287 { 288 u32 tmp; 289 290 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1); 291 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2); 292 293 /* enable DMA */ 294 tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE); 295 tmp |= UNIPHIER_SD_EXTMODE_DMA_EN; 296 writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE); 297 298 writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L); 299 300 /* suppress the warning "right shift count >= width of type" */ 301 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); 302 303 writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H); 304 305 writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL); 306 } 307 308 static int uniphier_sd_dma_wait_for_irq(struct uniphier_sd_priv *priv, u32 flag, 309 unsigned int blocks) 310 { 311 long wait = 1000000 + 10 * blocks; 312 313 while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) { 314 if (wait-- < 0) { 315 dev_err(priv->dev, "timeout during DMA\n"); 316 return -ETIMEDOUT; 317 } 318 319 udelay(10); 320 } 321 322 if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) { 323 dev_err(priv->dev, "error during DMA\n"); 324 return -EIO; 325 } 326 327 return 0; 328 } 329 330 static int uniphier_sd_dma_xfer(struct mmc *mmc, struct mmc_data *data) 331 { 332 struct uniphier_sd_priv *priv = mmc->priv; 333 size_t len = data->blocks * data->blocksize; 334 void *buf; 335 enum dma_data_direction dir; 336 dma_addr_t dma_addr; 337 u32 poll_flag, tmp; 338 int ret; 339 340 tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE); 341 342 if (data->flags & MMC_DATA_READ) { 343 buf = data->dest; 344 dir = DMA_FROM_DEVICE; 345 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2; 346 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD; 347 } else { 348 buf = (void *)data->src; 349 dir = DMA_TO_DEVICE; 350 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR; 351 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD; 352 } 353 354 writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE); 355 356 dma_addr = __dma_map_single(buf, len, dir); 357 358 uniphier_sd_dma_start(priv, dma_addr); 359 360 ret = uniphier_sd_dma_wait_for_irq(priv, poll_flag, data->blocks); 361 362 __dma_unmap_single(dma_addr, len, dir); 363 364 return ret; 365 } 366 367 /* check if the address is DMA'able */ 368 static bool uniphier_sd_addr_is_dmaable(unsigned long addr) 369 { 370 if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN)) 371 return false; 372 373 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ 374 defined(CONFIG_SPL_BUILD) 375 /* 376 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways 377 * of L2, which is unreachable from the DMA engine. 378 */ 379 if (addr < CONFIG_SPL_STACK) 380 return false; 381 #endif 382 383 return true; 384 } 385 386 static int uniphier_sd_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 387 struct mmc_data *data) 388 { 389 struct uniphier_sd_priv *priv = mmc->priv; 390 int ret; 391 u32 tmp; 392 393 if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) { 394 dev_err(priv->dev, "command busy\n"); 395 return -EBUSY; 396 } 397 398 /* clear all status flags */ 399 writel(0, priv->regbase + UNIPHIER_SD_INFO1); 400 writel(0, priv->regbase + UNIPHIER_SD_INFO2); 401 402 /* disable DMA once */ 403 tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE); 404 tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN; 405 writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE); 406 407 writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG); 408 409 tmp = cmd->cmdidx; 410 411 if (data) { 412 writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE); 413 writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT); 414 415 /* Do not send CMD12 automatically */ 416 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA; 417 418 if (data->blocks > 1) 419 tmp |= UNIPHIER_SD_CMD_MULTI; 420 421 if (data->flags & MMC_DATA_READ) 422 tmp |= UNIPHIER_SD_CMD_RD; 423 } 424 425 /* 426 * Do not use the response type auto-detection on this hardware. 427 * CMD8, for example, has different response types on SD and eMMC, 428 * while this controller always assumes the response type for SD. 429 * Set the response type manually. 430 */ 431 switch (cmd->resp_type) { 432 case MMC_RSP_NONE: 433 tmp |= UNIPHIER_SD_CMD_RSP_NONE; 434 break; 435 case MMC_RSP_R1: 436 tmp |= UNIPHIER_SD_CMD_RSP_R1; 437 break; 438 case MMC_RSP_R1b: 439 tmp |= UNIPHIER_SD_CMD_RSP_R1B; 440 break; 441 case MMC_RSP_R2: 442 tmp |= UNIPHIER_SD_CMD_RSP_R2; 443 break; 444 case MMC_RSP_R3: 445 tmp |= UNIPHIER_SD_CMD_RSP_R3; 446 break; 447 default: 448 dev_err(priv->dev, "unknown response type\n"); 449 return -EINVAL; 450 } 451 452 dev_dbg(priv->dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", 453 cmd->cmdidx, tmp, cmd->cmdarg); 454 writel(tmp, priv->regbase + UNIPHIER_SD_CMD); 455 456 ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO1, 457 UNIPHIER_SD_INFO1_RSP); 458 if (ret) 459 return ret; 460 461 if (cmd->resp_type & MMC_RSP_136) { 462 u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76); 463 u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54); 464 u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32); 465 u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10); 466 467 cmd->response[0] = (rsp_127_104 & 0xffffff) << 8 | 468 (rsp_103_72 & 0xff); 469 cmd->response[1] = (rsp_103_72 & 0xffffff) << 8 | 470 (rsp_71_40 & 0xff); 471 cmd->response[2] = (rsp_71_40 & 0xffffff) << 8 | 472 (rsp_39_8 & 0xff); 473 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; 474 } else { 475 /* bit 39-8 */ 476 cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10); 477 } 478 479 if (data) { 480 /* use DMA if the HW supports it and the buffer is aligned */ 481 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL && 482 uniphier_sd_addr_is_dmaable((long)data->src)) 483 ret = uniphier_sd_dma_xfer(mmc, data); 484 else 485 ret = uniphier_sd_pio_xfer(mmc, data); 486 487 ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO1, 488 UNIPHIER_SD_INFO1_CMP); 489 if (ret) 490 return ret; 491 } 492 493 return ret; 494 } 495 496 static void uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv, 497 struct mmc *mmc) 498 { 499 u32 val, tmp; 500 501 switch (mmc->bus_width) { 502 case 1: 503 val = UNIPHIER_SD_OPTION_WIDTH_1; 504 break; 505 case 4: 506 val = UNIPHIER_SD_OPTION_WIDTH_4; 507 break; 508 case 8: 509 val = UNIPHIER_SD_OPTION_WIDTH_8; 510 break; 511 default: 512 BUG(); 513 break; 514 } 515 516 tmp = readl(priv->regbase + UNIPHIER_SD_OPTION); 517 tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK; 518 tmp |= val; 519 writel(tmp, priv->regbase + UNIPHIER_SD_OPTION); 520 } 521 522 static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv, 523 struct mmc *mmc) 524 { 525 u32 tmp; 526 527 tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE); 528 if (mmc->ddr_mode) 529 tmp |= UNIPHIER_SD_IF_MODE_DDR; 530 else 531 tmp &= ~UNIPHIER_SD_IF_MODE_DDR; 532 writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE); 533 } 534 535 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv, 536 struct mmc *mmc) 537 { 538 unsigned int divisor; 539 u32 val, tmp; 540 541 if (!mmc->clock) 542 return; 543 544 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); 545 546 if (divisor <= 1) 547 val = UNIPHIER_SD_CLKCTL_DIV1; 548 else if (divisor <= 2) 549 val = UNIPHIER_SD_CLKCTL_DIV2; 550 else if (divisor <= 4) 551 val = UNIPHIER_SD_CLKCTL_DIV4; 552 else if (divisor <= 8) 553 val = UNIPHIER_SD_CLKCTL_DIV8; 554 else if (divisor <= 16) 555 val = UNIPHIER_SD_CLKCTL_DIV16; 556 else if (divisor <= 32) 557 val = UNIPHIER_SD_CLKCTL_DIV32; 558 else if (divisor <= 64) 559 val = UNIPHIER_SD_CLKCTL_DIV64; 560 else if (divisor <= 128) 561 val = UNIPHIER_SD_CLKCTL_DIV128; 562 else if (divisor <= 256) 563 val = UNIPHIER_SD_CLKCTL_DIV256; 564 else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024)) 565 val = UNIPHIER_SD_CLKCTL_DIV512; 566 else 567 val = UNIPHIER_SD_CLKCTL_DIV1024; 568 569 tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL); 570 571 /* stop the clock before changing its rate to avoid a glitch signal */ 572 tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN; 573 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); 574 575 tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK; 576 tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN; 577 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); 578 579 tmp |= UNIPHIER_SD_CLKCTL_SCLKEN; 580 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL); 581 } 582 583 static void uniphier_sd_set_ios(struct mmc *mmc) 584 { 585 struct uniphier_sd_priv *priv = mmc->priv; 586 587 dev_dbg(priv->dev, "clock %uHz, DDRmode %d, width %u\n", 588 mmc->clock, mmc->ddr_mode, mmc->bus_width); 589 590 uniphier_sd_set_bus_width(priv, mmc); 591 uniphier_sd_set_ddr_mode(priv, mmc); 592 uniphier_sd_set_clk_rate(priv, mmc); 593 594 udelay(1000); 595 } 596 597 static int uniphier_sd_init(struct mmc *mmc) 598 { 599 struct uniphier_sd_priv *priv = mmc->priv; 600 u32 tmp; 601 602 /* soft reset of the host */ 603 tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST); 604 tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX; 605 writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST); 606 tmp |= UNIPHIER_SD_SOFT_RST_RSTX; 607 writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST); 608 609 /* FIXME: implement eMMC hw_reset */ 610 611 writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP); 612 613 /* 614 * Connected to 32bit AXI. 615 * This register dropped backward compatibility at version 0x10. 616 * Write an appropriate value depending on the IP version. 617 */ 618 writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000, 619 priv->regbase + UNIPHIER_SD_HOST_MODE); 620 621 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) { 622 tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE); 623 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC; 624 writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE); 625 } 626 627 return 0; 628 } 629 630 static int uniphier_sd_getcd(struct mmc *mmc) 631 { 632 struct uniphier_sd_priv *priv = mmc->priv; 633 634 if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE) 635 return 1; 636 637 return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) & 638 UNIPHIER_SD_INFO1_CD); 639 } 640 641 static const struct mmc_ops uniphier_sd_ops = { 642 .send_cmd = uniphier_sd_send_cmd, 643 .set_ios = uniphier_sd_set_ios, 644 .init = uniphier_sd_init, 645 .getcd = uniphier_sd_getcd, 646 }; 647 648 int uniphier_sd_probe(struct udevice *dev) 649 { 650 struct uniphier_sd_priv *priv = dev_get_priv(dev); 651 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 652 fdt_addr_t base; 653 fdt_size_t size; 654 struct udevice *clk_dev; 655 int clk_id; 656 int ret; 657 658 priv->dev = dev; 659 660 base = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); 661 priv->regbase = map_sysmem(base, size); 662 if (!priv->regbase) 663 return -ENOMEM; 664 665 clk_id = clk_get_by_index(dev, 0, &clk_dev); 666 if (clk_id < 0) { 667 dev_err(dev, "failed to get host clock\n"); 668 return clk_id; 669 } 670 671 /* set to max rate */ 672 priv->mclk = clk_set_periph_rate(clk_dev, clk_id, ULONG_MAX); 673 if (IS_ERR_VALUE(priv->mclk)) { 674 dev_err(dev, "failed to set rate for host clock\n"); 675 return priv->mclk; 676 } 677 678 ret = clk_enable(clk_dev, clk_id); 679 if (ret) { 680 dev_err(dev, "failed to enable host clock\n"); 681 return ret; 682 } 683 684 priv->cfg.name = dev->name; 685 priv->cfg.ops = &uniphier_sd_ops; 686 priv->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; 687 688 switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) { 689 case 8: 690 priv->cfg.host_caps |= MMC_MODE_8BIT; 691 break; 692 case 4: 693 priv->cfg.host_caps |= MMC_MODE_4BIT; 694 break; 695 case 1: 696 break; 697 default: 698 dev_err(dev, "Invalid \"bus-width\" value\n"); 699 return -EINVAL; 700 } 701 702 if (fdt_get_property(gd->fdt_blob, dev->of_offset, "non-removable", 703 NULL)) 704 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE; 705 706 priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) & 707 UNIPHIER_SD_VERSION_IP; 708 dev_dbg(dev, "version %x\n", priv->version); 709 if (priv->version >= 0x10) { 710 priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL; 711 priv->caps |= UNIPHIER_SD_CAP_DIV1024; 712 } 713 714 priv->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; 715 priv->cfg.f_min = priv->mclk / 716 (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512); 717 priv->cfg.f_max = priv->mclk; 718 priv->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */ 719 720 priv->mmc = mmc_create(&priv->cfg, priv); 721 if (!priv->mmc) 722 return -EIO; 723 724 upriv->mmc = priv->mmc; 725 726 return 0; 727 } 728 729 int uniphier_sd_remove(struct udevice *dev) 730 { 731 struct uniphier_sd_priv *priv = dev_get_priv(dev); 732 733 unmap_sysmem(priv->regbase); 734 mmc_destroy(priv->mmc); 735 736 return 0; 737 } 738 739 static const struct udevice_id uniphier_sd_match[] = { 740 { .compatible = "socionext,uniphier-sdhc" }, 741 { /* sentinel */ } 742 }; 743 744 U_BOOT_DRIVER(uniphier_mmc) = { 745 .name = "uniphier-mmc", 746 .id = UCLASS_MMC, 747 .of_match = uniphier_sd_match, 748 .probe = uniphier_sd_probe, 749 .remove = uniphier_sd_remove, 750 .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv), 751 }; 752