1 /* 2 * Copyright (C) 2016 Socionext Inc. 3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <fdtdec.h> 11 #include <mmc.h> 12 #include <dm.h> 13 #include <dm/pinctrl.h> 14 #include <linux/compat.h> 15 #include <linux/dma-direction.h> 16 #include <linux/io.h> 17 #include <linux/sizes.h> 18 #include <power/regulator.h> 19 #include <asm/unaligned.h> 20 21 #include "tmio-common.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg) 26 { 27 return readq(priv->regbase + (reg << 1)); 28 } 29 30 static void tmio_sd_writeq(struct tmio_sd_priv *priv, 31 u64 val, unsigned int reg) 32 { 33 writeq(val, priv->regbase + (reg << 1)); 34 } 35 36 static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg) 37 { 38 return readw(priv->regbase + (reg >> 1)); 39 } 40 41 static void tmio_sd_writew(struct tmio_sd_priv *priv, 42 u16 val, unsigned int reg) 43 { 44 writew(val, priv->regbase + (reg >> 1)); 45 } 46 47 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg) 48 { 49 u32 val; 50 51 if (priv->caps & TMIO_SD_CAP_64BIT) 52 return readl(priv->regbase + (reg << 1)); 53 else if (priv->caps & TMIO_SD_CAP_16BIT) { 54 val = readw(priv->regbase + (reg >> 1)) & 0xffff; 55 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) || 56 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) { 57 val |= readw(priv->regbase + (reg >> 1) + 2) << 16; 58 } 59 return val; 60 } else 61 return readl(priv->regbase + reg); 62 } 63 64 void tmio_sd_writel(struct tmio_sd_priv *priv, 65 u32 val, unsigned int reg) 66 { 67 if (priv->caps & TMIO_SD_CAP_64BIT) 68 writel(val, priv->regbase + (reg << 1)); 69 else if (priv->caps & TMIO_SD_CAP_16BIT) { 70 writew(val & 0xffff, priv->regbase + (reg >> 1)); 71 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK || 72 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK || 73 reg == TMIO_SD_ARG) 74 writew(val >> 16, priv->regbase + (reg >> 1) + 2); 75 } else 76 writel(val, priv->regbase + reg); 77 } 78 79 static dma_addr_t __dma_map_single(void *ptr, size_t size, 80 enum dma_data_direction dir) 81 { 82 unsigned long addr = (unsigned long)ptr; 83 84 if (dir == DMA_FROM_DEVICE) 85 invalidate_dcache_range(addr, addr + size); 86 else 87 flush_dcache_range(addr, addr + size); 88 89 return addr; 90 } 91 92 static void __dma_unmap_single(dma_addr_t addr, size_t size, 93 enum dma_data_direction dir) 94 { 95 if (dir != DMA_TO_DEVICE) 96 invalidate_dcache_range(addr, addr + size); 97 } 98 99 static int tmio_sd_check_error(struct udevice *dev) 100 { 101 struct tmio_sd_priv *priv = dev_get_priv(dev); 102 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2); 103 104 if (info2 & TMIO_SD_INFO2_ERR_RTO) { 105 /* 106 * TIMEOUT must be returned for unsupported command. Do not 107 * display error log since this might be a part of sequence to 108 * distinguish between SD and MMC. 109 */ 110 return -ETIMEDOUT; 111 } 112 113 if (info2 & TMIO_SD_INFO2_ERR_TO) { 114 dev_err(dev, "timeout error\n"); 115 return -ETIMEDOUT; 116 } 117 118 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC | 119 TMIO_SD_INFO2_ERR_IDX)) { 120 dev_err(dev, "communication out of sync\n"); 121 return -EILSEQ; 122 } 123 124 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR | 125 TMIO_SD_INFO2_ERR_ILW)) { 126 dev_err(dev, "illegal access\n"); 127 return -EIO; 128 } 129 130 return 0; 131 } 132 133 static int tmio_sd_wait_for_irq(struct udevice *dev, unsigned int reg, 134 u32 flag) 135 { 136 struct tmio_sd_priv *priv = dev_get_priv(dev); 137 long wait = 1000000; 138 int ret; 139 140 while (!(tmio_sd_readl(priv, reg) & flag)) { 141 if (wait-- < 0) { 142 dev_err(dev, "timeout\n"); 143 return -ETIMEDOUT; 144 } 145 146 ret = tmio_sd_check_error(dev); 147 if (ret) 148 return ret; 149 150 udelay(1); 151 } 152 153 return 0; 154 } 155 156 #define tmio_pio_read_fifo(__width, __suffix) \ 157 static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \ 158 char *pbuf, uint blksz) \ 159 { \ 160 u##__width *buf = (u##__width *)pbuf; \ 161 int i; \ 162 \ 163 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \ 164 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 165 *buf++ = tmio_sd_read##__suffix(priv, \ 166 TMIO_SD_BUF); \ 167 } \ 168 } else { \ 169 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 170 u##__width data; \ 171 data = tmio_sd_read##__suffix(priv, \ 172 TMIO_SD_BUF); \ 173 put_unaligned(data, buf++); \ 174 } \ 175 } \ 176 } 177 178 tmio_pio_read_fifo(64, q) 179 tmio_pio_read_fifo(32, l) 180 tmio_pio_read_fifo(16, w) 181 182 static int tmio_sd_pio_read_one_block(struct udevice *dev, char *pbuf, 183 uint blocksize) 184 { 185 struct tmio_sd_priv *priv = dev_get_priv(dev); 186 int ret; 187 188 /* wait until the buffer is filled with data */ 189 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, 190 TMIO_SD_INFO2_BRE); 191 if (ret) 192 return ret; 193 194 /* 195 * Clear the status flag _before_ read the buffer out because 196 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered. 197 */ 198 tmio_sd_writel(priv, 0, TMIO_SD_INFO2); 199 200 if (priv->caps & TMIO_SD_CAP_64BIT) 201 tmio_pio_read_fifo_64(priv, pbuf, blocksize); 202 else if (priv->caps & TMIO_SD_CAP_16BIT) 203 tmio_pio_read_fifo_16(priv, pbuf, blocksize); 204 else 205 tmio_pio_read_fifo_32(priv, pbuf, blocksize); 206 207 return 0; 208 } 209 210 #define tmio_pio_write_fifo(__width, __suffix) \ 211 static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \ 212 const char *pbuf, uint blksz)\ 213 { \ 214 const u##__width *buf = (const u##__width *)pbuf; \ 215 int i; \ 216 \ 217 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \ 218 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 219 tmio_sd_write##__suffix(priv, *buf++, \ 220 TMIO_SD_BUF); \ 221 } \ 222 } else { \ 223 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 224 u##__width data = get_unaligned(buf++); \ 225 tmio_sd_write##__suffix(priv, data, \ 226 TMIO_SD_BUF); \ 227 } \ 228 } \ 229 } 230 231 tmio_pio_write_fifo(64, q) 232 tmio_pio_write_fifo(32, l) 233 tmio_pio_write_fifo(16, w) 234 235 static int tmio_sd_pio_write_one_block(struct udevice *dev, 236 const char *pbuf, uint blocksize) 237 { 238 struct tmio_sd_priv *priv = dev_get_priv(dev); 239 int ret; 240 241 /* wait until the buffer becomes empty */ 242 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, 243 TMIO_SD_INFO2_BWE); 244 if (ret) 245 return ret; 246 247 tmio_sd_writel(priv, 0, TMIO_SD_INFO2); 248 249 if (priv->caps & TMIO_SD_CAP_64BIT) 250 tmio_pio_write_fifo_64(priv, pbuf, blocksize); 251 else if (priv->caps & TMIO_SD_CAP_16BIT) 252 tmio_pio_write_fifo_16(priv, pbuf, blocksize); 253 else 254 tmio_pio_write_fifo_32(priv, pbuf, blocksize); 255 256 return 0; 257 } 258 259 static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_data *data) 260 { 261 const char *src = data->src; 262 char *dest = data->dest; 263 int i, ret; 264 265 for (i = 0; i < data->blocks; i++) { 266 if (data->flags & MMC_DATA_READ) 267 ret = tmio_sd_pio_read_one_block(dev, dest, 268 data->blocksize); 269 else 270 ret = tmio_sd_pio_write_one_block(dev, src, 271 data->blocksize); 272 if (ret) 273 return ret; 274 275 if (data->flags & MMC_DATA_READ) 276 dest += data->blocksize; 277 else 278 src += data->blocksize; 279 } 280 281 return 0; 282 } 283 284 static void tmio_sd_dma_start(struct tmio_sd_priv *priv, 285 dma_addr_t dma_addr) 286 { 287 u32 tmp; 288 289 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1); 290 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2); 291 292 /* enable DMA */ 293 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE); 294 tmp |= TMIO_SD_EXTMODE_DMA_EN; 295 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE); 296 297 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L); 298 299 /* suppress the warning "right shift count >= width of type" */ 300 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); 301 302 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H); 303 304 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL); 305 } 306 307 static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, 308 unsigned int blocks) 309 { 310 struct tmio_sd_priv *priv = dev_get_priv(dev); 311 long wait = 1000000 + 10 * blocks; 312 313 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) { 314 if (wait-- < 0) { 315 dev_err(dev, "timeout during DMA\n"); 316 return -ETIMEDOUT; 317 } 318 319 udelay(10); 320 } 321 322 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) { 323 dev_err(dev, "error during DMA\n"); 324 return -EIO; 325 } 326 327 return 0; 328 } 329 330 static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) 331 { 332 struct tmio_sd_priv *priv = dev_get_priv(dev); 333 size_t len = data->blocks * data->blocksize; 334 void *buf; 335 enum dma_data_direction dir; 336 dma_addr_t dma_addr; 337 u32 poll_flag, tmp; 338 int ret; 339 340 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE); 341 342 if (data->flags & MMC_DATA_READ) { 343 buf = data->dest; 344 dir = DMA_FROM_DEVICE; 345 /* 346 * The DMA READ completion flag position differs on Socionext 347 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using 348 * bit 17 is a hardware bug and forbidden. It is bit 17 on 349 * Renesas SoCs and bit 20 does not work on them. 350 */ 351 poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ? 352 TMIO_SD_DMA_INFO1_END_RD : 353 TMIO_SD_DMA_INFO1_END_RD2; 354 tmp |= TMIO_SD_DMA_MODE_DIR_RD; 355 } else { 356 buf = (void *)data->src; 357 dir = DMA_TO_DEVICE; 358 poll_flag = TMIO_SD_DMA_INFO1_END_WR; 359 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD; 360 } 361 362 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE); 363 364 dma_addr = __dma_map_single(buf, len, dir); 365 366 tmio_sd_dma_start(priv, dma_addr); 367 368 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); 369 370 __dma_unmap_single(dma_addr, len, dir); 371 372 return ret; 373 } 374 375 /* check if the address is DMA'able */ 376 static bool tmio_sd_addr_is_dmaable(unsigned long addr) 377 { 378 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN)) 379 return false; 380 381 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ 382 defined(CONFIG_SPL_BUILD) 383 /* 384 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways 385 * of L2, which is unreachable from the DMA engine. 386 */ 387 if (addr < CONFIG_SPL_STACK) 388 return false; 389 #endif 390 391 return true; 392 } 393 394 int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 395 struct mmc_data *data) 396 { 397 struct tmio_sd_priv *priv = dev_get_priv(dev); 398 int ret; 399 u32 tmp; 400 401 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) { 402 dev_err(dev, "command busy\n"); 403 return -EBUSY; 404 } 405 406 /* clear all status flags */ 407 tmio_sd_writel(priv, 0, TMIO_SD_INFO1); 408 tmio_sd_writel(priv, 0, TMIO_SD_INFO2); 409 410 /* disable DMA once */ 411 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE); 412 tmp &= ~TMIO_SD_EXTMODE_DMA_EN; 413 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE); 414 415 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG); 416 417 tmp = cmd->cmdidx; 418 419 if (data) { 420 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE); 421 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT); 422 423 /* Do not send CMD12 automatically */ 424 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA; 425 426 if (data->blocks > 1) 427 tmp |= TMIO_SD_CMD_MULTI; 428 429 if (data->flags & MMC_DATA_READ) 430 tmp |= TMIO_SD_CMD_RD; 431 } 432 433 /* 434 * Do not use the response type auto-detection on this hardware. 435 * CMD8, for example, has different response types on SD and eMMC, 436 * while this controller always assumes the response type for SD. 437 * Set the response type manually. 438 */ 439 switch (cmd->resp_type) { 440 case MMC_RSP_NONE: 441 tmp |= TMIO_SD_CMD_RSP_NONE; 442 break; 443 case MMC_RSP_R1: 444 tmp |= TMIO_SD_CMD_RSP_R1; 445 break; 446 case MMC_RSP_R1b: 447 tmp |= TMIO_SD_CMD_RSP_R1B; 448 break; 449 case MMC_RSP_R2: 450 tmp |= TMIO_SD_CMD_RSP_R2; 451 break; 452 case MMC_RSP_R3: 453 tmp |= TMIO_SD_CMD_RSP_R3; 454 break; 455 default: 456 dev_err(dev, "unknown response type\n"); 457 return -EINVAL; 458 } 459 460 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", 461 cmd->cmdidx, tmp, cmd->cmdarg); 462 tmio_sd_writel(priv, tmp, TMIO_SD_CMD); 463 464 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1, 465 TMIO_SD_INFO1_RSP); 466 if (ret) 467 return ret; 468 469 if (cmd->resp_type & MMC_RSP_136) { 470 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76); 471 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54); 472 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32); 473 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10); 474 475 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) | 476 ((rsp_103_72 & 0xff000000) >> 24); 477 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) | 478 ((rsp_71_40 & 0xff000000) >> 24); 479 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) | 480 ((rsp_39_8 & 0xff000000) >> 24); 481 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; 482 } else { 483 /* bit 39-8 */ 484 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10); 485 } 486 487 if (data) { 488 /* use DMA if the HW supports it and the buffer is aligned */ 489 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL && 490 tmio_sd_addr_is_dmaable((long)data->src)) 491 ret = tmio_sd_dma_xfer(dev, data); 492 else 493 ret = tmio_sd_pio_xfer(dev, data); 494 495 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1, 496 TMIO_SD_INFO1_CMP); 497 if (ret) 498 return ret; 499 } 500 501 tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, TMIO_SD_INFO2_SCLKDIVEN); 502 503 return ret; 504 } 505 506 static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv, 507 struct mmc *mmc) 508 { 509 u32 val, tmp; 510 511 switch (mmc->bus_width) { 512 case 0: 513 case 1: 514 val = TMIO_SD_OPTION_WIDTH_1; 515 break; 516 case 4: 517 val = TMIO_SD_OPTION_WIDTH_4; 518 break; 519 case 8: 520 val = TMIO_SD_OPTION_WIDTH_8; 521 break; 522 default: 523 return -EINVAL; 524 } 525 526 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION); 527 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK; 528 tmp |= val; 529 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION); 530 531 return 0; 532 } 533 534 static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv, 535 struct mmc *mmc) 536 { 537 u32 tmp; 538 539 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE); 540 if (mmc->ddr_mode) 541 tmp |= TMIO_SD_IF_MODE_DDR; 542 else 543 tmp &= ~TMIO_SD_IF_MODE_DDR; 544 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE); 545 } 546 547 static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, 548 struct mmc *mmc) 549 { 550 unsigned int divisor; 551 u32 val, tmp; 552 553 if (!mmc->clock) 554 return; 555 556 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); 557 558 if (divisor <= 1) 559 val = (priv->caps & TMIO_SD_CAP_RCAR) ? 560 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; 561 else if (divisor <= 2) 562 val = TMIO_SD_CLKCTL_DIV2; 563 else if (divisor <= 4) 564 val = TMIO_SD_CLKCTL_DIV4; 565 else if (divisor <= 8) 566 val = TMIO_SD_CLKCTL_DIV8; 567 else if (divisor <= 16) 568 val = TMIO_SD_CLKCTL_DIV16; 569 else if (divisor <= 32) 570 val = TMIO_SD_CLKCTL_DIV32; 571 else if (divisor <= 64) 572 val = TMIO_SD_CLKCTL_DIV64; 573 else if (divisor <= 128) 574 val = TMIO_SD_CLKCTL_DIV128; 575 else if (divisor <= 256) 576 val = TMIO_SD_CLKCTL_DIV256; 577 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024)) 578 val = TMIO_SD_CLKCTL_DIV512; 579 else 580 val = TMIO_SD_CLKCTL_DIV1024; 581 582 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); 583 if (tmp & TMIO_SD_CLKCTL_SCLKEN && 584 (tmp & TMIO_SD_CLKCTL_DIV_MASK) == val) 585 return; 586 587 /* stop the clock before changing its rate to avoid a glitch signal */ 588 tmp &= ~TMIO_SD_CLKCTL_SCLKEN; 589 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); 590 591 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK; 592 tmp |= val | TMIO_SD_CLKCTL_OFFEN; 593 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); 594 595 tmp |= TMIO_SD_CLKCTL_SCLKEN; 596 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); 597 598 udelay(1000); 599 } 600 601 static void tmio_sd_set_pins(struct udevice *dev) 602 { 603 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev); 604 605 #ifdef CONFIG_DM_REGULATOR 606 struct tmio_sd_priv *priv = dev_get_priv(dev); 607 608 if (priv->vqmmc_dev) { 609 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 610 regulator_set_value(priv->vqmmc_dev, 1800000); 611 else 612 regulator_set_value(priv->vqmmc_dev, 3300000); 613 regulator_set_enable(priv->vqmmc_dev, true); 614 } 615 #endif 616 617 #ifdef CONFIG_PINCTRL 618 switch (mmc->selected_mode) { 619 case MMC_LEGACY: 620 case SD_LEGACY: 621 case MMC_HS: 622 case SD_HS: 623 case MMC_HS_52: 624 case MMC_DDR_52: 625 pinctrl_select_state(dev, "default"); 626 break; 627 case UHS_SDR12: 628 case UHS_SDR25: 629 case UHS_SDR50: 630 case UHS_DDR50: 631 case UHS_SDR104: 632 case MMC_HS_200: 633 pinctrl_select_state(dev, "state_uhs"); 634 break; 635 default: 636 break; 637 } 638 #endif 639 } 640 641 int tmio_sd_set_ios(struct udevice *dev) 642 { 643 struct tmio_sd_priv *priv = dev_get_priv(dev); 644 struct mmc *mmc = mmc_get_mmc_dev(dev); 645 int ret; 646 647 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n", 648 mmc->clock, mmc->ddr_mode, mmc->bus_width); 649 650 ret = tmio_sd_set_bus_width(priv, mmc); 651 if (ret) 652 return ret; 653 tmio_sd_set_ddr_mode(priv, mmc); 654 tmio_sd_set_clk_rate(priv, mmc); 655 tmio_sd_set_pins(dev); 656 657 return 0; 658 } 659 660 int tmio_sd_get_cd(struct udevice *dev) 661 { 662 struct tmio_sd_priv *priv = dev_get_priv(dev); 663 664 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE) 665 return 1; 666 667 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) & 668 TMIO_SD_INFO1_CD); 669 } 670 671 static void tmio_sd_host_init(struct tmio_sd_priv *priv) 672 { 673 u32 tmp; 674 675 /* soft reset of the host */ 676 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST); 677 tmp &= ~TMIO_SD_SOFT_RST_RSTX; 678 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST); 679 tmp |= TMIO_SD_SOFT_RST_RSTX; 680 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST); 681 682 /* FIXME: implement eMMC hw_reset */ 683 684 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP); 685 686 /* 687 * Connected to 32bit AXI. 688 * This register dropped backward compatibility at version 0x10. 689 * Write an appropriate value depending on the IP version. 690 */ 691 if (priv->version >= 0x10) 692 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE); 693 else 694 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE); 695 696 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) { 697 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE); 698 tmp |= TMIO_SD_DMA_MODE_ADDR_INC; 699 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE); 700 } 701 } 702 703 int tmio_sd_bind(struct udevice *dev) 704 { 705 struct tmio_sd_plat *plat = dev_get_platdata(dev); 706 707 return mmc_bind(dev, &plat->mmc, &plat->cfg); 708 } 709 710 int tmio_sd_probe(struct udevice *dev, u32 quirks) 711 { 712 struct tmio_sd_plat *plat = dev_get_platdata(dev); 713 struct tmio_sd_priv *priv = dev_get_priv(dev); 714 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 715 fdt_addr_t base; 716 int ret; 717 718 base = devfdt_get_addr(dev); 719 if (base == FDT_ADDR_T_NONE) 720 return -EINVAL; 721 722 priv->regbase = devm_ioremap(dev, base, SZ_2K); 723 if (!priv->regbase) 724 return -ENOMEM; 725 726 #ifdef CONFIG_DM_REGULATOR 727 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev); 728 #endif 729 730 ret = mmc_of_parse(dev, &plat->cfg); 731 if (ret < 0) { 732 dev_err(dev, "failed to parse host caps\n"); 733 return ret; 734 } 735 736 plat->cfg.name = dev->name; 737 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 738 739 if (quirks) 740 priv->caps = quirks; 741 742 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) & 743 TMIO_SD_VERSION_IP; 744 dev_dbg(dev, "version %x\n", priv->version); 745 if (priv->version >= 0x10) { 746 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL; 747 priv->caps |= TMIO_SD_CAP_DIV1024; 748 } 749 750 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable", 751 NULL)) 752 priv->caps |= TMIO_SD_CAP_NONREMOVABLE; 753 754 tmio_sd_host_init(priv); 755 756 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; 757 plat->cfg.f_min = priv->mclk / 758 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512); 759 plat->cfg.f_max = priv->mclk; 760 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ 761 762 upriv->mmc = &plat->mmc; 763 764 return 0; 765 } 766