1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <fdtdec.h> 10 #include <mmc.h> 11 #include <dm.h> 12 #include <dm/pinctrl.h> 13 #include <linux/compat.h> 14 #include <linux/dma-direction.h> 15 #include <linux/io.h> 16 #include <linux/sizes.h> 17 #include <power/regulator.h> 18 #include <asm/unaligned.h> 19 20 #include "tmio-common.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg) 25 { 26 return readq(priv->regbase + (reg << 1)); 27 } 28 29 static void tmio_sd_writeq(struct tmio_sd_priv *priv, 30 u64 val, unsigned int reg) 31 { 32 writeq(val, priv->regbase + (reg << 1)); 33 } 34 35 static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg) 36 { 37 return readw(priv->regbase + (reg >> 1)); 38 } 39 40 static void tmio_sd_writew(struct tmio_sd_priv *priv, 41 u16 val, unsigned int reg) 42 { 43 writew(val, priv->regbase + (reg >> 1)); 44 } 45 46 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg) 47 { 48 u32 val; 49 50 if (priv->caps & TMIO_SD_CAP_64BIT) 51 return readl(priv->regbase + (reg << 1)); 52 else if (priv->caps & TMIO_SD_CAP_16BIT) { 53 val = readw(priv->regbase + (reg >> 1)) & 0xffff; 54 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) || 55 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) { 56 val |= readw(priv->regbase + (reg >> 1) + 2) << 16; 57 } 58 return val; 59 } else 60 return readl(priv->regbase + reg); 61 } 62 63 void tmio_sd_writel(struct tmio_sd_priv *priv, 64 u32 val, unsigned int reg) 65 { 66 if (priv->caps & TMIO_SD_CAP_64BIT) 67 writel(val, priv->regbase + (reg << 1)); 68 else if (priv->caps & TMIO_SD_CAP_16BIT) { 69 writew(val & 0xffff, priv->regbase + (reg >> 1)); 70 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK || 71 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK || 72 reg == TMIO_SD_ARG) 73 writew(val >> 16, priv->regbase + (reg >> 1) + 2); 74 } else 75 writel(val, priv->regbase + reg); 76 } 77 78 static dma_addr_t __dma_map_single(void *ptr, size_t size, 79 enum dma_data_direction dir) 80 { 81 unsigned long addr = (unsigned long)ptr; 82 83 if (dir == DMA_FROM_DEVICE) 84 invalidate_dcache_range(addr, addr + size); 85 else 86 flush_dcache_range(addr, addr + size); 87 88 return addr; 89 } 90 91 static void __dma_unmap_single(dma_addr_t addr, size_t size, 92 enum dma_data_direction dir) 93 { 94 if (dir != DMA_TO_DEVICE) 95 invalidate_dcache_range(addr, addr + size); 96 } 97 98 static int tmio_sd_check_error(struct udevice *dev) 99 { 100 struct tmio_sd_priv *priv = dev_get_priv(dev); 101 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2); 102 103 if (info2 & TMIO_SD_INFO2_ERR_RTO) { 104 /* 105 * TIMEOUT must be returned for unsupported command. Do not 106 * display error log since this might be a part of sequence to 107 * distinguish between SD and MMC. 108 */ 109 return -ETIMEDOUT; 110 } 111 112 if (info2 & TMIO_SD_INFO2_ERR_TO) { 113 dev_err(dev, "timeout error\n"); 114 return -ETIMEDOUT; 115 } 116 117 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC | 118 TMIO_SD_INFO2_ERR_IDX)) { 119 dev_err(dev, "communication out of sync\n"); 120 return -EILSEQ; 121 } 122 123 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR | 124 TMIO_SD_INFO2_ERR_ILW)) { 125 dev_err(dev, "illegal access\n"); 126 return -EIO; 127 } 128 129 return 0; 130 } 131 132 static int tmio_sd_wait_for_irq(struct udevice *dev, unsigned int reg, 133 u32 flag) 134 { 135 struct tmio_sd_priv *priv = dev_get_priv(dev); 136 long wait = 1000000; 137 int ret; 138 139 while (!(tmio_sd_readl(priv, reg) & flag)) { 140 if (wait-- < 0) { 141 dev_err(dev, "timeout\n"); 142 return -ETIMEDOUT; 143 } 144 145 ret = tmio_sd_check_error(dev); 146 if (ret) 147 return ret; 148 149 udelay(1); 150 } 151 152 return 0; 153 } 154 155 #define tmio_pio_read_fifo(__width, __suffix) \ 156 static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \ 157 char *pbuf, uint blksz) \ 158 { \ 159 u##__width *buf = (u##__width *)pbuf; \ 160 int i; \ 161 \ 162 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \ 163 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 164 *buf++ = tmio_sd_read##__suffix(priv, \ 165 TMIO_SD_BUF); \ 166 } \ 167 } else { \ 168 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 169 u##__width data; \ 170 data = tmio_sd_read##__suffix(priv, \ 171 TMIO_SD_BUF); \ 172 put_unaligned(data, buf++); \ 173 } \ 174 } \ 175 } 176 177 tmio_pio_read_fifo(64, q) 178 tmio_pio_read_fifo(32, l) 179 tmio_pio_read_fifo(16, w) 180 181 static int tmio_sd_pio_read_one_block(struct udevice *dev, char *pbuf, 182 uint blocksize) 183 { 184 struct tmio_sd_priv *priv = dev_get_priv(dev); 185 int ret; 186 187 /* wait until the buffer is filled with data */ 188 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, 189 TMIO_SD_INFO2_BRE); 190 if (ret) 191 return ret; 192 193 /* 194 * Clear the status flag _before_ read the buffer out because 195 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered. 196 */ 197 tmio_sd_writel(priv, 0, TMIO_SD_INFO2); 198 199 if (priv->caps & TMIO_SD_CAP_64BIT) 200 tmio_pio_read_fifo_64(priv, pbuf, blocksize); 201 else if (priv->caps & TMIO_SD_CAP_16BIT) 202 tmio_pio_read_fifo_16(priv, pbuf, blocksize); 203 else 204 tmio_pio_read_fifo_32(priv, pbuf, blocksize); 205 206 return 0; 207 } 208 209 #define tmio_pio_write_fifo(__width, __suffix) \ 210 static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \ 211 const char *pbuf, uint blksz)\ 212 { \ 213 const u##__width *buf = (const u##__width *)pbuf; \ 214 int i; \ 215 \ 216 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \ 217 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 218 tmio_sd_write##__suffix(priv, *buf++, \ 219 TMIO_SD_BUF); \ 220 } \ 221 } else { \ 222 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 223 u##__width data = get_unaligned(buf++); \ 224 tmio_sd_write##__suffix(priv, data, \ 225 TMIO_SD_BUF); \ 226 } \ 227 } \ 228 } 229 230 tmio_pio_write_fifo(64, q) 231 tmio_pio_write_fifo(32, l) 232 tmio_pio_write_fifo(16, w) 233 234 static int tmio_sd_pio_write_one_block(struct udevice *dev, 235 const char *pbuf, uint blocksize) 236 { 237 struct tmio_sd_priv *priv = dev_get_priv(dev); 238 int ret; 239 240 /* wait until the buffer becomes empty */ 241 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, 242 TMIO_SD_INFO2_BWE); 243 if (ret) 244 return ret; 245 246 tmio_sd_writel(priv, 0, TMIO_SD_INFO2); 247 248 if (priv->caps & TMIO_SD_CAP_64BIT) 249 tmio_pio_write_fifo_64(priv, pbuf, blocksize); 250 else if (priv->caps & TMIO_SD_CAP_16BIT) 251 tmio_pio_write_fifo_16(priv, pbuf, blocksize); 252 else 253 tmio_pio_write_fifo_32(priv, pbuf, blocksize); 254 255 return 0; 256 } 257 258 static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_data *data) 259 { 260 const char *src = data->src; 261 char *dest = data->dest; 262 int i, ret; 263 264 for (i = 0; i < data->blocks; i++) { 265 if (data->flags & MMC_DATA_READ) 266 ret = tmio_sd_pio_read_one_block(dev, dest, 267 data->blocksize); 268 else 269 ret = tmio_sd_pio_write_one_block(dev, src, 270 data->blocksize); 271 if (ret) 272 return ret; 273 274 if (data->flags & MMC_DATA_READ) 275 dest += data->blocksize; 276 else 277 src += data->blocksize; 278 } 279 280 return 0; 281 } 282 283 static void tmio_sd_dma_start(struct tmio_sd_priv *priv, 284 dma_addr_t dma_addr) 285 { 286 u32 tmp; 287 288 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1); 289 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2); 290 291 /* enable DMA */ 292 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE); 293 tmp |= TMIO_SD_EXTMODE_DMA_EN; 294 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE); 295 296 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L); 297 298 /* suppress the warning "right shift count >= width of type" */ 299 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); 300 301 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H); 302 303 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL); 304 } 305 306 static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, 307 unsigned int blocks) 308 { 309 struct tmio_sd_priv *priv = dev_get_priv(dev); 310 long wait = 1000000 + 10 * blocks; 311 312 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) { 313 if (wait-- < 0) { 314 dev_err(dev, "timeout during DMA\n"); 315 return -ETIMEDOUT; 316 } 317 318 udelay(10); 319 } 320 321 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) { 322 dev_err(dev, "error during DMA\n"); 323 return -EIO; 324 } 325 326 return 0; 327 } 328 329 static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) 330 { 331 struct tmio_sd_priv *priv = dev_get_priv(dev); 332 size_t len = data->blocks * data->blocksize; 333 void *buf; 334 enum dma_data_direction dir; 335 dma_addr_t dma_addr; 336 u32 poll_flag, tmp; 337 int ret; 338 339 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE); 340 341 if (data->flags & MMC_DATA_READ) { 342 buf = data->dest; 343 dir = DMA_FROM_DEVICE; 344 /* 345 * The DMA READ completion flag position differs on Socionext 346 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using 347 * bit 17 is a hardware bug and forbidden. It is bit 17 on 348 * Renesas SoCs and bit 20 does not work on them. 349 */ 350 poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ? 351 TMIO_SD_DMA_INFO1_END_RD : 352 TMIO_SD_DMA_INFO1_END_RD2; 353 tmp |= TMIO_SD_DMA_MODE_DIR_RD; 354 } else { 355 buf = (void *)data->src; 356 dir = DMA_TO_DEVICE; 357 poll_flag = TMIO_SD_DMA_INFO1_END_WR; 358 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD; 359 } 360 361 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE); 362 363 dma_addr = __dma_map_single(buf, len, dir); 364 365 tmio_sd_dma_start(priv, dma_addr); 366 367 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); 368 369 __dma_unmap_single(dma_addr, len, dir); 370 371 return ret; 372 } 373 374 /* check if the address is DMA'able */ 375 static bool tmio_sd_addr_is_dmaable(unsigned long addr) 376 { 377 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN)) 378 return false; 379 380 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ 381 defined(CONFIG_SPL_BUILD) 382 /* 383 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways 384 * of L2, which is unreachable from the DMA engine. 385 */ 386 if (addr < CONFIG_SPL_STACK) 387 return false; 388 #endif 389 390 return true; 391 } 392 393 int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 394 struct mmc_data *data) 395 { 396 struct tmio_sd_priv *priv = dev_get_priv(dev); 397 int ret; 398 u32 tmp; 399 400 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) { 401 dev_err(dev, "command busy\n"); 402 return -EBUSY; 403 } 404 405 /* clear all status flags */ 406 tmio_sd_writel(priv, 0, TMIO_SD_INFO1); 407 tmio_sd_writel(priv, 0, TMIO_SD_INFO2); 408 409 /* disable DMA once */ 410 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE); 411 tmp &= ~TMIO_SD_EXTMODE_DMA_EN; 412 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE); 413 414 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG); 415 416 tmp = cmd->cmdidx; 417 418 if (data) { 419 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE); 420 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT); 421 422 /* Do not send CMD12 automatically */ 423 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA; 424 425 if (data->blocks > 1) 426 tmp |= TMIO_SD_CMD_MULTI; 427 428 if (data->flags & MMC_DATA_READ) 429 tmp |= TMIO_SD_CMD_RD; 430 } 431 432 /* 433 * Do not use the response type auto-detection on this hardware. 434 * CMD8, for example, has different response types on SD and eMMC, 435 * while this controller always assumes the response type for SD. 436 * Set the response type manually. 437 */ 438 switch (cmd->resp_type) { 439 case MMC_RSP_NONE: 440 tmp |= TMIO_SD_CMD_RSP_NONE; 441 break; 442 case MMC_RSP_R1: 443 tmp |= TMIO_SD_CMD_RSP_R1; 444 break; 445 case MMC_RSP_R1b: 446 tmp |= TMIO_SD_CMD_RSP_R1B; 447 break; 448 case MMC_RSP_R2: 449 tmp |= TMIO_SD_CMD_RSP_R2; 450 break; 451 case MMC_RSP_R3: 452 tmp |= TMIO_SD_CMD_RSP_R3; 453 break; 454 default: 455 dev_err(dev, "unknown response type\n"); 456 return -EINVAL; 457 } 458 459 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", 460 cmd->cmdidx, tmp, cmd->cmdarg); 461 tmio_sd_writel(priv, tmp, TMIO_SD_CMD); 462 463 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1, 464 TMIO_SD_INFO1_RSP); 465 if (ret) 466 return ret; 467 468 if (cmd->resp_type & MMC_RSP_136) { 469 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76); 470 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54); 471 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32); 472 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10); 473 474 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) | 475 ((rsp_103_72 & 0xff000000) >> 24); 476 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) | 477 ((rsp_71_40 & 0xff000000) >> 24); 478 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) | 479 ((rsp_39_8 & 0xff000000) >> 24); 480 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; 481 } else { 482 /* bit 39-8 */ 483 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10); 484 } 485 486 if (data) { 487 /* use DMA if the HW supports it and the buffer is aligned */ 488 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL && 489 tmio_sd_addr_is_dmaable((long)data->src)) 490 ret = tmio_sd_dma_xfer(dev, data); 491 else 492 ret = tmio_sd_pio_xfer(dev, data); 493 494 ret = tmio_sd_wait_for_irq(dev, TMIO_SD_INFO1, 495 TMIO_SD_INFO1_CMP); 496 if (ret) 497 return ret; 498 } 499 500 tmio_sd_wait_for_irq(dev, TMIO_SD_INFO2, TMIO_SD_INFO2_SCLKDIVEN); 501 502 return ret; 503 } 504 505 static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv, 506 struct mmc *mmc) 507 { 508 u32 val, tmp; 509 510 switch (mmc->bus_width) { 511 case 0: 512 case 1: 513 val = TMIO_SD_OPTION_WIDTH_1; 514 break; 515 case 4: 516 val = TMIO_SD_OPTION_WIDTH_4; 517 break; 518 case 8: 519 val = TMIO_SD_OPTION_WIDTH_8; 520 break; 521 default: 522 return -EINVAL; 523 } 524 525 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION); 526 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK; 527 tmp |= val; 528 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION); 529 530 return 0; 531 } 532 533 static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv, 534 struct mmc *mmc) 535 { 536 u32 tmp; 537 538 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE); 539 if (mmc->ddr_mode) 540 tmp |= TMIO_SD_IF_MODE_DDR; 541 else 542 tmp &= ~TMIO_SD_IF_MODE_DDR; 543 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE); 544 } 545 546 static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, 547 struct mmc *mmc) 548 { 549 unsigned int divisor; 550 u32 val, tmp; 551 552 if (!mmc->clock) 553 return; 554 555 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); 556 557 if (divisor <= 1) 558 val = (priv->caps & TMIO_SD_CAP_RCAR) ? 559 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; 560 else if (divisor <= 2) 561 val = TMIO_SD_CLKCTL_DIV2; 562 else if (divisor <= 4) 563 val = TMIO_SD_CLKCTL_DIV4; 564 else if (divisor <= 8) 565 val = TMIO_SD_CLKCTL_DIV8; 566 else if (divisor <= 16) 567 val = TMIO_SD_CLKCTL_DIV16; 568 else if (divisor <= 32) 569 val = TMIO_SD_CLKCTL_DIV32; 570 else if (divisor <= 64) 571 val = TMIO_SD_CLKCTL_DIV64; 572 else if (divisor <= 128) 573 val = TMIO_SD_CLKCTL_DIV128; 574 else if (divisor <= 256) 575 val = TMIO_SD_CLKCTL_DIV256; 576 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024)) 577 val = TMIO_SD_CLKCTL_DIV512; 578 else 579 val = TMIO_SD_CLKCTL_DIV1024; 580 581 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); 582 if (tmp & TMIO_SD_CLKCTL_SCLKEN && 583 (tmp & TMIO_SD_CLKCTL_DIV_MASK) == val) 584 return; 585 586 /* stop the clock before changing its rate to avoid a glitch signal */ 587 tmp &= ~TMIO_SD_CLKCTL_SCLKEN; 588 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); 589 590 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK; 591 tmp |= val | TMIO_SD_CLKCTL_OFFEN; 592 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); 593 594 tmp |= TMIO_SD_CLKCTL_SCLKEN; 595 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); 596 597 udelay(1000); 598 } 599 600 static void tmio_sd_set_pins(struct udevice *dev) 601 { 602 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev); 603 604 #ifdef CONFIG_DM_REGULATOR 605 struct tmio_sd_priv *priv = dev_get_priv(dev); 606 607 if (priv->vqmmc_dev) { 608 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 609 regulator_set_value(priv->vqmmc_dev, 1800000); 610 else 611 regulator_set_value(priv->vqmmc_dev, 3300000); 612 regulator_set_enable(priv->vqmmc_dev, true); 613 } 614 #endif 615 616 #ifdef CONFIG_PINCTRL 617 switch (mmc->selected_mode) { 618 case MMC_LEGACY: 619 case SD_LEGACY: 620 case MMC_HS: 621 case SD_HS: 622 case MMC_HS_52: 623 case MMC_DDR_52: 624 pinctrl_select_state(dev, "default"); 625 break; 626 case UHS_SDR12: 627 case UHS_SDR25: 628 case UHS_SDR50: 629 case UHS_DDR50: 630 case UHS_SDR104: 631 case MMC_HS_200: 632 pinctrl_select_state(dev, "state_uhs"); 633 break; 634 default: 635 break; 636 } 637 #endif 638 } 639 640 int tmio_sd_set_ios(struct udevice *dev) 641 { 642 struct tmio_sd_priv *priv = dev_get_priv(dev); 643 struct mmc *mmc = mmc_get_mmc_dev(dev); 644 int ret; 645 646 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n", 647 mmc->clock, mmc->ddr_mode, mmc->bus_width); 648 649 ret = tmio_sd_set_bus_width(priv, mmc); 650 if (ret) 651 return ret; 652 tmio_sd_set_ddr_mode(priv, mmc); 653 tmio_sd_set_clk_rate(priv, mmc); 654 tmio_sd_set_pins(dev); 655 656 return 0; 657 } 658 659 int tmio_sd_get_cd(struct udevice *dev) 660 { 661 struct tmio_sd_priv *priv = dev_get_priv(dev); 662 663 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE) 664 return 1; 665 666 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) & 667 TMIO_SD_INFO1_CD); 668 } 669 670 static void tmio_sd_host_init(struct tmio_sd_priv *priv) 671 { 672 u32 tmp; 673 674 /* soft reset of the host */ 675 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST); 676 tmp &= ~TMIO_SD_SOFT_RST_RSTX; 677 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST); 678 tmp |= TMIO_SD_SOFT_RST_RSTX; 679 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST); 680 681 /* FIXME: implement eMMC hw_reset */ 682 683 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP); 684 685 /* 686 * Connected to 32bit AXI. 687 * This register dropped backward compatibility at version 0x10. 688 * Write an appropriate value depending on the IP version. 689 */ 690 if (priv->version >= 0x10) 691 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE); 692 else 693 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE); 694 695 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) { 696 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE); 697 tmp |= TMIO_SD_DMA_MODE_ADDR_INC; 698 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE); 699 } 700 } 701 702 int tmio_sd_bind(struct udevice *dev) 703 { 704 struct tmio_sd_plat *plat = dev_get_platdata(dev); 705 706 return mmc_bind(dev, &plat->mmc, &plat->cfg); 707 } 708 709 int tmio_sd_probe(struct udevice *dev, u32 quirks) 710 { 711 struct tmio_sd_plat *plat = dev_get_platdata(dev); 712 struct tmio_sd_priv *priv = dev_get_priv(dev); 713 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 714 fdt_addr_t base; 715 int ret; 716 717 base = devfdt_get_addr(dev); 718 if (base == FDT_ADDR_T_NONE) 719 return -EINVAL; 720 721 priv->regbase = devm_ioremap(dev, base, SZ_2K); 722 if (!priv->regbase) 723 return -ENOMEM; 724 725 #ifdef CONFIG_DM_REGULATOR 726 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev); 727 #endif 728 729 ret = mmc_of_parse(dev, &plat->cfg); 730 if (ret < 0) { 731 dev_err(dev, "failed to parse host caps\n"); 732 return ret; 733 } 734 735 plat->cfg.name = dev->name; 736 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 737 738 if (quirks) 739 priv->caps = quirks; 740 741 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) & 742 TMIO_SD_VERSION_IP; 743 dev_dbg(dev, "version %x\n", priv->version); 744 if (priv->version >= 0x10) { 745 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL; 746 priv->caps |= TMIO_SD_CAP_DIV1024; 747 } 748 749 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable", 750 NULL)) 751 priv->caps |= TMIO_SD_CAP_NONREMOVABLE; 752 753 tmio_sd_host_init(priv); 754 755 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; 756 plat->cfg.f_min = priv->mclk / 757 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512); 758 plat->cfg.f_max = priv->mclk; 759 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ 760 761 upriv->mmc = &plat->mmc; 762 763 return 0; 764 } 765