1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <fdtdec.h> 10 #include <mmc.h> 11 #include <dm.h> 12 #include <dm/pinctrl.h> 13 #include <linux/compat.h> 14 #include <linux/dma-direction.h> 15 #include <linux/io.h> 16 #include <linux/sizes.h> 17 #include <power/regulator.h> 18 #include <asm/unaligned.h> 19 20 #include "tmio-common.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg) 25 { 26 return readq(priv->regbase + (reg << 1)); 27 } 28 29 static void tmio_sd_writeq(struct tmio_sd_priv *priv, 30 u64 val, unsigned int reg) 31 { 32 writeq(val, priv->regbase + (reg << 1)); 33 } 34 35 static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg) 36 { 37 return readw(priv->regbase + (reg >> 1)); 38 } 39 40 static void tmio_sd_writew(struct tmio_sd_priv *priv, 41 u16 val, unsigned int reg) 42 { 43 writew(val, priv->regbase + (reg >> 1)); 44 } 45 46 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg) 47 { 48 u32 val; 49 50 if (priv->caps & TMIO_SD_CAP_64BIT) 51 return readl(priv->regbase + (reg << 1)); 52 else if (priv->caps & TMIO_SD_CAP_16BIT) { 53 val = readw(priv->regbase + (reg >> 1)) & 0xffff; 54 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) || 55 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) { 56 val |= readw(priv->regbase + (reg >> 1) + 2) << 16; 57 } 58 return val; 59 } else 60 return readl(priv->regbase + reg); 61 } 62 63 void tmio_sd_writel(struct tmio_sd_priv *priv, 64 u32 val, unsigned int reg) 65 { 66 if (priv->caps & TMIO_SD_CAP_64BIT) 67 writel(val, priv->regbase + (reg << 1)); 68 else if (priv->caps & TMIO_SD_CAP_16BIT) { 69 writew(val & 0xffff, priv->regbase + (reg >> 1)); 70 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK || 71 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK || 72 reg == TMIO_SD_ARG) 73 writew(val >> 16, priv->regbase + (reg >> 1) + 2); 74 } else 75 writel(val, priv->regbase + reg); 76 } 77 78 static dma_addr_t __dma_map_single(void *ptr, size_t size, 79 enum dma_data_direction dir) 80 { 81 unsigned long addr = (unsigned long)ptr; 82 83 if (dir == DMA_FROM_DEVICE) 84 invalidate_dcache_range(addr, addr + size); 85 else 86 flush_dcache_range(addr, addr + size); 87 88 return addr; 89 } 90 91 static void __dma_unmap_single(dma_addr_t addr, size_t size, 92 enum dma_data_direction dir) 93 { 94 if (dir != DMA_TO_DEVICE) 95 invalidate_dcache_range(addr, addr + size); 96 } 97 98 static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd) 99 { 100 struct tmio_sd_priv *priv = dev_get_priv(dev); 101 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2); 102 103 if (info2 & TMIO_SD_INFO2_ERR_RTO) { 104 /* 105 * TIMEOUT must be returned for unsupported command. Do not 106 * display error log since this might be a part of sequence to 107 * distinguish between SD and MMC. 108 */ 109 return -ETIMEDOUT; 110 } 111 112 if (info2 & TMIO_SD_INFO2_ERR_TO) { 113 dev_err(dev, "timeout error\n"); 114 return -ETIMEDOUT; 115 } 116 117 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC | 118 TMIO_SD_INFO2_ERR_IDX)) { 119 if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) && 120 (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)) 121 dev_err(dev, "communication out of sync\n"); 122 return -EILSEQ; 123 } 124 125 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR | 126 TMIO_SD_INFO2_ERR_ILW)) { 127 dev_err(dev, "illegal access\n"); 128 return -EIO; 129 } 130 131 return 0; 132 } 133 134 static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd, 135 unsigned int reg, u32 flag) 136 { 137 struct tmio_sd_priv *priv = dev_get_priv(dev); 138 long wait = 1000000; 139 int ret; 140 141 while (!(tmio_sd_readl(priv, reg) & flag)) { 142 if (wait-- < 0) { 143 dev_err(dev, "timeout\n"); 144 return -ETIMEDOUT; 145 } 146 147 ret = tmio_sd_check_error(dev, cmd); 148 if (ret) 149 return ret; 150 151 udelay(1); 152 } 153 154 return 0; 155 } 156 157 #define tmio_pio_read_fifo(__width, __suffix) \ 158 static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \ 159 char *pbuf, uint blksz) \ 160 { \ 161 u##__width *buf = (u##__width *)pbuf; \ 162 int i; \ 163 \ 164 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \ 165 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 166 *buf++ = tmio_sd_read##__suffix(priv, \ 167 TMIO_SD_BUF); \ 168 } \ 169 } else { \ 170 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 171 u##__width data; \ 172 data = tmio_sd_read##__suffix(priv, \ 173 TMIO_SD_BUF); \ 174 put_unaligned(data, buf++); \ 175 } \ 176 } \ 177 } 178 179 tmio_pio_read_fifo(64, q) 180 tmio_pio_read_fifo(32, l) 181 tmio_pio_read_fifo(16, w) 182 183 static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd, 184 char *pbuf, uint blocksize) 185 { 186 struct tmio_sd_priv *priv = dev_get_priv(dev); 187 int ret; 188 189 /* wait until the buffer is filled with data */ 190 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2, 191 TMIO_SD_INFO2_BRE); 192 if (ret) 193 return ret; 194 195 /* 196 * Clear the status flag _before_ read the buffer out because 197 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered. 198 */ 199 tmio_sd_writel(priv, 0, TMIO_SD_INFO2); 200 201 if (priv->caps & TMIO_SD_CAP_64BIT) 202 tmio_pio_read_fifo_64(priv, pbuf, blocksize); 203 else if (priv->caps & TMIO_SD_CAP_16BIT) 204 tmio_pio_read_fifo_16(priv, pbuf, blocksize); 205 else 206 tmio_pio_read_fifo_32(priv, pbuf, blocksize); 207 208 return 0; 209 } 210 211 #define tmio_pio_write_fifo(__width, __suffix) \ 212 static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \ 213 const char *pbuf, uint blksz)\ 214 { \ 215 const u##__width *buf = (const u##__width *)pbuf; \ 216 int i; \ 217 \ 218 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \ 219 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 220 tmio_sd_write##__suffix(priv, *buf++, \ 221 TMIO_SD_BUF); \ 222 } \ 223 } else { \ 224 for (i = 0; i < blksz / ((__width) / 8); i++) { \ 225 u##__width data = get_unaligned(buf++); \ 226 tmio_sd_write##__suffix(priv, data, \ 227 TMIO_SD_BUF); \ 228 } \ 229 } \ 230 } 231 232 tmio_pio_write_fifo(64, q) 233 tmio_pio_write_fifo(32, l) 234 tmio_pio_write_fifo(16, w) 235 236 static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd, 237 const char *pbuf, uint blocksize) 238 { 239 struct tmio_sd_priv *priv = dev_get_priv(dev); 240 int ret; 241 242 /* wait until the buffer becomes empty */ 243 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2, 244 TMIO_SD_INFO2_BWE); 245 if (ret) 246 return ret; 247 248 tmio_sd_writel(priv, 0, TMIO_SD_INFO2); 249 250 if (priv->caps & TMIO_SD_CAP_64BIT) 251 tmio_pio_write_fifo_64(priv, pbuf, blocksize); 252 else if (priv->caps & TMIO_SD_CAP_16BIT) 253 tmio_pio_write_fifo_16(priv, pbuf, blocksize); 254 else 255 tmio_pio_write_fifo_32(priv, pbuf, blocksize); 256 257 return 0; 258 } 259 260 static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd, 261 struct mmc_data *data) 262 { 263 const char *src = data->src; 264 char *dest = data->dest; 265 int i, ret; 266 267 for (i = 0; i < data->blocks; i++) { 268 if (data->flags & MMC_DATA_READ) 269 ret = tmio_sd_pio_read_one_block(dev, cmd, dest, 270 data->blocksize); 271 else 272 ret = tmio_sd_pio_write_one_block(dev, cmd, src, 273 data->blocksize); 274 if (ret) 275 return ret; 276 277 if (data->flags & MMC_DATA_READ) 278 dest += data->blocksize; 279 else 280 src += data->blocksize; 281 } 282 283 return 0; 284 } 285 286 static void tmio_sd_dma_start(struct tmio_sd_priv *priv, 287 dma_addr_t dma_addr) 288 { 289 u32 tmp; 290 291 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1); 292 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2); 293 294 /* enable DMA */ 295 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE); 296 tmp |= TMIO_SD_EXTMODE_DMA_EN; 297 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE); 298 299 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L); 300 301 /* suppress the warning "right shift count >= width of type" */ 302 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr)); 303 304 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H); 305 306 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL); 307 } 308 309 static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag, 310 unsigned int blocks) 311 { 312 struct tmio_sd_priv *priv = dev_get_priv(dev); 313 long wait = 1000000 + 10 * blocks; 314 315 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) { 316 if (wait-- < 0) { 317 dev_err(dev, "timeout during DMA\n"); 318 return -ETIMEDOUT; 319 } 320 321 udelay(10); 322 } 323 324 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) { 325 dev_err(dev, "error during DMA\n"); 326 return -EIO; 327 } 328 329 return 0; 330 } 331 332 static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data) 333 { 334 struct tmio_sd_priv *priv = dev_get_priv(dev); 335 size_t len = data->blocks * data->blocksize; 336 void *buf; 337 enum dma_data_direction dir; 338 dma_addr_t dma_addr; 339 u32 poll_flag, tmp; 340 int ret; 341 342 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE); 343 344 if (data->flags & MMC_DATA_READ) { 345 buf = data->dest; 346 dir = DMA_FROM_DEVICE; 347 /* 348 * The DMA READ completion flag position differs on Socionext 349 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using 350 * bit 17 is a hardware bug and forbidden. It is bit 17 on 351 * Renesas SoCs and bit 20 does not work on them. 352 */ 353 poll_flag = (priv->caps & TMIO_SD_CAP_RCAR) ? 354 TMIO_SD_DMA_INFO1_END_RD : 355 TMIO_SD_DMA_INFO1_END_RD2; 356 tmp |= TMIO_SD_DMA_MODE_DIR_RD; 357 } else { 358 buf = (void *)data->src; 359 dir = DMA_TO_DEVICE; 360 poll_flag = TMIO_SD_DMA_INFO1_END_WR; 361 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD; 362 } 363 364 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE); 365 366 dma_addr = __dma_map_single(buf, len, dir); 367 368 tmio_sd_dma_start(priv, dma_addr); 369 370 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks); 371 372 __dma_unmap_single(dma_addr, len, dir); 373 374 return ret; 375 } 376 377 /* check if the address is DMA'able */ 378 static bool tmio_sd_addr_is_dmaable(const char *src) 379 { 380 uintptr_t addr = (uintptr_t)src; 381 382 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN)) 383 return false; 384 385 #if defined(CONFIG_RCAR_GEN3) 386 /* Gen3 DMA has 32bit limit */ 387 if (addr >> 32) 388 return false; 389 #endif 390 391 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \ 392 defined(CONFIG_SPL_BUILD) 393 /* 394 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways 395 * of L2, which is unreachable from the DMA engine. 396 */ 397 if (addr < CONFIG_SPL_STACK) 398 return false; 399 #endif 400 401 return true; 402 } 403 404 int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 405 struct mmc_data *data) 406 { 407 struct tmio_sd_priv *priv = dev_get_priv(dev); 408 int ret; 409 u32 tmp; 410 411 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) { 412 dev_err(dev, "command busy\n"); 413 return -EBUSY; 414 } 415 416 /* clear all status flags */ 417 tmio_sd_writel(priv, 0, TMIO_SD_INFO1); 418 tmio_sd_writel(priv, 0, TMIO_SD_INFO2); 419 420 /* disable DMA once */ 421 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE); 422 tmp &= ~TMIO_SD_EXTMODE_DMA_EN; 423 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE); 424 425 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG); 426 427 tmp = cmd->cmdidx; 428 429 if (data) { 430 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE); 431 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT); 432 433 /* Do not send CMD12 automatically */ 434 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA; 435 436 if (data->blocks > 1) 437 tmp |= TMIO_SD_CMD_MULTI; 438 439 if (data->flags & MMC_DATA_READ) 440 tmp |= TMIO_SD_CMD_RD; 441 } 442 443 /* 444 * Do not use the response type auto-detection on this hardware. 445 * CMD8, for example, has different response types on SD and eMMC, 446 * while this controller always assumes the response type for SD. 447 * Set the response type manually. 448 */ 449 switch (cmd->resp_type) { 450 case MMC_RSP_NONE: 451 tmp |= TMIO_SD_CMD_RSP_NONE; 452 break; 453 case MMC_RSP_R1: 454 tmp |= TMIO_SD_CMD_RSP_R1; 455 break; 456 case MMC_RSP_R1b: 457 tmp |= TMIO_SD_CMD_RSP_R1B; 458 break; 459 case MMC_RSP_R2: 460 tmp |= TMIO_SD_CMD_RSP_R2; 461 break; 462 case MMC_RSP_R3: 463 tmp |= TMIO_SD_CMD_RSP_R3; 464 break; 465 default: 466 dev_err(dev, "unknown response type\n"); 467 return -EINVAL; 468 } 469 470 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n", 471 cmd->cmdidx, tmp, cmd->cmdarg); 472 tmio_sd_writel(priv, tmp, TMIO_SD_CMD); 473 474 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1, 475 TMIO_SD_INFO1_RSP); 476 if (ret) 477 return ret; 478 479 if (cmd->resp_type & MMC_RSP_136) { 480 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76); 481 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54); 482 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32); 483 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10); 484 485 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) | 486 ((rsp_103_72 & 0xff000000) >> 24); 487 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) | 488 ((rsp_71_40 & 0xff000000) >> 24); 489 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) | 490 ((rsp_39_8 & 0xff000000) >> 24); 491 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8; 492 } else { 493 /* bit 39-8 */ 494 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10); 495 } 496 497 if (data) { 498 /* use DMA if the HW supports it and the buffer is aligned */ 499 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL && 500 tmio_sd_addr_is_dmaable(data->src)) 501 ret = tmio_sd_dma_xfer(dev, data); 502 else 503 ret = tmio_sd_pio_xfer(dev, cmd, data); 504 if (ret) 505 return ret; 506 507 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1, 508 TMIO_SD_INFO1_CMP); 509 if (ret) 510 return ret; 511 } 512 513 return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2, 514 TMIO_SD_INFO2_SCLKDIVEN); 515 } 516 517 static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv, 518 struct mmc *mmc) 519 { 520 u32 val, tmp; 521 522 switch (mmc->bus_width) { 523 case 0: 524 case 1: 525 val = TMIO_SD_OPTION_WIDTH_1; 526 break; 527 case 4: 528 val = TMIO_SD_OPTION_WIDTH_4; 529 break; 530 case 8: 531 val = TMIO_SD_OPTION_WIDTH_8; 532 break; 533 default: 534 return -EINVAL; 535 } 536 537 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION); 538 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK; 539 tmp |= val; 540 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION); 541 542 return 0; 543 } 544 545 static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv, 546 struct mmc *mmc) 547 { 548 u32 tmp; 549 550 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE); 551 if (mmc->ddr_mode) 552 tmp |= TMIO_SD_IF_MODE_DDR; 553 else 554 tmp &= ~TMIO_SD_IF_MODE_DDR; 555 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE); 556 } 557 558 static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, 559 struct mmc *mmc) 560 { 561 unsigned int divisor; 562 u32 val, tmp; 563 564 if (!mmc->clock) 565 return; 566 567 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock); 568 569 if (divisor <= 1) 570 val = (priv->caps & TMIO_SD_CAP_RCAR) ? 571 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; 572 else if (divisor <= 2) 573 val = TMIO_SD_CLKCTL_DIV2; 574 else if (divisor <= 4) 575 val = TMIO_SD_CLKCTL_DIV4; 576 else if (divisor <= 8) 577 val = TMIO_SD_CLKCTL_DIV8; 578 else if (divisor <= 16) 579 val = TMIO_SD_CLKCTL_DIV16; 580 else if (divisor <= 32) 581 val = TMIO_SD_CLKCTL_DIV32; 582 else if (divisor <= 64) 583 val = TMIO_SD_CLKCTL_DIV64; 584 else if (divisor <= 128) 585 val = TMIO_SD_CLKCTL_DIV128; 586 else if (divisor <= 256) 587 val = TMIO_SD_CLKCTL_DIV256; 588 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024)) 589 val = TMIO_SD_CLKCTL_DIV512; 590 else 591 val = TMIO_SD_CLKCTL_DIV1024; 592 593 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL); 594 if (tmp & TMIO_SD_CLKCTL_SCLKEN && 595 (tmp & TMIO_SD_CLKCTL_DIV_MASK) == val) 596 return; 597 598 /* stop the clock before changing its rate to avoid a glitch signal */ 599 tmp &= ~TMIO_SD_CLKCTL_SCLKEN; 600 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); 601 602 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK; 603 tmp |= val | TMIO_SD_CLKCTL_OFFEN; 604 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); 605 606 tmp |= TMIO_SD_CLKCTL_SCLKEN; 607 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL); 608 609 udelay(1000); 610 } 611 612 static void tmio_sd_set_pins(struct udevice *dev) 613 { 614 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev); 615 616 #ifdef CONFIG_DM_REGULATOR 617 struct tmio_sd_priv *priv = dev_get_priv(dev); 618 619 if (priv->vqmmc_dev) { 620 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 621 regulator_set_value(priv->vqmmc_dev, 1800000); 622 else 623 regulator_set_value(priv->vqmmc_dev, 3300000); 624 regulator_set_enable(priv->vqmmc_dev, true); 625 } 626 #endif 627 628 #ifdef CONFIG_PINCTRL 629 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 630 pinctrl_select_state(dev, "state_uhs"); 631 else 632 pinctrl_select_state(dev, "default"); 633 #endif 634 } 635 636 int tmio_sd_set_ios(struct udevice *dev) 637 { 638 struct tmio_sd_priv *priv = dev_get_priv(dev); 639 struct mmc *mmc = mmc_get_mmc_dev(dev); 640 int ret; 641 642 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n", 643 mmc->clock, mmc->ddr_mode, mmc->bus_width); 644 645 tmio_sd_set_clk_rate(priv, mmc); 646 ret = tmio_sd_set_bus_width(priv, mmc); 647 if (ret) 648 return ret; 649 tmio_sd_set_ddr_mode(priv, mmc); 650 tmio_sd_set_pins(dev); 651 652 return 0; 653 } 654 655 int tmio_sd_get_cd(struct udevice *dev) 656 { 657 struct tmio_sd_priv *priv = dev_get_priv(dev); 658 659 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE) 660 return 1; 661 662 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) & 663 TMIO_SD_INFO1_CD); 664 } 665 666 static void tmio_sd_host_init(struct tmio_sd_priv *priv) 667 { 668 u32 tmp; 669 670 /* soft reset of the host */ 671 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST); 672 tmp &= ~TMIO_SD_SOFT_RST_RSTX; 673 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST); 674 tmp |= TMIO_SD_SOFT_RST_RSTX; 675 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST); 676 677 /* FIXME: implement eMMC hw_reset */ 678 679 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP); 680 681 /* 682 * Connected to 32bit AXI. 683 * This register dropped backward compatibility at version 0x10. 684 * Write an appropriate value depending on the IP version. 685 */ 686 if (priv->version >= 0x10) 687 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE); 688 else 689 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE); 690 691 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) { 692 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE); 693 tmp |= TMIO_SD_DMA_MODE_ADDR_INC; 694 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE); 695 } 696 } 697 698 int tmio_sd_bind(struct udevice *dev) 699 { 700 struct tmio_sd_plat *plat = dev_get_platdata(dev); 701 702 return mmc_bind(dev, &plat->mmc, &plat->cfg); 703 } 704 705 int tmio_sd_probe(struct udevice *dev, u32 quirks) 706 { 707 struct tmio_sd_plat *plat = dev_get_platdata(dev); 708 struct tmio_sd_priv *priv = dev_get_priv(dev); 709 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 710 fdt_addr_t base; 711 int ret; 712 713 base = devfdt_get_addr(dev); 714 if (base == FDT_ADDR_T_NONE) 715 return -EINVAL; 716 717 priv->regbase = devm_ioremap(dev, base, SZ_2K); 718 if (!priv->regbase) 719 return -ENOMEM; 720 721 #ifdef CONFIG_DM_REGULATOR 722 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev); 723 if (priv->vqmmc_dev) 724 regulator_set_value(priv->vqmmc_dev, 3300000); 725 #endif 726 727 ret = mmc_of_parse(dev, &plat->cfg); 728 if (ret < 0) { 729 dev_err(dev, "failed to parse host caps\n"); 730 return ret; 731 } 732 733 plat->cfg.name = dev->name; 734 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 735 736 if (quirks) 737 priv->caps = quirks; 738 739 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) & 740 TMIO_SD_VERSION_IP; 741 dev_dbg(dev, "version %x\n", priv->version); 742 if (priv->version >= 0x10) { 743 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL; 744 priv->caps |= TMIO_SD_CAP_DIV1024; 745 } 746 747 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable", 748 NULL)) 749 priv->caps |= TMIO_SD_CAP_NONREMOVABLE; 750 751 tmio_sd_host_init(priv); 752 753 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; 754 plat->cfg.f_min = priv->mclk / 755 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512); 756 plat->cfg.f_max = priv->mclk; 757 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */ 758 759 upriv->mmc = &plat->mmc; 760 761 return 0; 762 } 763