1 /* 2 * (C) Copyright 2009 SAMSUNG Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 * Portions Copyright 2011-2013 NVIDIA Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <bouncebuf.h> 11 #include <common.h> 12 #include <asm/gpio.h> 13 #include <asm/io.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <asm/arch-tegra/mmc.h> 17 #include <asm/arch-tegra/tegra_mmc.h> 18 #include <mmc.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE]; 23 24 #ifndef CONFIG_OF_CONTROL 25 #error "Please enable device tree support to use this driver" 26 #endif 27 28 static void mmc_set_power(struct mmc_host *host, unsigned short power) 29 { 30 u8 pwr = 0; 31 debug("%s: power = %x\n", __func__, power); 32 33 if (power != (unsigned short)-1) { 34 switch (1 << power) { 35 case MMC_VDD_165_195: 36 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; 37 break; 38 case MMC_VDD_29_30: 39 case MMC_VDD_30_31: 40 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; 41 break; 42 case MMC_VDD_32_33: 43 case MMC_VDD_33_34: 44 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; 45 break; 46 } 47 } 48 debug("%s: pwr = %X\n", __func__, pwr); 49 50 /* Set the bus voltage first (if any) */ 51 writeb(pwr, &host->reg->pwrcon); 52 if (pwr == 0) 53 return; 54 55 /* Now enable bus power */ 56 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER; 57 writeb(pwr, &host->reg->pwrcon); 58 } 59 60 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data, 61 struct bounce_buffer *bbstate) 62 { 63 unsigned char ctrl; 64 65 66 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", 67 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, 68 data->blocksize); 69 70 writel((u32)bbstate->bounce_buffer, &host->reg->sysad); 71 /* 72 * DMASEL[4:3] 73 * 00 = Selects SDMA 74 * 01 = Reserved 75 * 10 = Selects 32-bit Address ADMA2 76 * 11 = Selects 64-bit Address ADMA2 77 */ 78 ctrl = readb(&host->reg->hostctl); 79 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; 80 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; 81 writeb(ctrl, &host->reg->hostctl); 82 83 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 84 writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize); 85 writew(data->blocks, &host->reg->blkcnt); 86 } 87 88 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data) 89 { 90 unsigned short mode; 91 debug(" mmc_set_transfer_mode called\n"); 92 /* 93 * TRNMOD 94 * MUL1SIN0[5] : Multi/Single Block Select 95 * RD1WT0[4] : Data Transfer Direction Select 96 * 1 = read 97 * 0 = write 98 * ENACMD12[2] : Auto CMD12 Enable 99 * ENBLKCNT[1] : Block Count Enable 100 * ENDMA[0] : DMA Enable 101 */ 102 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | 103 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); 104 105 if (data->blocks > 1) 106 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; 107 108 if (data->flags & MMC_DATA_READ) 109 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; 110 111 writew(mode, &host->reg->trnmod); 112 } 113 114 static int mmc_wait_inhibit(struct mmc_host *host, 115 struct mmc_cmd *cmd, 116 struct mmc_data *data, 117 unsigned int timeout) 118 { 119 /* 120 * PRNSTS 121 * CMDINHDAT[1] : Command Inhibit (DAT) 122 * CMDINHCMD[0] : Command Inhibit (CMD) 123 */ 124 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; 125 126 /* 127 * We shouldn't wait for data inhibit for stop commands, even 128 * though they might use busy signaling 129 */ 130 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) 131 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; 132 133 while (readl(&host->reg->prnsts) & mask) { 134 if (timeout == 0) { 135 printf("%s: timeout error\n", __func__); 136 return -1; 137 } 138 timeout--; 139 udelay(1000); 140 } 141 142 return 0; 143 } 144 145 static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, 146 struct mmc_data *data, struct bounce_buffer *bbstate) 147 { 148 struct mmc_host *host = mmc->priv; 149 int flags, i; 150 int result; 151 unsigned int mask = 0; 152 unsigned int retry = 0x100000; 153 debug(" mmc_send_cmd called\n"); 154 155 result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */); 156 157 if (result < 0) 158 return result; 159 160 if (data) 161 mmc_prepare_data(host, data, bbstate); 162 163 debug("cmd->arg: %08x\n", cmd->cmdarg); 164 writel(cmd->cmdarg, &host->reg->argument); 165 166 if (data) 167 mmc_set_transfer_mode(host, data); 168 169 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 170 return -1; 171 172 /* 173 * CMDREG 174 * CMDIDX[13:8] : Command index 175 * DATAPRNT[5] : Data Present Select 176 * ENCMDIDX[4] : Command Index Check Enable 177 * ENCMDCRC[3] : Command CRC Check Enable 178 * RSPTYP[1:0] 179 * 00 = No Response 180 * 01 = Length 136 181 * 10 = Length 48 182 * 11 = Length 48 Check busy after response 183 */ 184 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 185 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; 186 else if (cmd->resp_type & MMC_RSP_136) 187 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; 188 else if (cmd->resp_type & MMC_RSP_BUSY) 189 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; 190 else 191 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; 192 193 if (cmd->resp_type & MMC_RSP_CRC) 194 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; 195 if (cmd->resp_type & MMC_RSP_OPCODE) 196 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; 197 if (data) 198 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; 199 200 debug("cmd: %d\n", cmd->cmdidx); 201 202 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); 203 204 for (i = 0; i < retry; i++) { 205 mask = readl(&host->reg->norintsts); 206 /* Command Complete */ 207 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { 208 if (!data) 209 writel(mask, &host->reg->norintsts); 210 break; 211 } 212 } 213 214 if (i == retry) { 215 printf("%s: waiting for status update\n", __func__); 216 writel(mask, &host->reg->norintsts); 217 return TIMEOUT; 218 } 219 220 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { 221 /* Timeout Error */ 222 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); 223 writel(mask, &host->reg->norintsts); 224 return TIMEOUT; 225 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 226 /* Error Interrupt */ 227 debug("error: %08x cmd %d\n", mask, cmd->cmdidx); 228 writel(mask, &host->reg->norintsts); 229 return -1; 230 } 231 232 if (cmd->resp_type & MMC_RSP_PRESENT) { 233 if (cmd->resp_type & MMC_RSP_136) { 234 /* CRC is stripped so we need to do some shifting. */ 235 for (i = 0; i < 4; i++) { 236 unsigned int offset = 237 (unsigned int)(&host->reg->rspreg3 - i); 238 cmd->response[i] = readl(offset) << 8; 239 240 if (i != 3) { 241 cmd->response[i] |= 242 readb(offset - 1); 243 } 244 debug("cmd->resp[%d]: %08x\n", 245 i, cmd->response[i]); 246 } 247 } else if (cmd->resp_type & MMC_RSP_BUSY) { 248 for (i = 0; i < retry; i++) { 249 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ 250 if (readl(&host->reg->prnsts) 251 & (1 << 20)) /* DAT[0] */ 252 break; 253 } 254 255 if (i == retry) { 256 printf("%s: card is still busy\n", __func__); 257 writel(mask, &host->reg->norintsts); 258 return TIMEOUT; 259 } 260 261 cmd->response[0] = readl(&host->reg->rspreg0); 262 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 263 } else { 264 cmd->response[0] = readl(&host->reg->rspreg0); 265 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 266 } 267 } 268 269 if (data) { 270 unsigned long start = get_timer(0); 271 272 while (1) { 273 mask = readl(&host->reg->norintsts); 274 275 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 276 /* Error Interrupt */ 277 writel(mask, &host->reg->norintsts); 278 printf("%s: error during transfer: 0x%08x\n", 279 __func__, mask); 280 return -1; 281 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { 282 /* 283 * DMA Interrupt, restart the transfer where 284 * it was interrupted. 285 */ 286 unsigned int address = readl(&host->reg->sysad); 287 288 debug("DMA end\n"); 289 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, 290 &host->reg->norintsts); 291 writel(address, &host->reg->sysad); 292 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { 293 /* Transfer Complete */ 294 debug("r/w is done\n"); 295 break; 296 } else if (get_timer(start) > 8000UL) { 297 writel(mask, &host->reg->norintsts); 298 printf("%s: MMC Timeout\n" 299 " Interrupt status 0x%08x\n" 300 " Interrupt status enable 0x%08x\n" 301 " Interrupt signal enable 0x%08x\n" 302 " Present status 0x%08x\n", 303 __func__, mask, 304 readl(&host->reg->norintstsen), 305 readl(&host->reg->norintsigen), 306 readl(&host->reg->prnsts)); 307 return -1; 308 } 309 } 310 writel(mask, &host->reg->norintsts); 311 } 312 313 udelay(1000); 314 return 0; 315 } 316 317 static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 318 struct mmc_data *data) 319 { 320 void *buf; 321 unsigned int bbflags; 322 size_t len; 323 struct bounce_buffer bbstate; 324 int ret; 325 326 if (data) { 327 if (data->flags & MMC_DATA_READ) { 328 buf = data->dest; 329 bbflags = GEN_BB_WRITE; 330 } else { 331 buf = (void *)data->src; 332 bbflags = GEN_BB_READ; 333 } 334 len = data->blocks * data->blocksize; 335 336 bounce_buffer_start(&bbstate, buf, len, bbflags); 337 } 338 339 ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate); 340 341 if (data) 342 bounce_buffer_stop(&bbstate); 343 344 return ret; 345 } 346 347 static void mmc_change_clock(struct mmc_host *host, uint clock) 348 { 349 int div; 350 unsigned short clk; 351 unsigned long timeout; 352 353 debug(" mmc_change_clock called\n"); 354 355 /* 356 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0 357 */ 358 if (clock == 0) 359 goto out; 360 clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock, 361 &div); 362 debug("div = %d\n", div); 363 364 writew(0, &host->reg->clkcon); 365 366 /* 367 * CLKCON 368 * SELFREQ[15:8] : base clock divided by value 369 * ENSDCLK[2] : SD Clock Enable 370 * STBLINTCLK[1] : Internal Clock Stable 371 * ENINTCLK[0] : Internal Clock Enable 372 */ 373 div >>= 1; 374 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | 375 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); 376 writew(clk, &host->reg->clkcon); 377 378 /* Wait max 10 ms */ 379 timeout = 10; 380 while (!(readw(&host->reg->clkcon) & 381 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { 382 if (timeout == 0) { 383 printf("%s: timeout error\n", __func__); 384 return; 385 } 386 timeout--; 387 udelay(1000); 388 } 389 390 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 391 writew(clk, &host->reg->clkcon); 392 393 debug("mmc_change_clock: clkcon = %08X\n", clk); 394 395 out: 396 host->clock = clock; 397 } 398 399 static void tegra_mmc_set_ios(struct mmc *mmc) 400 { 401 struct mmc_host *host = mmc->priv; 402 unsigned char ctrl; 403 debug(" mmc_set_ios called\n"); 404 405 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); 406 407 /* Change clock first */ 408 mmc_change_clock(host, mmc->clock); 409 410 ctrl = readb(&host->reg->hostctl); 411 412 /* 413 * WIDE8[5] 414 * 0 = Depend on WIDE4 415 * 1 = 8-bit mode 416 * WIDE4[1] 417 * 1 = 4-bit mode 418 * 0 = 1-bit mode 419 */ 420 if (mmc->bus_width == 8) 421 ctrl |= (1 << 5); 422 else if (mmc->bus_width == 4) 423 ctrl |= (1 << 1); 424 else 425 ctrl &= ~(1 << 1); 426 427 writeb(ctrl, &host->reg->hostctl); 428 debug("mmc_set_ios: hostctl = %08X\n", ctrl); 429 } 430 431 static void mmc_reset(struct mmc_host *host, struct mmc *mmc) 432 { 433 unsigned int timeout; 434 debug(" mmc_reset called\n"); 435 436 /* 437 * RSTALL[0] : Software reset for all 438 * 1 = reset 439 * 0 = work 440 */ 441 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst); 442 443 host->clock = 0; 444 445 /* Wait max 100 ms */ 446 timeout = 100; 447 448 /* hw clears the bit when it's done */ 449 while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { 450 if (timeout == 0) { 451 printf("%s: timeout error\n", __func__); 452 return; 453 } 454 timeout--; 455 udelay(1000); 456 } 457 458 /* Set SD bus voltage & enable bus power */ 459 mmc_set_power(host, fls(mmc->cfg->voltages) - 1); 460 debug("%s: power control = %02X, host control = %02X\n", __func__, 461 readb(&host->reg->pwrcon), readb(&host->reg->hostctl)); 462 463 /* Make sure SDIO pads are set up */ 464 pad_init_mmc(host); 465 } 466 467 static int tegra_mmc_core_init(struct mmc *mmc) 468 { 469 struct mmc_host *host = mmc->priv; 470 unsigned int mask; 471 debug(" mmc_core_init called\n"); 472 473 mmc_reset(host, mmc); 474 475 host->version = readw(&host->reg->hcver); 476 debug("host version = %x\n", host->version); 477 478 /* mask all */ 479 writel(0xffffffff, &host->reg->norintstsen); 480 writel(0xffffffff, &host->reg->norintsigen); 481 482 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */ 483 /* 484 * NORMAL Interrupt Status Enable Register init 485 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable 486 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable 487 * [3] ENSTADMAINT : DMA boundary interrupt 488 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable 489 * [0] ENSTACMDCMPLT : Command Complete Status Enable 490 */ 491 mask = readl(&host->reg->norintstsen); 492 mask &= ~(0xffff); 493 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | 494 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | 495 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | 496 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | 497 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); 498 writel(mask, &host->reg->norintstsen); 499 500 /* 501 * NORMAL Interrupt Signal Enable Register init 502 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable 503 */ 504 mask = readl(&host->reg->norintsigen); 505 mask &= ~(0xffff); 506 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; 507 writel(mask, &host->reg->norintsigen); 508 509 return 0; 510 } 511 512 static int tegra_mmc_getcd(struct mmc *mmc) 513 { 514 struct mmc_host *host = mmc->priv; 515 516 debug("tegra_mmc_getcd called\n"); 517 518 if (fdt_gpio_isvalid(&host->cd_gpio)) 519 return fdtdec_get_gpio(&host->cd_gpio); 520 521 return 1; 522 } 523 524 static const struct mmc_ops tegra_mmc_ops = { 525 .send_cmd = tegra_mmc_send_cmd, 526 .set_ios = tegra_mmc_set_ios, 527 .init = tegra_mmc_core_init, 528 .getcd = tegra_mmc_getcd, 529 }; 530 531 static int do_mmc_init(int dev_index) 532 { 533 struct mmc_host *host; 534 char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */ 535 struct mmc *mmc; 536 537 /* DT should have been read & host config filled in */ 538 host = &mmc_host[dev_index]; 539 if (!host->enabled) 540 return -1; 541 542 debug(" do_mmc_init: index %d, bus width %d " 543 "pwr_gpio %d cd_gpio %d\n", 544 dev_index, host->width, 545 host->pwr_gpio.gpio, host->cd_gpio.gpio); 546 547 host->clock = 0; 548 clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); 549 550 if (fdt_gpio_isvalid(&host->pwr_gpio)) { 551 sprintf(gpusage, "SD/MMC%d PWR", dev_index); 552 gpio_request(host->pwr_gpio.gpio, gpusage); 553 gpio_direction_output(host->pwr_gpio.gpio, 1); 554 debug(" Power GPIO name = %s\n", host->pwr_gpio.name); 555 } 556 557 if (fdt_gpio_isvalid(&host->cd_gpio)) { 558 sprintf(gpusage, "SD/MMC%d CD", dev_index); 559 gpio_request(host->cd_gpio.gpio, gpusage); 560 gpio_direction_input(host->cd_gpio.gpio); 561 debug(" CD GPIO name = %s\n", host->cd_gpio.name); 562 } 563 564 memset(&host->cfg, 0, sizeof(host->cfg)); 565 566 host->cfg.name = "Tegra SD/MMC"; 567 host->cfg.ops = &tegra_mmc_ops; 568 569 host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 570 host->cfg.host_caps = 0; 571 if (host->width == 8) 572 host->cfg.host_caps |= MMC_MODE_8BIT; 573 if (host->width >= 4) 574 host->cfg.host_caps |= MMC_MODE_4BIT; 575 host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; 576 577 /* 578 * min freq is for card identification, and is the highest 579 * low-speed SDIO card frequency (actually 400KHz) 580 * max freq is highest HS eMMC clock as per the SD/MMC spec 581 * (actually 52MHz) 582 */ 583 host->cfg.f_min = 375000; 584 host->cfg.f_max = 48000000; 585 586 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 587 588 mmc = mmc_create(&host->cfg, host); 589 if (mmc == NULL) 590 return -1; 591 592 return 0; 593 } 594 595 /** 596 * Get the host address and peripheral ID for a node. 597 * 598 * @param blob fdt blob 599 * @param node Device index (0-3) 600 * @param host Structure to fill in (reg, width, mmc_id) 601 */ 602 static int mmc_get_config(const void *blob, int node, struct mmc_host *host) 603 { 604 debug("%s: node = %d\n", __func__, node); 605 606 host->enabled = fdtdec_get_is_enabled(blob, node); 607 608 host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg"); 609 if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) { 610 debug("%s: no sdmmc base reg info found\n", __func__); 611 return -FDT_ERR_NOTFOUND; 612 } 613 614 host->mmc_id = clock_decode_periph_id(blob, node); 615 if (host->mmc_id == PERIPH_ID_NONE) { 616 debug("%s: could not decode periph id\n", __func__); 617 return -FDT_ERR_NOTFOUND; 618 } 619 620 /* 621 * NOTE: mmc->bus_width is determined by mmc.c dynamically. 622 * TBD: Override it with this value? 623 */ 624 host->width = fdtdec_get_int(blob, node, "bus-width", 0); 625 if (!host->width) 626 debug("%s: no sdmmc width found\n", __func__); 627 628 /* These GPIOs are optional */ 629 fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio); 630 fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio); 631 fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio); 632 633 debug("%s: found controller at %p, width = %d, periph_id = %d\n", 634 __func__, host->reg, host->width, host->mmc_id); 635 return 0; 636 } 637 638 /* 639 * Process a list of nodes, adding them to our list of SDMMC ports. 640 * 641 * @param blob fdt blob 642 * @param node_list list of nodes to process (any <=0 are ignored) 643 * @param count number of nodes to process 644 * @return 0 if ok, -1 on error 645 */ 646 static int process_nodes(const void *blob, int node_list[], int count) 647 { 648 struct mmc_host *host; 649 int i, node; 650 651 debug("%s: count = %d\n", __func__, count); 652 653 /* build mmc_host[] for each controller */ 654 for (i = 0; i < count; i++) { 655 node = node_list[i]; 656 if (node <= 0) 657 continue; 658 659 host = &mmc_host[i]; 660 host->id = i; 661 662 if (mmc_get_config(blob, node, host)) { 663 printf("%s: failed to decode dev %d\n", __func__, i); 664 return -1; 665 } 666 do_mmc_init(i); 667 } 668 return 0; 669 } 670 671 void tegra_mmc_init(void) 672 { 673 int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count; 674 const void *blob = gd->fdt_blob; 675 debug("%s entry\n", __func__); 676 677 /* See if any Tegra124 MMC controllers are present */ 678 count = fdtdec_find_aliases_for_id(blob, "sdhci", 679 COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, 680 CONFIG_SYS_MMC_MAX_DEVICE); 681 debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count); 682 if (process_nodes(blob, node_list, count)) { 683 printf("%s: Error processing T30 mmc node(s)!\n", __func__); 684 return; 685 } 686 687 /* See if any Tegra30 MMC controllers are present */ 688 count = fdtdec_find_aliases_for_id(blob, "sdhci", 689 COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, 690 CONFIG_SYS_MMC_MAX_DEVICE); 691 debug("%s: count of T30 sdhci nodes is %d\n", __func__, count); 692 if (process_nodes(blob, node_list, count)) { 693 printf("%s: Error processing T30 mmc node(s)!\n", __func__); 694 return; 695 } 696 697 /* Now look for any Tegra20 MMC controllers */ 698 count = fdtdec_find_aliases_for_id(blob, "sdhci", 699 COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, 700 CONFIG_SYS_MMC_MAX_DEVICE); 701 debug("%s: count of T20 sdhci nodes is %d\n", __func__, count); 702 if (process_nodes(blob, node_list, count)) { 703 printf("%s: Error processing T20 mmc node(s)!\n", __func__); 704 return; 705 } 706 } 707