1 /* 2 * (C) Copyright 2009 SAMSUNG Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 * Portions Copyright 2011-2016 NVIDIA Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <bouncebuf.h> 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <mmc.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <asm/arch-tegra/tegra_mmc.h> 18 19 struct tegra_mmc_plat { 20 struct mmc_config cfg; 21 struct mmc mmc; 22 }; 23 24 struct tegra_mmc_priv { 25 struct tegra_mmc *reg; 26 struct reset_ctl reset_ctl; 27 struct clk clk; 28 struct gpio_desc cd_gpio; /* Change Detect GPIO */ 29 struct gpio_desc pwr_gpio; /* Power GPIO */ 30 struct gpio_desc wp_gpio; /* Write Protect GPIO */ 31 unsigned int version; /* SDHCI spec. version */ 32 unsigned int clock; /* Current clock (MHz) */ 33 }; 34 35 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv, 36 unsigned short power) 37 { 38 u8 pwr = 0; 39 debug("%s: power = %x\n", __func__, power); 40 41 if (power != (unsigned short)-1) { 42 switch (1 << power) { 43 case MMC_VDD_165_195: 44 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; 45 break; 46 case MMC_VDD_29_30: 47 case MMC_VDD_30_31: 48 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; 49 break; 50 case MMC_VDD_32_33: 51 case MMC_VDD_33_34: 52 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; 53 break; 54 } 55 } 56 debug("%s: pwr = %X\n", __func__, pwr); 57 58 /* Set the bus voltage first (if any) */ 59 writeb(pwr, &priv->reg->pwrcon); 60 if (pwr == 0) 61 return; 62 63 /* Now enable bus power */ 64 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER; 65 writeb(pwr, &priv->reg->pwrcon); 66 } 67 68 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv, 69 struct mmc_data *data, 70 struct bounce_buffer *bbstate) 71 { 72 unsigned char ctrl; 73 74 75 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", 76 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, 77 data->blocksize); 78 79 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad); 80 /* 81 * DMASEL[4:3] 82 * 00 = Selects SDMA 83 * 01 = Reserved 84 * 10 = Selects 32-bit Address ADMA2 85 * 11 = Selects 64-bit Address ADMA2 86 */ 87 ctrl = readb(&priv->reg->hostctl); 88 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; 89 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; 90 writeb(ctrl, &priv->reg->hostctl); 91 92 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 93 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize); 94 writew(data->blocks, &priv->reg->blkcnt); 95 } 96 97 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv, 98 struct mmc_data *data) 99 { 100 unsigned short mode; 101 debug(" mmc_set_transfer_mode called\n"); 102 /* 103 * TRNMOD 104 * MUL1SIN0[5] : Multi/Single Block Select 105 * RD1WT0[4] : Data Transfer Direction Select 106 * 1 = read 107 * 0 = write 108 * ENACMD12[2] : Auto CMD12 Enable 109 * ENBLKCNT[1] : Block Count Enable 110 * ENDMA[0] : DMA Enable 111 */ 112 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | 113 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); 114 115 if (data->blocks > 1) 116 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; 117 118 if (data->flags & MMC_DATA_READ) 119 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; 120 121 writew(mode, &priv->reg->trnmod); 122 } 123 124 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv, 125 struct mmc_cmd *cmd, 126 struct mmc_data *data, 127 unsigned int timeout) 128 { 129 /* 130 * PRNSTS 131 * CMDINHDAT[1] : Command Inhibit (DAT) 132 * CMDINHCMD[0] : Command Inhibit (CMD) 133 */ 134 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; 135 136 /* 137 * We shouldn't wait for data inhibit for stop commands, even 138 * though they might use busy signaling 139 */ 140 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) 141 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; 142 143 while (readl(&priv->reg->prnsts) & mask) { 144 if (timeout == 0) { 145 printf("%s: timeout error\n", __func__); 146 return -1; 147 } 148 timeout--; 149 udelay(1000); 150 } 151 152 return 0; 153 } 154 155 static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd, 156 struct mmc_data *data, 157 struct bounce_buffer *bbstate) 158 { 159 struct tegra_mmc_priv *priv = dev_get_priv(dev); 160 int flags, i; 161 int result; 162 unsigned int mask = 0; 163 unsigned int retry = 0x100000; 164 debug(" mmc_send_cmd called\n"); 165 166 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */); 167 168 if (result < 0) 169 return result; 170 171 if (data) 172 tegra_mmc_prepare_data(priv, data, bbstate); 173 174 debug("cmd->arg: %08x\n", cmd->cmdarg); 175 writel(cmd->cmdarg, &priv->reg->argument); 176 177 if (data) 178 tegra_mmc_set_transfer_mode(priv, data); 179 180 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 181 return -1; 182 183 /* 184 * CMDREG 185 * CMDIDX[13:8] : Command index 186 * DATAPRNT[5] : Data Present Select 187 * ENCMDIDX[4] : Command Index Check Enable 188 * ENCMDCRC[3] : Command CRC Check Enable 189 * RSPTYP[1:0] 190 * 00 = No Response 191 * 01 = Length 136 192 * 10 = Length 48 193 * 11 = Length 48 Check busy after response 194 */ 195 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 196 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; 197 else if (cmd->resp_type & MMC_RSP_136) 198 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; 199 else if (cmd->resp_type & MMC_RSP_BUSY) 200 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; 201 else 202 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; 203 204 if (cmd->resp_type & MMC_RSP_CRC) 205 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; 206 if (cmd->resp_type & MMC_RSP_OPCODE) 207 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; 208 if (data) 209 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; 210 211 debug("cmd: %d\n", cmd->cmdidx); 212 213 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg); 214 215 for (i = 0; i < retry; i++) { 216 mask = readl(&priv->reg->norintsts); 217 /* Command Complete */ 218 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { 219 if (!data) 220 writel(mask, &priv->reg->norintsts); 221 break; 222 } 223 } 224 225 if (i == retry) { 226 printf("%s: waiting for status update\n", __func__); 227 writel(mask, &priv->reg->norintsts); 228 return -ETIMEDOUT; 229 } 230 231 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { 232 /* Timeout Error */ 233 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); 234 writel(mask, &priv->reg->norintsts); 235 return -ETIMEDOUT; 236 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 237 /* Error Interrupt */ 238 debug("error: %08x cmd %d\n", mask, cmd->cmdidx); 239 writel(mask, &priv->reg->norintsts); 240 return -1; 241 } 242 243 if (cmd->resp_type & MMC_RSP_PRESENT) { 244 if (cmd->resp_type & MMC_RSP_136) { 245 /* CRC is stripped so we need to do some shifting. */ 246 for (i = 0; i < 4; i++) { 247 unsigned long offset = (unsigned long) 248 (&priv->reg->rspreg3 - i); 249 cmd->response[i] = readl(offset) << 8; 250 251 if (i != 3) { 252 cmd->response[i] |= 253 readb(offset - 1); 254 } 255 debug("cmd->resp[%d]: %08x\n", 256 i, cmd->response[i]); 257 } 258 } else if (cmd->resp_type & MMC_RSP_BUSY) { 259 for (i = 0; i < retry; i++) { 260 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ 261 if (readl(&priv->reg->prnsts) 262 & (1 << 20)) /* DAT[0] */ 263 break; 264 } 265 266 if (i == retry) { 267 printf("%s: card is still busy\n", __func__); 268 writel(mask, &priv->reg->norintsts); 269 return -ETIMEDOUT; 270 } 271 272 cmd->response[0] = readl(&priv->reg->rspreg0); 273 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 274 } else { 275 cmd->response[0] = readl(&priv->reg->rspreg0); 276 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 277 } 278 } 279 280 if (data) { 281 unsigned long start = get_timer(0); 282 283 while (1) { 284 mask = readl(&priv->reg->norintsts); 285 286 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 287 /* Error Interrupt */ 288 writel(mask, &priv->reg->norintsts); 289 printf("%s: error during transfer: 0x%08x\n", 290 __func__, mask); 291 return -1; 292 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { 293 /* 294 * DMA Interrupt, restart the transfer where 295 * it was interrupted. 296 */ 297 unsigned int address = readl(&priv->reg->sysad); 298 299 debug("DMA end\n"); 300 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, 301 &priv->reg->norintsts); 302 writel(address, &priv->reg->sysad); 303 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { 304 /* Transfer Complete */ 305 debug("r/w is done\n"); 306 break; 307 } else if (get_timer(start) > 8000UL) { 308 writel(mask, &priv->reg->norintsts); 309 printf("%s: MMC Timeout\n" 310 " Interrupt status 0x%08x\n" 311 " Interrupt status enable 0x%08x\n" 312 " Interrupt signal enable 0x%08x\n" 313 " Present status 0x%08x\n", 314 __func__, mask, 315 readl(&priv->reg->norintstsen), 316 readl(&priv->reg->norintsigen), 317 readl(&priv->reg->prnsts)); 318 return -1; 319 } 320 } 321 writel(mask, &priv->reg->norintsts); 322 } 323 324 udelay(1000); 325 return 0; 326 } 327 328 static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 329 struct mmc_data *data) 330 { 331 void *buf; 332 unsigned int bbflags; 333 size_t len; 334 struct bounce_buffer bbstate; 335 int ret; 336 337 if (data) { 338 if (data->flags & MMC_DATA_READ) { 339 buf = data->dest; 340 bbflags = GEN_BB_WRITE; 341 } else { 342 buf = (void *)data->src; 343 bbflags = GEN_BB_READ; 344 } 345 len = data->blocks * data->blocksize; 346 347 bounce_buffer_start(&bbstate, buf, len, bbflags); 348 } 349 350 ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate); 351 352 if (data) 353 bounce_buffer_stop(&bbstate); 354 355 return ret; 356 } 357 358 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock) 359 { 360 ulong rate; 361 int div; 362 unsigned short clk; 363 unsigned long timeout; 364 365 debug(" mmc_change_clock called\n"); 366 367 /* 368 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0 369 */ 370 if (clock == 0) 371 goto out; 372 373 rate = clk_set_rate(&priv->clk, clock); 374 div = (rate + clock - 1) / clock; 375 debug("div = %d\n", div); 376 377 writew(0, &priv->reg->clkcon); 378 379 /* 380 * CLKCON 381 * SELFREQ[15:8] : base clock divided by value 382 * ENSDCLK[2] : SD Clock Enable 383 * STBLINTCLK[1] : Internal Clock Stable 384 * ENINTCLK[0] : Internal Clock Enable 385 */ 386 div >>= 1; 387 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | 388 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); 389 writew(clk, &priv->reg->clkcon); 390 391 /* Wait max 10 ms */ 392 timeout = 10; 393 while (!(readw(&priv->reg->clkcon) & 394 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { 395 if (timeout == 0) { 396 printf("%s: timeout error\n", __func__); 397 return; 398 } 399 timeout--; 400 udelay(1000); 401 } 402 403 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 404 writew(clk, &priv->reg->clkcon); 405 406 debug("mmc_change_clock: clkcon = %08X\n", clk); 407 408 out: 409 priv->clock = clock; 410 } 411 412 static int tegra_mmc_set_ios(struct udevice *dev) 413 { 414 struct tegra_mmc_priv *priv = dev_get_priv(dev); 415 struct mmc *mmc = mmc_get_mmc_dev(dev); 416 unsigned char ctrl; 417 debug(" mmc_set_ios called\n"); 418 419 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); 420 421 /* Change clock first */ 422 tegra_mmc_change_clock(priv, mmc->clock); 423 424 ctrl = readb(&priv->reg->hostctl); 425 426 /* 427 * WIDE8[5] 428 * 0 = Depend on WIDE4 429 * 1 = 8-bit mode 430 * WIDE4[1] 431 * 1 = 4-bit mode 432 * 0 = 1-bit mode 433 */ 434 if (mmc->bus_width == 8) 435 ctrl |= (1 << 5); 436 else if (mmc->bus_width == 4) 437 ctrl |= (1 << 1); 438 else 439 ctrl &= ~(1 << 1 | 1 << 5); 440 441 writeb(ctrl, &priv->reg->hostctl); 442 debug("mmc_set_ios: hostctl = %08X\n", ctrl); 443 444 return 0; 445 } 446 447 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) 448 { 449 #if defined(CONFIG_TEGRA30) 450 u32 val; 451 452 debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg); 453 454 /* Set the pad drive strength for SDMMC1 or 3 only */ 455 if (priv->reg != (void *)0x78000000 && 456 priv->reg != (void *)0x78000400) { 457 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 458 __func__); 459 return; 460 } 461 462 val = readl(&priv->reg->sdmemcmppadctl); 463 val &= 0xFFFFFFF0; 464 val |= MEMCOMP_PADCTRL_VREF; 465 writel(val, &priv->reg->sdmemcmppadctl); 466 467 val = readl(&priv->reg->autocalcfg); 468 val &= 0xFFFF0000; 469 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 470 writel(val, &priv->reg->autocalcfg); 471 #endif 472 } 473 474 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc) 475 { 476 unsigned int timeout; 477 debug(" mmc_reset called\n"); 478 479 /* 480 * RSTALL[0] : Software reset for all 481 * 1 = reset 482 * 0 = work 483 */ 484 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst); 485 486 priv->clock = 0; 487 488 /* Wait max 100 ms */ 489 timeout = 100; 490 491 /* hw clears the bit when it's done */ 492 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { 493 if (timeout == 0) { 494 printf("%s: timeout error\n", __func__); 495 return; 496 } 497 timeout--; 498 udelay(1000); 499 } 500 501 /* Set SD bus voltage & enable bus power */ 502 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1); 503 debug("%s: power control = %02X, host control = %02X\n", __func__, 504 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl)); 505 506 /* Make sure SDIO pads are set up */ 507 tegra_mmc_pad_init(priv); 508 } 509 510 static int tegra_mmc_init(struct udevice *dev) 511 { 512 struct tegra_mmc_priv *priv = dev_get_priv(dev); 513 struct mmc *mmc = mmc_get_mmc_dev(dev); 514 unsigned int mask; 515 debug(" tegra_mmc_init called\n"); 516 517 tegra_mmc_reset(priv, mmc); 518 519 #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK) 520 /* 521 * Disable the external clock loopback and use the internal one on 522 * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 523 * bits being set to 0xfffd according to the TRM. 524 * 525 * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled 526 * approach once proper kernel integration made it mainline. 527 */ 528 if (priv->reg == (void *)0x700b0400) { 529 mask = readl(&priv->reg->venmiscctl); 530 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK; 531 writel(mask, &priv->reg->venmiscctl); 532 } 533 #endif 534 535 priv->version = readw(&priv->reg->hcver); 536 debug("host version = %x\n", priv->version); 537 538 /* mask all */ 539 writel(0xffffffff, &priv->reg->norintstsen); 540 writel(0xffffffff, &priv->reg->norintsigen); 541 542 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */ 543 /* 544 * NORMAL Interrupt Status Enable Register init 545 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable 546 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable 547 * [3] ENSTADMAINT : DMA boundary interrupt 548 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable 549 * [0] ENSTACMDCMPLT : Command Complete Status Enable 550 */ 551 mask = readl(&priv->reg->norintstsen); 552 mask &= ~(0xffff); 553 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | 554 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | 555 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | 556 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | 557 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); 558 writel(mask, &priv->reg->norintstsen); 559 560 /* 561 * NORMAL Interrupt Signal Enable Register init 562 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable 563 */ 564 mask = readl(&priv->reg->norintsigen); 565 mask &= ~(0xffff); 566 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; 567 writel(mask, &priv->reg->norintsigen); 568 569 return 0; 570 } 571 572 static int tegra_mmc_getcd(struct udevice *dev) 573 { 574 struct tegra_mmc_priv *priv = dev_get_priv(dev); 575 576 debug("tegra_mmc_getcd called\n"); 577 578 if (dm_gpio_is_valid(&priv->cd_gpio)) 579 return dm_gpio_get_value(&priv->cd_gpio); 580 581 return 1; 582 } 583 584 static const struct dm_mmc_ops tegra_mmc_ops = { 585 .send_cmd = tegra_mmc_send_cmd, 586 .set_ios = tegra_mmc_set_ios, 587 .get_cd = tegra_mmc_getcd, 588 }; 589 590 static int tegra_mmc_probe(struct udevice *dev) 591 { 592 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 593 struct tegra_mmc_plat *plat = dev_get_platdata(dev); 594 struct tegra_mmc_priv *priv = dev_get_priv(dev); 595 struct mmc_config *cfg = &plat->cfg; 596 int bus_width, ret; 597 598 cfg->name = dev->name; 599 600 bus_width = dev_read_u32_default(dev, "bus-width", 1); 601 602 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 603 cfg->host_caps = 0; 604 if (bus_width == 8) 605 cfg->host_caps |= MMC_MODE_8BIT; 606 if (bus_width >= 4) 607 cfg->host_caps |= MMC_MODE_4BIT; 608 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 609 610 /* 611 * min freq is for card identification, and is the highest 612 * low-speed SDIO card frequency (actually 400KHz) 613 * max freq is highest HS eMMC clock as per the SD/MMC spec 614 * (actually 52MHz) 615 */ 616 cfg->f_min = 375000; 617 cfg->f_max = 48000000; 618 619 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 620 621 priv->reg = (void *)dev_read_addr(dev); 622 623 ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl); 624 if (ret) { 625 debug("reset_get_by_name() failed: %d\n", ret); 626 return ret; 627 } 628 ret = clk_get_by_index(dev, 0, &priv->clk); 629 if (ret) { 630 debug("clk_get_by_index() failed: %d\n", ret); 631 return ret; 632 } 633 634 ret = reset_assert(&priv->reset_ctl); 635 if (ret) 636 return ret; 637 ret = clk_enable(&priv->clk); 638 if (ret) 639 return ret; 640 ret = clk_set_rate(&priv->clk, 20000000); 641 if (IS_ERR_VALUE(ret)) 642 return ret; 643 ret = reset_deassert(&priv->reset_ctl); 644 if (ret) 645 return ret; 646 647 /* These GPIOs are optional */ 648 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); 649 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); 650 gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio, 651 GPIOD_IS_OUT); 652 if (dm_gpio_is_valid(&priv->pwr_gpio)) 653 dm_gpio_set_value(&priv->pwr_gpio, 1); 654 655 upriv->mmc = &plat->mmc; 656 657 return tegra_mmc_init(dev); 658 } 659 660 static int tegra_mmc_bind(struct udevice *dev) 661 { 662 struct tegra_mmc_plat *plat = dev_get_platdata(dev); 663 664 return mmc_bind(dev, &plat->mmc, &plat->cfg); 665 } 666 667 static const struct udevice_id tegra_mmc_ids[] = { 668 { .compatible = "nvidia,tegra20-sdhci" }, 669 { .compatible = "nvidia,tegra30-sdhci" }, 670 { .compatible = "nvidia,tegra114-sdhci" }, 671 { .compatible = "nvidia,tegra124-sdhci" }, 672 { .compatible = "nvidia,tegra210-sdhci" }, 673 { .compatible = "nvidia,tegra186-sdhci" }, 674 { } 675 }; 676 677 U_BOOT_DRIVER(tegra_mmc_drv) = { 678 .name = "tegra_mmc", 679 .id = UCLASS_MMC, 680 .of_match = tegra_mmc_ids, 681 .bind = tegra_mmc_bind, 682 .probe = tegra_mmc_probe, 683 .ops = &tegra_mmc_ops, 684 .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat), 685 .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv), 686 }; 687