1 /* 2 * (C) Copyright 2009 SAMSUNG Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 * Portions Copyright 2011-2013 NVIDIA Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #include <bouncebuf.h> 23 #include <common.h> 24 #include <asm/gpio.h> 25 #include <asm/io.h> 26 #include <asm/arch/clock.h> 27 #include <asm/arch-tegra/clk_rst.h> 28 #include <asm/arch-tegra/tegra_mmc.h> 29 #include <mmc.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 struct mmc mmc_dev[MAX_HOSTS]; 34 struct mmc_host mmc_host[MAX_HOSTS]; 35 36 #ifndef CONFIG_OF_CONTROL 37 #error "Please enable device tree support to use this driver" 38 #endif 39 40 static void mmc_set_power(struct mmc_host *host, unsigned short power) 41 { 42 u8 pwr = 0; 43 debug("%s: power = %x\n", __func__, power); 44 45 if (power != (unsigned short)-1) { 46 switch (1 << power) { 47 case MMC_VDD_165_195: 48 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; 49 break; 50 case MMC_VDD_29_30: 51 case MMC_VDD_30_31: 52 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; 53 break; 54 case MMC_VDD_32_33: 55 case MMC_VDD_33_34: 56 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; 57 break; 58 } 59 } 60 debug("%s: pwr = %X\n", __func__, pwr); 61 62 /* Set the bus voltage first (if any) */ 63 writeb(pwr, &host->reg->pwrcon); 64 if (pwr == 0) 65 return; 66 67 /* Now enable bus power */ 68 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER; 69 writeb(pwr, &host->reg->pwrcon); 70 } 71 72 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data, 73 struct bounce_buffer *bbstate) 74 { 75 unsigned char ctrl; 76 77 78 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", 79 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, 80 data->blocksize); 81 82 writel((u32)bbstate->bounce_buffer, &host->reg->sysad); 83 /* 84 * DMASEL[4:3] 85 * 00 = Selects SDMA 86 * 01 = Reserved 87 * 10 = Selects 32-bit Address ADMA2 88 * 11 = Selects 64-bit Address ADMA2 89 */ 90 ctrl = readb(&host->reg->hostctl); 91 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; 92 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; 93 writeb(ctrl, &host->reg->hostctl); 94 95 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 96 writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize); 97 writew(data->blocks, &host->reg->blkcnt); 98 } 99 100 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data) 101 { 102 unsigned short mode; 103 debug(" mmc_set_transfer_mode called\n"); 104 /* 105 * TRNMOD 106 * MUL1SIN0[5] : Multi/Single Block Select 107 * RD1WT0[4] : Data Transfer Direction Select 108 * 1 = read 109 * 0 = write 110 * ENACMD12[2] : Auto CMD12 Enable 111 * ENBLKCNT[1] : Block Count Enable 112 * ENDMA[0] : DMA Enable 113 */ 114 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | 115 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); 116 117 if (data->blocks > 1) 118 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; 119 120 if (data->flags & MMC_DATA_READ) 121 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; 122 123 writew(mode, &host->reg->trnmod); 124 } 125 126 static int mmc_wait_inhibit(struct mmc_host *host, 127 struct mmc_cmd *cmd, 128 struct mmc_data *data, 129 unsigned int timeout) 130 { 131 /* 132 * PRNSTS 133 * CMDINHDAT[1] : Command Inhibit (DAT) 134 * CMDINHCMD[0] : Command Inhibit (CMD) 135 */ 136 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; 137 138 /* 139 * We shouldn't wait for data inhibit for stop commands, even 140 * though they might use busy signaling 141 */ 142 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) 143 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; 144 145 while (readl(&host->reg->prnsts) & mask) { 146 if (timeout == 0) { 147 printf("%s: timeout error\n", __func__); 148 return -1; 149 } 150 timeout--; 151 udelay(1000); 152 } 153 154 return 0; 155 } 156 157 static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, 158 struct mmc_data *data, struct bounce_buffer *bbstate) 159 { 160 struct mmc_host *host = (struct mmc_host *)mmc->priv; 161 int flags, i; 162 int result; 163 unsigned int mask = 0; 164 unsigned int retry = 0x100000; 165 debug(" mmc_send_cmd called\n"); 166 167 result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */); 168 169 if (result < 0) 170 return result; 171 172 if (data) 173 mmc_prepare_data(host, data, bbstate); 174 175 debug("cmd->arg: %08x\n", cmd->cmdarg); 176 writel(cmd->cmdarg, &host->reg->argument); 177 178 if (data) 179 mmc_set_transfer_mode(host, data); 180 181 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 182 return -1; 183 184 /* 185 * CMDREG 186 * CMDIDX[13:8] : Command index 187 * DATAPRNT[5] : Data Present Select 188 * ENCMDIDX[4] : Command Index Check Enable 189 * ENCMDCRC[3] : Command CRC Check Enable 190 * RSPTYP[1:0] 191 * 00 = No Response 192 * 01 = Length 136 193 * 10 = Length 48 194 * 11 = Length 48 Check busy after response 195 */ 196 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 197 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; 198 else if (cmd->resp_type & MMC_RSP_136) 199 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; 200 else if (cmd->resp_type & MMC_RSP_BUSY) 201 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; 202 else 203 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; 204 205 if (cmd->resp_type & MMC_RSP_CRC) 206 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; 207 if (cmd->resp_type & MMC_RSP_OPCODE) 208 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; 209 if (data) 210 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; 211 212 debug("cmd: %d\n", cmd->cmdidx); 213 214 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); 215 216 for (i = 0; i < retry; i++) { 217 mask = readl(&host->reg->norintsts); 218 /* Command Complete */ 219 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { 220 if (!data) 221 writel(mask, &host->reg->norintsts); 222 break; 223 } 224 } 225 226 if (i == retry) { 227 printf("%s: waiting for status update\n", __func__); 228 writel(mask, &host->reg->norintsts); 229 return TIMEOUT; 230 } 231 232 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { 233 /* Timeout Error */ 234 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); 235 writel(mask, &host->reg->norintsts); 236 return TIMEOUT; 237 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 238 /* Error Interrupt */ 239 debug("error: %08x cmd %d\n", mask, cmd->cmdidx); 240 writel(mask, &host->reg->norintsts); 241 return -1; 242 } 243 244 if (cmd->resp_type & MMC_RSP_PRESENT) { 245 if (cmd->resp_type & MMC_RSP_136) { 246 /* CRC is stripped so we need to do some shifting. */ 247 for (i = 0; i < 4; i++) { 248 unsigned int offset = 249 (unsigned int)(&host->reg->rspreg3 - i); 250 cmd->response[i] = readl(offset) << 8; 251 252 if (i != 3) { 253 cmd->response[i] |= 254 readb(offset - 1); 255 } 256 debug("cmd->resp[%d]: %08x\n", 257 i, cmd->response[i]); 258 } 259 } else if (cmd->resp_type & MMC_RSP_BUSY) { 260 for (i = 0; i < retry; i++) { 261 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ 262 if (readl(&host->reg->prnsts) 263 & (1 << 20)) /* DAT[0] */ 264 break; 265 } 266 267 if (i == retry) { 268 printf("%s: card is still busy\n", __func__); 269 writel(mask, &host->reg->norintsts); 270 return TIMEOUT; 271 } 272 273 cmd->response[0] = readl(&host->reg->rspreg0); 274 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 275 } else { 276 cmd->response[0] = readl(&host->reg->rspreg0); 277 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 278 } 279 } 280 281 if (data) { 282 unsigned long start = get_timer(0); 283 284 while (1) { 285 mask = readl(&host->reg->norintsts); 286 287 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 288 /* Error Interrupt */ 289 writel(mask, &host->reg->norintsts); 290 printf("%s: error during transfer: 0x%08x\n", 291 __func__, mask); 292 return -1; 293 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { 294 /* 295 * DMA Interrupt, restart the transfer where 296 * it was interrupted. 297 */ 298 unsigned int address = readl(&host->reg->sysad); 299 300 debug("DMA end\n"); 301 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, 302 &host->reg->norintsts); 303 writel(address, &host->reg->sysad); 304 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { 305 /* Transfer Complete */ 306 debug("r/w is done\n"); 307 break; 308 } else if (get_timer(start) > 2000UL) { 309 writel(mask, &host->reg->norintsts); 310 printf("%s: MMC Timeout\n" 311 " Interrupt status 0x%08x\n" 312 " Interrupt status enable 0x%08x\n" 313 " Interrupt signal enable 0x%08x\n" 314 " Present status 0x%08x\n", 315 __func__, mask, 316 readl(&host->reg->norintstsen), 317 readl(&host->reg->norintsigen), 318 readl(&host->reg->prnsts)); 319 return -1; 320 } 321 } 322 writel(mask, &host->reg->norintsts); 323 } 324 325 udelay(1000); 326 return 0; 327 } 328 329 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 330 struct mmc_data *data) 331 { 332 void *buf; 333 unsigned int bbflags; 334 size_t len; 335 struct bounce_buffer bbstate; 336 int ret; 337 338 if (data) { 339 if (data->flags & MMC_DATA_READ) { 340 buf = data->dest; 341 bbflags = GEN_BB_WRITE; 342 } else { 343 buf = (void *)data->src; 344 bbflags = GEN_BB_READ; 345 } 346 len = data->blocks * data->blocksize; 347 348 bounce_buffer_start(&bbstate, buf, len, bbflags); 349 } 350 351 ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate); 352 353 if (data) 354 bounce_buffer_stop(&bbstate); 355 356 return ret; 357 } 358 359 static void mmc_change_clock(struct mmc_host *host, uint clock) 360 { 361 int div; 362 unsigned short clk; 363 unsigned long timeout; 364 365 debug(" mmc_change_clock called\n"); 366 367 /* 368 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0 369 */ 370 if (clock == 0) 371 goto out; 372 clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock, 373 &div); 374 debug("div = %d\n", div); 375 376 writew(0, &host->reg->clkcon); 377 378 /* 379 * CLKCON 380 * SELFREQ[15:8] : base clock divided by value 381 * ENSDCLK[2] : SD Clock Enable 382 * STBLINTCLK[1] : Internal Clock Stable 383 * ENINTCLK[0] : Internal Clock Enable 384 */ 385 div >>= 1; 386 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | 387 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); 388 writew(clk, &host->reg->clkcon); 389 390 /* Wait max 10 ms */ 391 timeout = 10; 392 while (!(readw(&host->reg->clkcon) & 393 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { 394 if (timeout == 0) { 395 printf("%s: timeout error\n", __func__); 396 return; 397 } 398 timeout--; 399 udelay(1000); 400 } 401 402 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 403 writew(clk, &host->reg->clkcon); 404 405 debug("mmc_change_clock: clkcon = %08X\n", clk); 406 407 out: 408 host->clock = clock; 409 } 410 411 static void mmc_set_ios(struct mmc *mmc) 412 { 413 struct mmc_host *host = mmc->priv; 414 unsigned char ctrl; 415 debug(" mmc_set_ios called\n"); 416 417 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); 418 419 /* Change clock first */ 420 mmc_change_clock(host, mmc->clock); 421 422 ctrl = readb(&host->reg->hostctl); 423 424 /* 425 * WIDE8[5] 426 * 0 = Depend on WIDE4 427 * 1 = 8-bit mode 428 * WIDE4[1] 429 * 1 = 4-bit mode 430 * 0 = 1-bit mode 431 */ 432 if (mmc->bus_width == 8) 433 ctrl |= (1 << 5); 434 else if (mmc->bus_width == 4) 435 ctrl |= (1 << 1); 436 else 437 ctrl &= ~(1 << 1); 438 439 writeb(ctrl, &host->reg->hostctl); 440 debug("mmc_set_ios: hostctl = %08X\n", ctrl); 441 } 442 443 static void mmc_reset(struct mmc_host *host, struct mmc *mmc) 444 { 445 unsigned int timeout; 446 debug(" mmc_reset called\n"); 447 448 /* 449 * RSTALL[0] : Software reset for all 450 * 1 = reset 451 * 0 = work 452 */ 453 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst); 454 455 host->clock = 0; 456 457 /* Wait max 100 ms */ 458 timeout = 100; 459 460 /* hw clears the bit when it's done */ 461 while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { 462 if (timeout == 0) { 463 printf("%s: timeout error\n", __func__); 464 return; 465 } 466 timeout--; 467 udelay(1000); 468 } 469 470 /* Set SD bus voltage & enable bus power */ 471 mmc_set_power(host, fls(mmc->voltages) - 1); 472 debug("%s: power control = %02X, host control = %02X\n", __func__, 473 readb(&host->reg->pwrcon), readb(&host->reg->hostctl)); 474 475 /* Make sure SDIO pads are set up */ 476 pad_init_mmc(host); 477 } 478 479 static int mmc_core_init(struct mmc *mmc) 480 { 481 struct mmc_host *host = (struct mmc_host *)mmc->priv; 482 unsigned int mask; 483 debug(" mmc_core_init called\n"); 484 485 mmc_reset(host, mmc); 486 487 host->version = readw(&host->reg->hcver); 488 debug("host version = %x\n", host->version); 489 490 /* mask all */ 491 writel(0xffffffff, &host->reg->norintstsen); 492 writel(0xffffffff, &host->reg->norintsigen); 493 494 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */ 495 /* 496 * NORMAL Interrupt Status Enable Register init 497 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable 498 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable 499 * [3] ENSTADMAINT : DMA boundary interrupt 500 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable 501 * [0] ENSTACMDCMPLT : Command Complete Status Enable 502 */ 503 mask = readl(&host->reg->norintstsen); 504 mask &= ~(0xffff); 505 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | 506 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | 507 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | 508 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | 509 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); 510 writel(mask, &host->reg->norintstsen); 511 512 /* 513 * NORMAL Interrupt Signal Enable Register init 514 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable 515 */ 516 mask = readl(&host->reg->norintsigen); 517 mask &= ~(0xffff); 518 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; 519 writel(mask, &host->reg->norintsigen); 520 521 return 0; 522 } 523 524 int tegra_mmc_getcd(struct mmc *mmc) 525 { 526 struct mmc_host *host = (struct mmc_host *)mmc->priv; 527 528 debug("tegra_mmc_getcd called\n"); 529 530 if (fdt_gpio_isvalid(&host->cd_gpio)) 531 return fdtdec_get_gpio(&host->cd_gpio); 532 533 return 1; 534 } 535 536 static int do_mmc_init(int dev_index) 537 { 538 struct mmc_host *host; 539 char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */ 540 struct mmc *mmc; 541 542 /* DT should have been read & host config filled in */ 543 host = &mmc_host[dev_index]; 544 if (!host->enabled) 545 return -1; 546 547 debug(" do_mmc_init: index %d, bus width %d " 548 "pwr_gpio %d cd_gpio %d\n", 549 dev_index, host->width, 550 host->pwr_gpio.gpio, host->cd_gpio.gpio); 551 552 host->clock = 0; 553 clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); 554 555 if (fdt_gpio_isvalid(&host->pwr_gpio)) { 556 sprintf(gpusage, "SD/MMC%d PWR", dev_index); 557 gpio_request(host->pwr_gpio.gpio, gpusage); 558 gpio_direction_output(host->pwr_gpio.gpio, 1); 559 debug(" Power GPIO name = %s\n", host->pwr_gpio.name); 560 } 561 562 if (fdt_gpio_isvalid(&host->cd_gpio)) { 563 sprintf(gpusage, "SD/MMC%d CD", dev_index); 564 gpio_request(host->cd_gpio.gpio, gpusage); 565 gpio_direction_input(host->cd_gpio.gpio); 566 debug(" CD GPIO name = %s\n", host->cd_gpio.name); 567 } 568 569 mmc = &mmc_dev[dev_index]; 570 571 sprintf(mmc->name, "Tegra SD/MMC"); 572 mmc->priv = host; 573 mmc->send_cmd = mmc_send_cmd; 574 mmc->set_ios = mmc_set_ios; 575 mmc->init = mmc_core_init; 576 mmc->getcd = tegra_mmc_getcd; 577 mmc->getwp = NULL; 578 579 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 580 mmc->host_caps = 0; 581 if (host->width == 8) 582 mmc->host_caps |= MMC_MODE_8BIT; 583 if (host->width >= 4) 584 mmc->host_caps |= MMC_MODE_4BIT; 585 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; 586 587 /* 588 * min freq is for card identification, and is the highest 589 * low-speed SDIO card frequency (actually 400KHz) 590 * max freq is highest HS eMMC clock as per the SD/MMC spec 591 * (actually 52MHz) 592 */ 593 mmc->f_min = 375000; 594 mmc->f_max = 48000000; 595 596 mmc_register(mmc); 597 598 return 0; 599 } 600 601 /** 602 * Get the host address and peripheral ID for a node. 603 * 604 * @param blob fdt blob 605 * @param node Device index (0-3) 606 * @param host Structure to fill in (reg, width, mmc_id) 607 */ 608 static int mmc_get_config(const void *blob, int node, struct mmc_host *host) 609 { 610 debug("%s: node = %d\n", __func__, node); 611 612 host->enabled = fdtdec_get_is_enabled(blob, node); 613 614 host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg"); 615 if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) { 616 debug("%s: no sdmmc base reg info found\n", __func__); 617 return -FDT_ERR_NOTFOUND; 618 } 619 620 host->mmc_id = clock_decode_periph_id(blob, node); 621 if (host->mmc_id == PERIPH_ID_NONE) { 622 debug("%s: could not decode periph id\n", __func__); 623 return -FDT_ERR_NOTFOUND; 624 } 625 626 /* 627 * NOTE: mmc->bus_width is determined by mmc.c dynamically. 628 * TBD: Override it with this value? 629 */ 630 host->width = fdtdec_get_int(blob, node, "bus-width", 0); 631 if (!host->width) 632 debug("%s: no sdmmc width found\n", __func__); 633 634 /* These GPIOs are optional */ 635 fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio); 636 fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio); 637 fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio); 638 639 debug("%s: found controller at %p, width = %d, periph_id = %d\n", 640 __func__, host->reg, host->width, host->mmc_id); 641 return 0; 642 } 643 644 /* 645 * Process a list of nodes, adding them to our list of SDMMC ports. 646 * 647 * @param blob fdt blob 648 * @param node_list list of nodes to process (any <=0 are ignored) 649 * @param count number of nodes to process 650 * @return 0 if ok, -1 on error 651 */ 652 static int process_nodes(const void *blob, int node_list[], int count) 653 { 654 struct mmc_host *host; 655 int i, node; 656 657 debug("%s: count = %d\n", __func__, count); 658 659 /* build mmc_host[] for each controller */ 660 for (i = 0; i < count; i++) { 661 node = node_list[i]; 662 if (node <= 0) 663 continue; 664 665 host = &mmc_host[i]; 666 host->id = i; 667 668 if (mmc_get_config(blob, node, host)) { 669 printf("%s: failed to decode dev %d\n", __func__, i); 670 return -1; 671 } 672 do_mmc_init(i); 673 } 674 return 0; 675 } 676 677 void tegra_mmc_init(void) 678 { 679 int node_list[MAX_HOSTS], count; 680 const void *blob = gd->fdt_blob; 681 debug("%s entry\n", __func__); 682 683 /* See if any Tegra30 MMC controllers are present */ 684 count = fdtdec_find_aliases_for_id(blob, "sdhci", 685 COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS); 686 debug("%s: count of T30 sdhci nodes is %d\n", __func__, count); 687 if (process_nodes(blob, node_list, count)) { 688 printf("%s: Error processing T30 mmc node(s)!\n", __func__); 689 return; 690 } 691 692 /* Now look for any Tegra20 MMC controllers */ 693 count = fdtdec_find_aliases_for_id(blob, "sdhci", 694 COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS); 695 debug("%s: count of T20 sdhci nodes is %d\n", __func__, count); 696 if (process_nodes(blob, node_list, count)) { 697 printf("%s: Error processing T20 mmc node(s)!\n", __func__); 698 return; 699 } 700 } 701