1 /* 2 * (C) Copyright 2009 SAMSUNG Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 * Portions Copyright 2011-2016 NVIDIA Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <bouncebuf.h> 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <mmc.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <asm/arch-tegra/tegra_mmc.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 struct tegra_mmc_plat { 22 struct mmc_config cfg; 23 struct mmc mmc; 24 }; 25 26 struct tegra_mmc_priv { 27 struct tegra_mmc *reg; 28 struct reset_ctl reset_ctl; 29 struct clk clk; 30 struct gpio_desc cd_gpio; /* Change Detect GPIO */ 31 struct gpio_desc pwr_gpio; /* Power GPIO */ 32 struct gpio_desc wp_gpio; /* Write Protect GPIO */ 33 unsigned int version; /* SDHCI spec. version */ 34 unsigned int clock; /* Current clock (MHz) */ 35 }; 36 37 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv, 38 unsigned short power) 39 { 40 u8 pwr = 0; 41 debug("%s: power = %x\n", __func__, power); 42 43 if (power != (unsigned short)-1) { 44 switch (1 << power) { 45 case MMC_VDD_165_195: 46 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; 47 break; 48 case MMC_VDD_29_30: 49 case MMC_VDD_30_31: 50 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; 51 break; 52 case MMC_VDD_32_33: 53 case MMC_VDD_33_34: 54 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; 55 break; 56 } 57 } 58 debug("%s: pwr = %X\n", __func__, pwr); 59 60 /* Set the bus voltage first (if any) */ 61 writeb(pwr, &priv->reg->pwrcon); 62 if (pwr == 0) 63 return; 64 65 /* Now enable bus power */ 66 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER; 67 writeb(pwr, &priv->reg->pwrcon); 68 } 69 70 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv, 71 struct mmc_data *data, 72 struct bounce_buffer *bbstate) 73 { 74 unsigned char ctrl; 75 76 77 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", 78 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, 79 data->blocksize); 80 81 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad); 82 /* 83 * DMASEL[4:3] 84 * 00 = Selects SDMA 85 * 01 = Reserved 86 * 10 = Selects 32-bit Address ADMA2 87 * 11 = Selects 64-bit Address ADMA2 88 */ 89 ctrl = readb(&priv->reg->hostctl); 90 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; 91 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; 92 writeb(ctrl, &priv->reg->hostctl); 93 94 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 95 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize); 96 writew(data->blocks, &priv->reg->blkcnt); 97 } 98 99 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv, 100 struct mmc_data *data) 101 { 102 unsigned short mode; 103 debug(" mmc_set_transfer_mode called\n"); 104 /* 105 * TRNMOD 106 * MUL1SIN0[5] : Multi/Single Block Select 107 * RD1WT0[4] : Data Transfer Direction Select 108 * 1 = read 109 * 0 = write 110 * ENACMD12[2] : Auto CMD12 Enable 111 * ENBLKCNT[1] : Block Count Enable 112 * ENDMA[0] : DMA Enable 113 */ 114 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | 115 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); 116 117 if (data->blocks > 1) 118 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; 119 120 if (data->flags & MMC_DATA_READ) 121 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; 122 123 writew(mode, &priv->reg->trnmod); 124 } 125 126 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv, 127 struct mmc_cmd *cmd, 128 struct mmc_data *data, 129 unsigned int timeout) 130 { 131 /* 132 * PRNSTS 133 * CMDINHDAT[1] : Command Inhibit (DAT) 134 * CMDINHCMD[0] : Command Inhibit (CMD) 135 */ 136 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; 137 138 /* 139 * We shouldn't wait for data inhibit for stop commands, even 140 * though they might use busy signaling 141 */ 142 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) 143 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; 144 145 while (readl(&priv->reg->prnsts) & mask) { 146 if (timeout == 0) { 147 printf("%s: timeout error\n", __func__); 148 return -1; 149 } 150 timeout--; 151 udelay(1000); 152 } 153 154 return 0; 155 } 156 157 static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd, 158 struct mmc_data *data, 159 struct bounce_buffer *bbstate) 160 { 161 struct tegra_mmc_priv *priv = dev_get_priv(dev); 162 int flags, i; 163 int result; 164 unsigned int mask = 0; 165 unsigned int retry = 0x100000; 166 debug(" mmc_send_cmd called\n"); 167 168 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */); 169 170 if (result < 0) 171 return result; 172 173 if (data) 174 tegra_mmc_prepare_data(priv, data, bbstate); 175 176 debug("cmd->arg: %08x\n", cmd->cmdarg); 177 writel(cmd->cmdarg, &priv->reg->argument); 178 179 if (data) 180 tegra_mmc_set_transfer_mode(priv, data); 181 182 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 183 return -1; 184 185 /* 186 * CMDREG 187 * CMDIDX[13:8] : Command index 188 * DATAPRNT[5] : Data Present Select 189 * ENCMDIDX[4] : Command Index Check Enable 190 * ENCMDCRC[3] : Command CRC Check Enable 191 * RSPTYP[1:0] 192 * 00 = No Response 193 * 01 = Length 136 194 * 10 = Length 48 195 * 11 = Length 48 Check busy after response 196 */ 197 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 198 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; 199 else if (cmd->resp_type & MMC_RSP_136) 200 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; 201 else if (cmd->resp_type & MMC_RSP_BUSY) 202 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; 203 else 204 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; 205 206 if (cmd->resp_type & MMC_RSP_CRC) 207 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; 208 if (cmd->resp_type & MMC_RSP_OPCODE) 209 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; 210 if (data) 211 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; 212 213 debug("cmd: %d\n", cmd->cmdidx); 214 215 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg); 216 217 for (i = 0; i < retry; i++) { 218 mask = readl(&priv->reg->norintsts); 219 /* Command Complete */ 220 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { 221 if (!data) 222 writel(mask, &priv->reg->norintsts); 223 break; 224 } 225 } 226 227 if (i == retry) { 228 printf("%s: waiting for status update\n", __func__); 229 writel(mask, &priv->reg->norintsts); 230 return -ETIMEDOUT; 231 } 232 233 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { 234 /* Timeout Error */ 235 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); 236 writel(mask, &priv->reg->norintsts); 237 return -ETIMEDOUT; 238 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 239 /* Error Interrupt */ 240 debug("error: %08x cmd %d\n", mask, cmd->cmdidx); 241 writel(mask, &priv->reg->norintsts); 242 return -1; 243 } 244 245 if (cmd->resp_type & MMC_RSP_PRESENT) { 246 if (cmd->resp_type & MMC_RSP_136) { 247 /* CRC is stripped so we need to do some shifting. */ 248 for (i = 0; i < 4; i++) { 249 unsigned long offset = (unsigned long) 250 (&priv->reg->rspreg3 - i); 251 cmd->response[i] = readl(offset) << 8; 252 253 if (i != 3) { 254 cmd->response[i] |= 255 readb(offset - 1); 256 } 257 debug("cmd->resp[%d]: %08x\n", 258 i, cmd->response[i]); 259 } 260 } else if (cmd->resp_type & MMC_RSP_BUSY) { 261 for (i = 0; i < retry; i++) { 262 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ 263 if (readl(&priv->reg->prnsts) 264 & (1 << 20)) /* DAT[0] */ 265 break; 266 } 267 268 if (i == retry) { 269 printf("%s: card is still busy\n", __func__); 270 writel(mask, &priv->reg->norintsts); 271 return -ETIMEDOUT; 272 } 273 274 cmd->response[0] = readl(&priv->reg->rspreg0); 275 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 276 } else { 277 cmd->response[0] = readl(&priv->reg->rspreg0); 278 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 279 } 280 } 281 282 if (data) { 283 unsigned long start = get_timer(0); 284 285 while (1) { 286 mask = readl(&priv->reg->norintsts); 287 288 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 289 /* Error Interrupt */ 290 writel(mask, &priv->reg->norintsts); 291 printf("%s: error during transfer: 0x%08x\n", 292 __func__, mask); 293 return -1; 294 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { 295 /* 296 * DMA Interrupt, restart the transfer where 297 * it was interrupted. 298 */ 299 unsigned int address = readl(&priv->reg->sysad); 300 301 debug("DMA end\n"); 302 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, 303 &priv->reg->norintsts); 304 writel(address, &priv->reg->sysad); 305 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { 306 /* Transfer Complete */ 307 debug("r/w is done\n"); 308 break; 309 } else if (get_timer(start) > 8000UL) { 310 writel(mask, &priv->reg->norintsts); 311 printf("%s: MMC Timeout\n" 312 " Interrupt status 0x%08x\n" 313 " Interrupt status enable 0x%08x\n" 314 " Interrupt signal enable 0x%08x\n" 315 " Present status 0x%08x\n", 316 __func__, mask, 317 readl(&priv->reg->norintstsen), 318 readl(&priv->reg->norintsigen), 319 readl(&priv->reg->prnsts)); 320 return -1; 321 } 322 } 323 writel(mask, &priv->reg->norintsts); 324 } 325 326 udelay(1000); 327 return 0; 328 } 329 330 static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 331 struct mmc_data *data) 332 { 333 void *buf; 334 unsigned int bbflags; 335 size_t len; 336 struct bounce_buffer bbstate; 337 int ret; 338 339 if (data) { 340 if (data->flags & MMC_DATA_READ) { 341 buf = data->dest; 342 bbflags = GEN_BB_WRITE; 343 } else { 344 buf = (void *)data->src; 345 bbflags = GEN_BB_READ; 346 } 347 len = data->blocks * data->blocksize; 348 349 bounce_buffer_start(&bbstate, buf, len, bbflags); 350 } 351 352 ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate); 353 354 if (data) 355 bounce_buffer_stop(&bbstate); 356 357 return ret; 358 } 359 360 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock) 361 { 362 ulong rate; 363 int div; 364 unsigned short clk; 365 unsigned long timeout; 366 367 debug(" mmc_change_clock called\n"); 368 369 /* 370 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0 371 */ 372 if (clock == 0) 373 goto out; 374 375 rate = clk_set_rate(&priv->clk, clock); 376 div = (rate + clock - 1) / clock; 377 debug("div = %d\n", div); 378 379 writew(0, &priv->reg->clkcon); 380 381 /* 382 * CLKCON 383 * SELFREQ[15:8] : base clock divided by value 384 * ENSDCLK[2] : SD Clock Enable 385 * STBLINTCLK[1] : Internal Clock Stable 386 * ENINTCLK[0] : Internal Clock Enable 387 */ 388 div >>= 1; 389 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | 390 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); 391 writew(clk, &priv->reg->clkcon); 392 393 /* Wait max 10 ms */ 394 timeout = 10; 395 while (!(readw(&priv->reg->clkcon) & 396 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { 397 if (timeout == 0) { 398 printf("%s: timeout error\n", __func__); 399 return; 400 } 401 timeout--; 402 udelay(1000); 403 } 404 405 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 406 writew(clk, &priv->reg->clkcon); 407 408 debug("mmc_change_clock: clkcon = %08X\n", clk); 409 410 out: 411 priv->clock = clock; 412 } 413 414 static int tegra_mmc_set_ios(struct udevice *dev) 415 { 416 struct tegra_mmc_priv *priv = dev_get_priv(dev); 417 struct mmc *mmc = mmc_get_mmc_dev(dev); 418 unsigned char ctrl; 419 debug(" mmc_set_ios called\n"); 420 421 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); 422 423 /* Change clock first */ 424 tegra_mmc_change_clock(priv, mmc->clock); 425 426 ctrl = readb(&priv->reg->hostctl); 427 428 /* 429 * WIDE8[5] 430 * 0 = Depend on WIDE4 431 * 1 = 8-bit mode 432 * WIDE4[1] 433 * 1 = 4-bit mode 434 * 0 = 1-bit mode 435 */ 436 if (mmc->bus_width == 8) 437 ctrl |= (1 << 5); 438 else if (mmc->bus_width == 4) 439 ctrl |= (1 << 1); 440 else 441 ctrl &= ~(1 << 1 | 1 << 5); 442 443 writeb(ctrl, &priv->reg->hostctl); 444 debug("mmc_set_ios: hostctl = %08X\n", ctrl); 445 446 return 0; 447 } 448 449 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) 450 { 451 #if defined(CONFIG_TEGRA30) 452 u32 val; 453 454 debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg); 455 456 /* Set the pad drive strength for SDMMC1 or 3 only */ 457 if (priv->reg != (void *)0x78000000 && 458 priv->reg != (void *)0x78000400) { 459 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 460 __func__); 461 return; 462 } 463 464 val = readl(&priv->reg->sdmemcmppadctl); 465 val &= 0xFFFFFFF0; 466 val |= MEMCOMP_PADCTRL_VREF; 467 writel(val, &priv->reg->sdmemcmppadctl); 468 469 val = readl(&priv->reg->autocalcfg); 470 val &= 0xFFFF0000; 471 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 472 writel(val, &priv->reg->autocalcfg); 473 #endif 474 } 475 476 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc) 477 { 478 unsigned int timeout; 479 debug(" mmc_reset called\n"); 480 481 /* 482 * RSTALL[0] : Software reset for all 483 * 1 = reset 484 * 0 = work 485 */ 486 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst); 487 488 priv->clock = 0; 489 490 /* Wait max 100 ms */ 491 timeout = 100; 492 493 /* hw clears the bit when it's done */ 494 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { 495 if (timeout == 0) { 496 printf("%s: timeout error\n", __func__); 497 return; 498 } 499 timeout--; 500 udelay(1000); 501 } 502 503 /* Set SD bus voltage & enable bus power */ 504 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1); 505 debug("%s: power control = %02X, host control = %02X\n", __func__, 506 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl)); 507 508 /* Make sure SDIO pads are set up */ 509 tegra_mmc_pad_init(priv); 510 } 511 512 static int tegra_mmc_init(struct udevice *dev) 513 { 514 struct tegra_mmc_priv *priv = dev_get_priv(dev); 515 struct mmc *mmc = mmc_get_mmc_dev(dev); 516 unsigned int mask; 517 debug(" tegra_mmc_init called\n"); 518 519 tegra_mmc_reset(priv, mmc); 520 521 #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK) 522 /* 523 * Disable the external clock loopback and use the internal one on 524 * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 525 * bits being set to 0xfffd according to the TRM. 526 * 527 * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled 528 * approach once proper kernel integration made it mainline. 529 */ 530 if (priv->reg == (void *)0x700b0400) { 531 mask = readl(&priv->reg->venmiscctl); 532 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK; 533 writel(mask, &priv->reg->venmiscctl); 534 } 535 #endif 536 537 priv->version = readw(&priv->reg->hcver); 538 debug("host version = %x\n", priv->version); 539 540 /* mask all */ 541 writel(0xffffffff, &priv->reg->norintstsen); 542 writel(0xffffffff, &priv->reg->norintsigen); 543 544 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */ 545 /* 546 * NORMAL Interrupt Status Enable Register init 547 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable 548 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable 549 * [3] ENSTADMAINT : DMA boundary interrupt 550 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable 551 * [0] ENSTACMDCMPLT : Command Complete Status Enable 552 */ 553 mask = readl(&priv->reg->norintstsen); 554 mask &= ~(0xffff); 555 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | 556 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | 557 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | 558 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | 559 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); 560 writel(mask, &priv->reg->norintstsen); 561 562 /* 563 * NORMAL Interrupt Signal Enable Register init 564 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable 565 */ 566 mask = readl(&priv->reg->norintsigen); 567 mask &= ~(0xffff); 568 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; 569 writel(mask, &priv->reg->norintsigen); 570 571 return 0; 572 } 573 574 static int tegra_mmc_getcd(struct udevice *dev) 575 { 576 struct tegra_mmc_priv *priv = dev_get_priv(dev); 577 578 debug("tegra_mmc_getcd called\n"); 579 580 if (dm_gpio_is_valid(&priv->cd_gpio)) 581 return dm_gpio_get_value(&priv->cd_gpio); 582 583 return 1; 584 } 585 586 static const struct dm_mmc_ops tegra_mmc_ops = { 587 .send_cmd = tegra_mmc_send_cmd, 588 .set_ios = tegra_mmc_set_ios, 589 .get_cd = tegra_mmc_getcd, 590 }; 591 592 static int tegra_mmc_probe(struct udevice *dev) 593 { 594 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 595 struct tegra_mmc_plat *plat = dev_get_platdata(dev); 596 struct tegra_mmc_priv *priv = dev_get_priv(dev); 597 struct mmc_config *cfg = &plat->cfg; 598 int bus_width, ret; 599 600 cfg->name = dev->name; 601 602 bus_width = dev_read_u32_default(dev, "bus-width", 1); 603 604 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 605 cfg->host_caps = 0; 606 if (bus_width == 8) 607 cfg->host_caps |= MMC_MODE_8BIT; 608 if (bus_width >= 4) 609 cfg->host_caps |= MMC_MODE_4BIT; 610 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 611 612 /* 613 * min freq is for card identification, and is the highest 614 * low-speed SDIO card frequency (actually 400KHz) 615 * max freq is highest HS eMMC clock as per the SD/MMC spec 616 * (actually 52MHz) 617 */ 618 cfg->f_min = 375000; 619 cfg->f_max = 48000000; 620 621 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 622 623 priv->reg = (void *)dev_read_addr(dev); 624 625 ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl); 626 if (ret) { 627 debug("reset_get_by_name() failed: %d\n", ret); 628 return ret; 629 } 630 ret = clk_get_by_index(dev, 0, &priv->clk); 631 if (ret) { 632 debug("clk_get_by_index() failed: %d\n", ret); 633 return ret; 634 } 635 636 ret = reset_assert(&priv->reset_ctl); 637 if (ret) 638 return ret; 639 ret = clk_enable(&priv->clk); 640 if (ret) 641 return ret; 642 ret = clk_set_rate(&priv->clk, 20000000); 643 if (IS_ERR_VALUE(ret)) 644 return ret; 645 ret = reset_deassert(&priv->reset_ctl); 646 if (ret) 647 return ret; 648 649 /* These GPIOs are optional */ 650 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); 651 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); 652 gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio, 653 GPIOD_IS_OUT); 654 if (dm_gpio_is_valid(&priv->pwr_gpio)) 655 dm_gpio_set_value(&priv->pwr_gpio, 1); 656 657 upriv->mmc = &plat->mmc; 658 659 return tegra_mmc_init(dev); 660 } 661 662 static int tegra_mmc_bind(struct udevice *dev) 663 { 664 struct tegra_mmc_plat *plat = dev_get_platdata(dev); 665 666 return mmc_bind(dev, &plat->mmc, &plat->cfg); 667 } 668 669 static const struct udevice_id tegra_mmc_ids[] = { 670 { .compatible = "nvidia,tegra20-sdhci" }, 671 { .compatible = "nvidia,tegra30-sdhci" }, 672 { .compatible = "nvidia,tegra114-sdhci" }, 673 { .compatible = "nvidia,tegra124-sdhci" }, 674 { .compatible = "nvidia,tegra210-sdhci" }, 675 { .compatible = "nvidia,tegra186-sdhci" }, 676 { } 677 }; 678 679 U_BOOT_DRIVER(tegra_mmc_drv) = { 680 .name = "tegra_mmc", 681 .id = UCLASS_MMC, 682 .of_match = tegra_mmc_ids, 683 .bind = tegra_mmc_bind, 684 .probe = tegra_mmc_probe, 685 .ops = &tegra_mmc_ops, 686 .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat), 687 .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv), 688 }; 689