1 /* 2 * (C) Copyright 2009 SAMSUNG Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 * Portions Copyright 2011-2015 NVIDIA Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <bouncebuf.h> 11 #include <common.h> 12 #include <errno.h> 13 #include <asm/gpio.h> 14 #include <asm/io.h> 15 #ifndef CONFIG_TEGRA186 16 #include <asm/arch/clock.h> 17 #include <asm/arch-tegra/clk_rst.h> 18 #endif 19 #include <asm/arch-tegra/mmc.h> 20 #include <asm/arch-tegra/tegra_mmc.h> 21 #include <mmc.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE]; 26 27 #if !CONFIG_IS_ENABLED(OF_CONTROL) 28 #error "Please enable device tree support to use this driver" 29 #endif 30 31 static void mmc_set_power(struct mmc_host *host, unsigned short power) 32 { 33 u8 pwr = 0; 34 debug("%s: power = %x\n", __func__, power); 35 36 if (power != (unsigned short)-1) { 37 switch (1 << power) { 38 case MMC_VDD_165_195: 39 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; 40 break; 41 case MMC_VDD_29_30: 42 case MMC_VDD_30_31: 43 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; 44 break; 45 case MMC_VDD_32_33: 46 case MMC_VDD_33_34: 47 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; 48 break; 49 } 50 } 51 debug("%s: pwr = %X\n", __func__, pwr); 52 53 /* Set the bus voltage first (if any) */ 54 writeb(pwr, &host->reg->pwrcon); 55 if (pwr == 0) 56 return; 57 58 /* Now enable bus power */ 59 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER; 60 writeb(pwr, &host->reg->pwrcon); 61 } 62 63 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data, 64 struct bounce_buffer *bbstate) 65 { 66 unsigned char ctrl; 67 68 69 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", 70 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, 71 data->blocksize); 72 73 writel((u32)(unsigned long)bbstate->bounce_buffer, &host->reg->sysad); 74 /* 75 * DMASEL[4:3] 76 * 00 = Selects SDMA 77 * 01 = Reserved 78 * 10 = Selects 32-bit Address ADMA2 79 * 11 = Selects 64-bit Address ADMA2 80 */ 81 ctrl = readb(&host->reg->hostctl); 82 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; 83 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; 84 writeb(ctrl, &host->reg->hostctl); 85 86 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 87 writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize); 88 writew(data->blocks, &host->reg->blkcnt); 89 } 90 91 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data) 92 { 93 unsigned short mode; 94 debug(" mmc_set_transfer_mode called\n"); 95 /* 96 * TRNMOD 97 * MUL1SIN0[5] : Multi/Single Block Select 98 * RD1WT0[4] : Data Transfer Direction Select 99 * 1 = read 100 * 0 = write 101 * ENACMD12[2] : Auto CMD12 Enable 102 * ENBLKCNT[1] : Block Count Enable 103 * ENDMA[0] : DMA Enable 104 */ 105 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | 106 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); 107 108 if (data->blocks > 1) 109 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; 110 111 if (data->flags & MMC_DATA_READ) 112 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; 113 114 writew(mode, &host->reg->trnmod); 115 } 116 117 static int mmc_wait_inhibit(struct mmc_host *host, 118 struct mmc_cmd *cmd, 119 struct mmc_data *data, 120 unsigned int timeout) 121 { 122 /* 123 * PRNSTS 124 * CMDINHDAT[1] : Command Inhibit (DAT) 125 * CMDINHCMD[0] : Command Inhibit (CMD) 126 */ 127 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; 128 129 /* 130 * We shouldn't wait for data inhibit for stop commands, even 131 * though they might use busy signaling 132 */ 133 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) 134 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; 135 136 while (readl(&host->reg->prnsts) & mask) { 137 if (timeout == 0) { 138 printf("%s: timeout error\n", __func__); 139 return -1; 140 } 141 timeout--; 142 udelay(1000); 143 } 144 145 return 0; 146 } 147 148 static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, 149 struct mmc_data *data, struct bounce_buffer *bbstate) 150 { 151 struct mmc_host *host = mmc->priv; 152 int flags, i; 153 int result; 154 unsigned int mask = 0; 155 unsigned int retry = 0x100000; 156 debug(" mmc_send_cmd called\n"); 157 158 result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */); 159 160 if (result < 0) 161 return result; 162 163 if (data) 164 mmc_prepare_data(host, data, bbstate); 165 166 debug("cmd->arg: %08x\n", cmd->cmdarg); 167 writel(cmd->cmdarg, &host->reg->argument); 168 169 if (data) 170 mmc_set_transfer_mode(host, data); 171 172 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 173 return -1; 174 175 /* 176 * CMDREG 177 * CMDIDX[13:8] : Command index 178 * DATAPRNT[5] : Data Present Select 179 * ENCMDIDX[4] : Command Index Check Enable 180 * ENCMDCRC[3] : Command CRC Check Enable 181 * RSPTYP[1:0] 182 * 00 = No Response 183 * 01 = Length 136 184 * 10 = Length 48 185 * 11 = Length 48 Check busy after response 186 */ 187 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 188 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; 189 else if (cmd->resp_type & MMC_RSP_136) 190 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; 191 else if (cmd->resp_type & MMC_RSP_BUSY) 192 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; 193 else 194 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; 195 196 if (cmd->resp_type & MMC_RSP_CRC) 197 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; 198 if (cmd->resp_type & MMC_RSP_OPCODE) 199 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; 200 if (data) 201 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; 202 203 debug("cmd: %d\n", cmd->cmdidx); 204 205 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); 206 207 for (i = 0; i < retry; i++) { 208 mask = readl(&host->reg->norintsts); 209 /* Command Complete */ 210 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { 211 if (!data) 212 writel(mask, &host->reg->norintsts); 213 break; 214 } 215 } 216 217 if (i == retry) { 218 printf("%s: waiting for status update\n", __func__); 219 writel(mask, &host->reg->norintsts); 220 return -ETIMEDOUT; 221 } 222 223 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { 224 /* Timeout Error */ 225 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); 226 writel(mask, &host->reg->norintsts); 227 return -ETIMEDOUT; 228 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 229 /* Error Interrupt */ 230 debug("error: %08x cmd %d\n", mask, cmd->cmdidx); 231 writel(mask, &host->reg->norintsts); 232 return -1; 233 } 234 235 if (cmd->resp_type & MMC_RSP_PRESENT) { 236 if (cmd->resp_type & MMC_RSP_136) { 237 /* CRC is stripped so we need to do some shifting. */ 238 for (i = 0; i < 4; i++) { 239 unsigned long offset = 240 (unsigned long)(&host->reg->rspreg3 - i); 241 cmd->response[i] = readl(offset) << 8; 242 243 if (i != 3) { 244 cmd->response[i] |= 245 readb(offset - 1); 246 } 247 debug("cmd->resp[%d]: %08x\n", 248 i, cmd->response[i]); 249 } 250 } else if (cmd->resp_type & MMC_RSP_BUSY) { 251 for (i = 0; i < retry; i++) { 252 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ 253 if (readl(&host->reg->prnsts) 254 & (1 << 20)) /* DAT[0] */ 255 break; 256 } 257 258 if (i == retry) { 259 printf("%s: card is still busy\n", __func__); 260 writel(mask, &host->reg->norintsts); 261 return -ETIMEDOUT; 262 } 263 264 cmd->response[0] = readl(&host->reg->rspreg0); 265 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 266 } else { 267 cmd->response[0] = readl(&host->reg->rspreg0); 268 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 269 } 270 } 271 272 if (data) { 273 unsigned long start = get_timer(0); 274 275 while (1) { 276 mask = readl(&host->reg->norintsts); 277 278 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 279 /* Error Interrupt */ 280 writel(mask, &host->reg->norintsts); 281 printf("%s: error during transfer: 0x%08x\n", 282 __func__, mask); 283 return -1; 284 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { 285 /* 286 * DMA Interrupt, restart the transfer where 287 * it was interrupted. 288 */ 289 unsigned int address = readl(&host->reg->sysad); 290 291 debug("DMA end\n"); 292 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, 293 &host->reg->norintsts); 294 writel(address, &host->reg->sysad); 295 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { 296 /* Transfer Complete */ 297 debug("r/w is done\n"); 298 break; 299 } else if (get_timer(start) > 8000UL) { 300 writel(mask, &host->reg->norintsts); 301 printf("%s: MMC Timeout\n" 302 " Interrupt status 0x%08x\n" 303 " Interrupt status enable 0x%08x\n" 304 " Interrupt signal enable 0x%08x\n" 305 " Present status 0x%08x\n", 306 __func__, mask, 307 readl(&host->reg->norintstsen), 308 readl(&host->reg->norintsigen), 309 readl(&host->reg->prnsts)); 310 return -1; 311 } 312 } 313 writel(mask, &host->reg->norintsts); 314 } 315 316 udelay(1000); 317 return 0; 318 } 319 320 static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 321 struct mmc_data *data) 322 { 323 void *buf; 324 unsigned int bbflags; 325 size_t len; 326 struct bounce_buffer bbstate; 327 int ret; 328 329 if (data) { 330 if (data->flags & MMC_DATA_READ) { 331 buf = data->dest; 332 bbflags = GEN_BB_WRITE; 333 } else { 334 buf = (void *)data->src; 335 bbflags = GEN_BB_READ; 336 } 337 len = data->blocks * data->blocksize; 338 339 bounce_buffer_start(&bbstate, buf, len, bbflags); 340 } 341 342 ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate); 343 344 if (data) 345 bounce_buffer_stop(&bbstate); 346 347 return ret; 348 } 349 350 static void mmc_change_clock(struct mmc_host *host, uint clock) 351 { 352 int div; 353 unsigned short clk; 354 unsigned long timeout; 355 356 debug(" mmc_change_clock called\n"); 357 358 /* 359 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0 360 */ 361 if (clock == 0) 362 goto out; 363 #ifndef CONFIG_TEGRA186 364 clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock, 365 &div); 366 #else 367 div = (20000000 + clock - 1) / clock; 368 #endif 369 debug("div = %d\n", div); 370 371 writew(0, &host->reg->clkcon); 372 373 /* 374 * CLKCON 375 * SELFREQ[15:8] : base clock divided by value 376 * ENSDCLK[2] : SD Clock Enable 377 * STBLINTCLK[1] : Internal Clock Stable 378 * ENINTCLK[0] : Internal Clock Enable 379 */ 380 div >>= 1; 381 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | 382 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); 383 writew(clk, &host->reg->clkcon); 384 385 /* Wait max 10 ms */ 386 timeout = 10; 387 while (!(readw(&host->reg->clkcon) & 388 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { 389 if (timeout == 0) { 390 printf("%s: timeout error\n", __func__); 391 return; 392 } 393 timeout--; 394 udelay(1000); 395 } 396 397 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 398 writew(clk, &host->reg->clkcon); 399 400 debug("mmc_change_clock: clkcon = %08X\n", clk); 401 402 out: 403 host->clock = clock; 404 } 405 406 static void tegra_mmc_set_ios(struct mmc *mmc) 407 { 408 struct mmc_host *host = mmc->priv; 409 unsigned char ctrl; 410 debug(" mmc_set_ios called\n"); 411 412 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); 413 414 /* Change clock first */ 415 mmc_change_clock(host, mmc->clock); 416 417 ctrl = readb(&host->reg->hostctl); 418 419 /* 420 * WIDE8[5] 421 * 0 = Depend on WIDE4 422 * 1 = 8-bit mode 423 * WIDE4[1] 424 * 1 = 4-bit mode 425 * 0 = 1-bit mode 426 */ 427 if (mmc->bus_width == 8) 428 ctrl |= (1 << 5); 429 else if (mmc->bus_width == 4) 430 ctrl |= (1 << 1); 431 else 432 ctrl &= ~(1 << 1); 433 434 writeb(ctrl, &host->reg->hostctl); 435 debug("mmc_set_ios: hostctl = %08X\n", ctrl); 436 } 437 438 static void mmc_reset(struct mmc_host *host, struct mmc *mmc) 439 { 440 unsigned int timeout; 441 debug(" mmc_reset called\n"); 442 443 /* 444 * RSTALL[0] : Software reset for all 445 * 1 = reset 446 * 0 = work 447 */ 448 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst); 449 450 host->clock = 0; 451 452 /* Wait max 100 ms */ 453 timeout = 100; 454 455 /* hw clears the bit when it's done */ 456 while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { 457 if (timeout == 0) { 458 printf("%s: timeout error\n", __func__); 459 return; 460 } 461 timeout--; 462 udelay(1000); 463 } 464 465 /* Set SD bus voltage & enable bus power */ 466 mmc_set_power(host, fls(mmc->cfg->voltages) - 1); 467 debug("%s: power control = %02X, host control = %02X\n", __func__, 468 readb(&host->reg->pwrcon), readb(&host->reg->hostctl)); 469 470 /* Make sure SDIO pads are set up */ 471 pad_init_mmc(host); 472 } 473 474 static int tegra_mmc_core_init(struct mmc *mmc) 475 { 476 struct mmc_host *host = mmc->priv; 477 unsigned int mask; 478 debug(" mmc_core_init called\n"); 479 480 mmc_reset(host, mmc); 481 482 host->version = readw(&host->reg->hcver); 483 debug("host version = %x\n", host->version); 484 485 /* mask all */ 486 writel(0xffffffff, &host->reg->norintstsen); 487 writel(0xffffffff, &host->reg->norintsigen); 488 489 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */ 490 /* 491 * NORMAL Interrupt Status Enable Register init 492 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable 493 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable 494 * [3] ENSTADMAINT : DMA boundary interrupt 495 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable 496 * [0] ENSTACMDCMPLT : Command Complete Status Enable 497 */ 498 mask = readl(&host->reg->norintstsen); 499 mask &= ~(0xffff); 500 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | 501 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | 502 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | 503 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | 504 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); 505 writel(mask, &host->reg->norintstsen); 506 507 /* 508 * NORMAL Interrupt Signal Enable Register init 509 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable 510 */ 511 mask = readl(&host->reg->norintsigen); 512 mask &= ~(0xffff); 513 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; 514 writel(mask, &host->reg->norintsigen); 515 516 return 0; 517 } 518 519 static int tegra_mmc_getcd(struct mmc *mmc) 520 { 521 struct mmc_host *host = mmc->priv; 522 523 debug("tegra_mmc_getcd called\n"); 524 525 if (dm_gpio_is_valid(&host->cd_gpio)) 526 return dm_gpio_get_value(&host->cd_gpio); 527 528 return 1; 529 } 530 531 static const struct mmc_ops tegra_mmc_ops = { 532 .send_cmd = tegra_mmc_send_cmd, 533 .set_ios = tegra_mmc_set_ios, 534 .init = tegra_mmc_core_init, 535 .getcd = tegra_mmc_getcd, 536 }; 537 538 static int do_mmc_init(int dev_index, bool removable) 539 { 540 struct mmc_host *host; 541 struct mmc *mmc; 542 543 /* DT should have been read & host config filled in */ 544 host = &mmc_host[dev_index]; 545 if (!host->enabled) 546 return -1; 547 548 debug(" do_mmc_init: index %d, bus width %d pwr_gpio %d cd_gpio %d\n", 549 dev_index, host->width, gpio_get_number(&host->pwr_gpio), 550 gpio_get_number(&host->cd_gpio)); 551 552 host->clock = 0; 553 #ifndef CONFIG_TEGRA186 554 clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); 555 #endif 556 557 if (dm_gpio_is_valid(&host->pwr_gpio)) 558 dm_gpio_set_value(&host->pwr_gpio, 1); 559 560 memset(&host->cfg, 0, sizeof(host->cfg)); 561 562 host->cfg.name = "Tegra SD/MMC"; 563 host->cfg.ops = &tegra_mmc_ops; 564 565 host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 566 host->cfg.host_caps = 0; 567 if (host->width == 8) 568 host->cfg.host_caps |= MMC_MODE_8BIT; 569 if (host->width >= 4) 570 host->cfg.host_caps |= MMC_MODE_4BIT; 571 host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 572 573 /* 574 * min freq is for card identification, and is the highest 575 * low-speed SDIO card frequency (actually 400KHz) 576 * max freq is highest HS eMMC clock as per the SD/MMC spec 577 * (actually 52MHz) 578 */ 579 host->cfg.f_min = 375000; 580 #ifndef CONFIG_TEGRA186 581 host->cfg.f_max = 48000000; 582 #else 583 host->cfg.f_max = 375000; 584 #endif 585 586 host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 587 588 mmc = mmc_create(&host->cfg, host); 589 mmc->block_dev.removable = removable; 590 if (mmc == NULL) 591 return -1; 592 593 return 0; 594 } 595 596 /** 597 * Get the host address and peripheral ID for a node. 598 * 599 * @param blob fdt blob 600 * @param node Device index (0-3) 601 * @param host Structure to fill in (reg, width, mmc_id) 602 */ 603 static int mmc_get_config(const void *blob, int node, struct mmc_host *host, 604 bool *removablep) 605 { 606 debug("%s: node = %d\n", __func__, node); 607 608 host->enabled = fdtdec_get_is_enabled(blob, node); 609 610 host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg"); 611 if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) { 612 debug("%s: no sdmmc base reg info found\n", __func__); 613 return -FDT_ERR_NOTFOUND; 614 } 615 616 #ifndef CONFIG_TEGRA186 617 host->mmc_id = clock_decode_periph_id(blob, node); 618 if (host->mmc_id == PERIPH_ID_NONE) { 619 debug("%s: could not decode periph id\n", __func__); 620 return -FDT_ERR_NOTFOUND; 621 } 622 #endif 623 624 /* 625 * NOTE: mmc->bus_width is determined by mmc.c dynamically. 626 * TBD: Override it with this value? 627 */ 628 host->width = fdtdec_get_int(blob, node, "bus-width", 0); 629 if (!host->width) 630 debug("%s: no sdmmc width found\n", __func__); 631 632 /* These GPIOs are optional */ 633 gpio_request_by_name_nodev(blob, node, "cd-gpios", 0, &host->cd_gpio, 634 GPIOD_IS_IN); 635 gpio_request_by_name_nodev(blob, node, "wp-gpios", 0, &host->wp_gpio, 636 GPIOD_IS_IN); 637 gpio_request_by_name_nodev(blob, node, "power-gpios", 0, 638 &host->pwr_gpio, GPIOD_IS_OUT); 639 *removablep = !fdtdec_get_bool(blob, node, "non-removable"); 640 641 debug("%s: found controller at %p, width = %d, periph_id = %d\n", 642 __func__, host->reg, host->width, 643 #ifndef CONFIG_TEGRA186 644 host->mmc_id 645 #else 646 -1 647 #endif 648 ); 649 return 0; 650 } 651 652 /* 653 * Process a list of nodes, adding them to our list of SDMMC ports. 654 * 655 * @param blob fdt blob 656 * @param node_list list of nodes to process (any <=0 are ignored) 657 * @param count number of nodes to process 658 * @return 0 if ok, -1 on error 659 */ 660 static int process_nodes(const void *blob, int node_list[], int count) 661 { 662 struct mmc_host *host; 663 bool removable; 664 int i, node; 665 666 debug("%s: count = %d\n", __func__, count); 667 668 /* build mmc_host[] for each controller */ 669 for (i = 0; i < count; i++) { 670 node = node_list[i]; 671 if (node <= 0) 672 continue; 673 674 host = &mmc_host[i]; 675 host->id = i; 676 677 if (mmc_get_config(blob, node, host, &removable)) { 678 printf("%s: failed to decode dev %d\n", __func__, i); 679 return -1; 680 } 681 do_mmc_init(i, removable); 682 } 683 return 0; 684 } 685 686 void tegra_mmc_init(void) 687 { 688 int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count; 689 const void *blob = gd->fdt_blob; 690 debug("%s entry\n", __func__); 691 692 /* See if any Tegra186 MMC controllers are present */ 693 count = fdtdec_find_aliases_for_id(blob, "sdhci", 694 COMPAT_NVIDIA_TEGRA186_SDMMC, node_list, 695 CONFIG_SYS_MMC_MAX_DEVICE); 696 debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__, count); 697 if (process_nodes(blob, node_list, count)) { 698 printf("%s: Error processing T186 mmc node(s)!\n", __func__); 699 return; 700 } 701 702 /* See if any Tegra210 MMC controllers are present */ 703 count = fdtdec_find_aliases_for_id(blob, "sdhci", 704 COMPAT_NVIDIA_TEGRA210_SDMMC, node_list, 705 CONFIG_SYS_MMC_MAX_DEVICE); 706 debug("%s: count of Tegra210 sdhci nodes is %d\n", __func__, count); 707 if (process_nodes(blob, node_list, count)) { 708 printf("%s: Error processing T210 mmc node(s)!\n", __func__); 709 return; 710 } 711 712 /* See if any Tegra124 MMC controllers are present */ 713 count = fdtdec_find_aliases_for_id(blob, "sdhci", 714 COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, 715 CONFIG_SYS_MMC_MAX_DEVICE); 716 debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count); 717 if (process_nodes(blob, node_list, count)) { 718 printf("%s: Error processing T124 mmc node(s)!\n", __func__); 719 return; 720 } 721 722 /* See if any Tegra30 MMC controllers are present */ 723 count = fdtdec_find_aliases_for_id(blob, "sdhci", 724 COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, 725 CONFIG_SYS_MMC_MAX_DEVICE); 726 debug("%s: count of T30 sdhci nodes is %d\n", __func__, count); 727 if (process_nodes(blob, node_list, count)) { 728 printf("%s: Error processing T30 mmc node(s)!\n", __func__); 729 return; 730 } 731 732 /* Now look for any Tegra20 MMC controllers */ 733 count = fdtdec_find_aliases_for_id(blob, "sdhci", 734 COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, 735 CONFIG_SYS_MMC_MAX_DEVICE); 736 debug("%s: count of T20 sdhci nodes is %d\n", __func__, count); 737 if (process_nodes(blob, node_list, count)) { 738 printf("%s: Error processing T20 mmc node(s)!\n", __func__); 739 return; 740 } 741 } 742