1 /* 2 * (C) Copyright 2009 SAMSUNG Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 * Portions Copyright 2011-2012 NVIDIA Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #include <bouncebuf.h> 23 #include <common.h> 24 #include <asm/gpio.h> 25 #include <asm/io.h> 26 #include <asm/arch/clock.h> 27 #include <asm/arch-tegra/clk_rst.h> 28 #include <asm/arch-tegra/tegra_mmc.h> 29 #include <mmc.h> 30 31 /* support 4 mmc hosts */ 32 struct mmc mmc_dev[4]; 33 struct mmc_host mmc_host[4]; 34 35 36 /** 37 * Get the host address and peripheral ID for a device. Devices are numbered 38 * from 0 to 3. 39 * 40 * @param host Structure to fill in (base, reg, mmc_id) 41 * @param dev_index Device index (0-3) 42 */ 43 static void tegra_get_setup(struct mmc_host *host, int dev_index) 44 { 45 debug("tegra_get_setup: dev_index = %d\n", dev_index); 46 47 switch (dev_index) { 48 case 1: 49 host->base = TEGRA_SDMMC3_BASE; 50 host->mmc_id = PERIPH_ID_SDMMC3; 51 break; 52 case 2: 53 host->base = TEGRA_SDMMC2_BASE; 54 host->mmc_id = PERIPH_ID_SDMMC2; 55 break; 56 case 3: 57 host->base = TEGRA_SDMMC1_BASE; 58 host->mmc_id = PERIPH_ID_SDMMC1; 59 break; 60 case 0: 61 default: 62 host->base = TEGRA_SDMMC4_BASE; 63 host->mmc_id = PERIPH_ID_SDMMC4; 64 break; 65 } 66 67 host->reg = (struct tegra_mmc *)host->base; 68 } 69 70 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data, 71 struct bounce_buffer *bbstate) 72 { 73 unsigned char ctrl; 74 75 76 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", 77 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, 78 data->blocksize); 79 80 writel((u32)bbstate->bounce_buffer, &host->reg->sysad); 81 /* 82 * DMASEL[4:3] 83 * 00 = Selects SDMA 84 * 01 = Reserved 85 * 10 = Selects 32-bit Address ADMA2 86 * 11 = Selects 64-bit Address ADMA2 87 */ 88 ctrl = readb(&host->reg->hostctl); 89 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; 90 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; 91 writeb(ctrl, &host->reg->hostctl); 92 93 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 94 writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize); 95 writew(data->blocks, &host->reg->blkcnt); 96 } 97 98 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data) 99 { 100 unsigned short mode; 101 debug(" mmc_set_transfer_mode called\n"); 102 /* 103 * TRNMOD 104 * MUL1SIN0[5] : Multi/Single Block Select 105 * RD1WT0[4] : Data Transfer Direction Select 106 * 1 = read 107 * 0 = write 108 * ENACMD12[2] : Auto CMD12 Enable 109 * ENBLKCNT[1] : Block Count Enable 110 * ENDMA[0] : DMA Enable 111 */ 112 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | 113 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); 114 115 if (data->blocks > 1) 116 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; 117 118 if (data->flags & MMC_DATA_READ) 119 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; 120 121 writew(mode, &host->reg->trnmod); 122 } 123 124 static int mmc_wait_inhibit(struct mmc_host *host, 125 struct mmc_cmd *cmd, 126 struct mmc_data *data, 127 unsigned int timeout) 128 { 129 /* 130 * PRNSTS 131 * CMDINHDAT[1] : Command Inhibit (DAT) 132 * CMDINHCMD[0] : Command Inhibit (CMD) 133 */ 134 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; 135 136 /* 137 * We shouldn't wait for data inhibit for stop commands, even 138 * though they might use busy signaling 139 */ 140 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) 141 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; 142 143 while (readl(&host->reg->prnsts) & mask) { 144 if (timeout == 0) { 145 printf("%s: timeout error\n", __func__); 146 return -1; 147 } 148 timeout--; 149 udelay(1000); 150 } 151 152 return 0; 153 } 154 155 static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, 156 struct mmc_data *data, struct bounce_buffer *bbstate) 157 { 158 struct mmc_host *host = (struct mmc_host *)mmc->priv; 159 int flags, i; 160 int result; 161 unsigned int mask = 0; 162 unsigned int retry = 0x100000; 163 debug(" mmc_send_cmd called\n"); 164 165 result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */); 166 167 if (result < 0) 168 return result; 169 170 if (data) 171 mmc_prepare_data(host, data, bbstate); 172 173 debug("cmd->arg: %08x\n", cmd->cmdarg); 174 writel(cmd->cmdarg, &host->reg->argument); 175 176 if (data) 177 mmc_set_transfer_mode(host, data); 178 179 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 180 return -1; 181 182 /* 183 * CMDREG 184 * CMDIDX[13:8] : Command index 185 * DATAPRNT[5] : Data Present Select 186 * ENCMDIDX[4] : Command Index Check Enable 187 * ENCMDCRC[3] : Command CRC Check Enable 188 * RSPTYP[1:0] 189 * 00 = No Response 190 * 01 = Length 136 191 * 10 = Length 48 192 * 11 = Length 48 Check busy after response 193 */ 194 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 195 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; 196 else if (cmd->resp_type & MMC_RSP_136) 197 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; 198 else if (cmd->resp_type & MMC_RSP_BUSY) 199 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; 200 else 201 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; 202 203 if (cmd->resp_type & MMC_RSP_CRC) 204 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; 205 if (cmd->resp_type & MMC_RSP_OPCODE) 206 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; 207 if (data) 208 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; 209 210 debug("cmd: %d\n", cmd->cmdidx); 211 212 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); 213 214 for (i = 0; i < retry; i++) { 215 mask = readl(&host->reg->norintsts); 216 /* Command Complete */ 217 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { 218 if (!data) 219 writel(mask, &host->reg->norintsts); 220 break; 221 } 222 } 223 224 if (i == retry) { 225 printf("%s: waiting for status update\n", __func__); 226 writel(mask, &host->reg->norintsts); 227 return TIMEOUT; 228 } 229 230 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { 231 /* Timeout Error */ 232 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); 233 writel(mask, &host->reg->norintsts); 234 return TIMEOUT; 235 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 236 /* Error Interrupt */ 237 debug("error: %08x cmd %d\n", mask, cmd->cmdidx); 238 writel(mask, &host->reg->norintsts); 239 return -1; 240 } 241 242 if (cmd->resp_type & MMC_RSP_PRESENT) { 243 if (cmd->resp_type & MMC_RSP_136) { 244 /* CRC is stripped so we need to do some shifting. */ 245 for (i = 0; i < 4; i++) { 246 unsigned int offset = 247 (unsigned int)(&host->reg->rspreg3 - i); 248 cmd->response[i] = readl(offset) << 8; 249 250 if (i != 3) { 251 cmd->response[i] |= 252 readb(offset - 1); 253 } 254 debug("cmd->resp[%d]: %08x\n", 255 i, cmd->response[i]); 256 } 257 } else if (cmd->resp_type & MMC_RSP_BUSY) { 258 for (i = 0; i < retry; i++) { 259 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ 260 if (readl(&host->reg->prnsts) 261 & (1 << 20)) /* DAT[0] */ 262 break; 263 } 264 265 if (i == retry) { 266 printf("%s: card is still busy\n", __func__); 267 writel(mask, &host->reg->norintsts); 268 return TIMEOUT; 269 } 270 271 cmd->response[0] = readl(&host->reg->rspreg0); 272 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 273 } else { 274 cmd->response[0] = readl(&host->reg->rspreg0); 275 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 276 } 277 } 278 279 if (data) { 280 unsigned long start = get_timer(0); 281 282 while (1) { 283 mask = readl(&host->reg->norintsts); 284 285 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 286 /* Error Interrupt */ 287 writel(mask, &host->reg->norintsts); 288 printf("%s: error during transfer: 0x%08x\n", 289 __func__, mask); 290 return -1; 291 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { 292 /* 293 * DMA Interrupt, restart the transfer where 294 * it was interrupted. 295 */ 296 unsigned int address = readl(&host->reg->sysad); 297 298 debug("DMA end\n"); 299 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, 300 &host->reg->norintsts); 301 writel(address, &host->reg->sysad); 302 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { 303 /* Transfer Complete */ 304 debug("r/w is done\n"); 305 break; 306 } else if (get_timer(start) > 2000UL) { 307 writel(mask, &host->reg->norintsts); 308 printf("%s: MMC Timeout\n" 309 " Interrupt status 0x%08x\n" 310 " Interrupt status enable 0x%08x\n" 311 " Interrupt signal enable 0x%08x\n" 312 " Present status 0x%08x\n", 313 __func__, mask, 314 readl(&host->reg->norintstsen), 315 readl(&host->reg->norintsigen), 316 readl(&host->reg->prnsts)); 317 return -1; 318 } 319 } 320 writel(mask, &host->reg->norintsts); 321 } 322 323 udelay(1000); 324 return 0; 325 } 326 327 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 328 struct mmc_data *data) 329 { 330 void *buf; 331 unsigned int bbflags; 332 size_t len; 333 struct bounce_buffer bbstate; 334 int ret; 335 336 if (data) { 337 if (data->flags & MMC_DATA_READ) { 338 buf = data->dest; 339 bbflags = GEN_BB_WRITE; 340 } else { 341 buf = (void *)data->src; 342 bbflags = GEN_BB_READ; 343 } 344 len = data->blocks * data->blocksize; 345 346 bounce_buffer_start(&bbstate, buf, len, bbflags); 347 } 348 349 ret = mmc_send_cmd_bounced(mmc, cmd, data, &bbstate); 350 351 if (data) 352 bounce_buffer_stop(&bbstate); 353 354 return ret; 355 } 356 357 static void mmc_change_clock(struct mmc_host *host, uint clock) 358 { 359 int div; 360 unsigned short clk; 361 unsigned long timeout; 362 363 debug(" mmc_change_clock called\n"); 364 365 /* 366 * Change Tegra SDMMCx clock divisor here. Source is 216MHz, 367 * PLLP_OUT0 368 */ 369 if (clock == 0) 370 goto out; 371 clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock, 372 &div); 373 debug("div = %d\n", div); 374 375 writew(0, &host->reg->clkcon); 376 377 /* 378 * CLKCON 379 * SELFREQ[15:8] : base clock divided by value 380 * ENSDCLK[2] : SD Clock Enable 381 * STBLINTCLK[1] : Internal Clock Stable 382 * ENINTCLK[0] : Internal Clock Enable 383 */ 384 div >>= 1; 385 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | 386 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); 387 writew(clk, &host->reg->clkcon); 388 389 /* Wait max 10 ms */ 390 timeout = 10; 391 while (!(readw(&host->reg->clkcon) & 392 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { 393 if (timeout == 0) { 394 printf("%s: timeout error\n", __func__); 395 return; 396 } 397 timeout--; 398 udelay(1000); 399 } 400 401 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 402 writew(clk, &host->reg->clkcon); 403 404 debug("mmc_change_clock: clkcon = %08X\n", clk); 405 406 out: 407 host->clock = clock; 408 } 409 410 static void mmc_set_ios(struct mmc *mmc) 411 { 412 struct mmc_host *host = mmc->priv; 413 unsigned char ctrl; 414 debug(" mmc_set_ios called\n"); 415 416 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); 417 418 /* Change clock first */ 419 mmc_change_clock(host, mmc->clock); 420 421 ctrl = readb(&host->reg->hostctl); 422 423 /* 424 * WIDE8[5] 425 * 0 = Depend on WIDE4 426 * 1 = 8-bit mode 427 * WIDE4[1] 428 * 1 = 4-bit mode 429 * 0 = 1-bit mode 430 */ 431 if (mmc->bus_width == 8) 432 ctrl |= (1 << 5); 433 else if (mmc->bus_width == 4) 434 ctrl |= (1 << 1); 435 else 436 ctrl &= ~(1 << 1); 437 438 writeb(ctrl, &host->reg->hostctl); 439 debug("mmc_set_ios: hostctl = %08X\n", ctrl); 440 } 441 442 static void mmc_reset(struct mmc_host *host) 443 { 444 unsigned int timeout; 445 debug(" mmc_reset called\n"); 446 447 /* 448 * RSTALL[0] : Software reset for all 449 * 1 = reset 450 * 0 = work 451 */ 452 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst); 453 454 host->clock = 0; 455 456 /* Wait max 100 ms */ 457 timeout = 100; 458 459 /* hw clears the bit when it's done */ 460 while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { 461 if (timeout == 0) { 462 printf("%s: timeout error\n", __func__); 463 return; 464 } 465 timeout--; 466 udelay(1000); 467 } 468 } 469 470 static int mmc_core_init(struct mmc *mmc) 471 { 472 struct mmc_host *host = (struct mmc_host *)mmc->priv; 473 unsigned int mask; 474 debug(" mmc_core_init called\n"); 475 476 mmc_reset(host); 477 478 host->version = readw(&host->reg->hcver); 479 debug("host version = %x\n", host->version); 480 481 /* mask all */ 482 writel(0xffffffff, &host->reg->norintstsen); 483 writel(0xffffffff, &host->reg->norintsigen); 484 485 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */ 486 /* 487 * NORMAL Interrupt Status Enable Register init 488 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable 489 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable 490 * [3] ENSTADMAINT : DMA boundary interrupt 491 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable 492 * [0] ENSTACMDCMPLT : Command Complete Status Enable 493 */ 494 mask = readl(&host->reg->norintstsen); 495 mask &= ~(0xffff); 496 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | 497 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | 498 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | 499 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | 500 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); 501 writel(mask, &host->reg->norintstsen); 502 503 /* 504 * NORMAL Interrupt Signal Enable Register init 505 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable 506 */ 507 mask = readl(&host->reg->norintsigen); 508 mask &= ~(0xffff); 509 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; 510 writel(mask, &host->reg->norintsigen); 511 512 return 0; 513 } 514 515 int tegra_mmc_getcd(struct mmc *mmc) 516 { 517 struct mmc_host *host = (struct mmc_host *)mmc->priv; 518 519 debug("tegra_mmc_getcd called\n"); 520 521 if (host->cd_gpio >= 0) 522 return !gpio_get_value(host->cd_gpio); 523 524 return 1; 525 } 526 527 int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio) 528 { 529 struct mmc_host *host; 530 char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */ 531 struct mmc *mmc; 532 533 debug(" tegra_mmc_init: index %d, bus width %d " 534 "pwr_gpio %d cd_gpio %d\n", 535 dev_index, bus_width, pwr_gpio, cd_gpio); 536 537 host = &mmc_host[dev_index]; 538 539 host->clock = 0; 540 host->pwr_gpio = pwr_gpio; 541 host->cd_gpio = cd_gpio; 542 tegra_get_setup(host, dev_index); 543 544 clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); 545 546 if (host->pwr_gpio >= 0) { 547 sprintf(gpusage, "SD/MMC%d PWR", dev_index); 548 gpio_request(host->pwr_gpio, gpusage); 549 gpio_direction_output(host->pwr_gpio, 1); 550 } 551 552 if (host->cd_gpio >= 0) { 553 sprintf(gpusage, "SD/MMC%d CD", dev_index); 554 gpio_request(host->cd_gpio, gpusage); 555 gpio_direction_input(host->cd_gpio); 556 } 557 558 mmc = &mmc_dev[dev_index]; 559 560 sprintf(mmc->name, "Tegra SD/MMC"); 561 mmc->priv = host; 562 mmc->send_cmd = mmc_send_cmd; 563 mmc->set_ios = mmc_set_ios; 564 mmc->init = mmc_core_init; 565 mmc->getcd = tegra_mmc_getcd; 566 567 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 568 mmc->host_caps = 0; 569 if (bus_width == 8) 570 mmc->host_caps |= MMC_MODE_8BIT; 571 if (bus_width >= 4) 572 mmc->host_caps |= MMC_MODE_4BIT; 573 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC; 574 575 /* 576 * min freq is for card identification, and is the highest 577 * low-speed SDIO card frequency (actually 400KHz) 578 * max freq is highest HS eMMC clock as per the SD/MMC spec 579 * (actually 52MHz) 580 * Both of these are the closest equivalents w/216MHz source 581 * clock and Tegra SDMMC divisors. 582 */ 583 mmc->f_min = 375000; 584 mmc->f_max = 48000000; 585 586 mmc_register(mmc); 587 588 return 0; 589 } 590