1 /* 2 * (C) Copyright 2009 SAMSUNG Electronics 3 * Minkyu Kang <mk7.kang@samsung.com> 4 * Jaehoon Chung <jh80.chung@samsung.com> 5 * Portions Copyright 2011-2016 NVIDIA Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <bouncebuf.h> 11 #include <common.h> 12 #include <dm/device.h> 13 #include <errno.h> 14 #include <asm/gpio.h> 15 #include <asm/io.h> 16 #include <asm/arch-tegra/tegra_mmc.h> 17 #include <mmc.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 struct tegra_mmc_priv { 22 struct tegra_mmc *reg; 23 struct reset_ctl reset_ctl; 24 struct clk clk; 25 struct gpio_desc cd_gpio; /* Change Detect GPIO */ 26 struct gpio_desc pwr_gpio; /* Power GPIO */ 27 struct gpio_desc wp_gpio; /* Write Protect GPIO */ 28 unsigned int version; /* SDHCI spec. version */ 29 unsigned int clock; /* Current clock (MHz) */ 30 struct mmc_config cfg; /* mmc configuration */ 31 struct mmc *mmc; 32 }; 33 34 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv, 35 unsigned short power) 36 { 37 u8 pwr = 0; 38 debug("%s: power = %x\n", __func__, power); 39 40 if (power != (unsigned short)-1) { 41 switch (1 << power) { 42 case MMC_VDD_165_195: 43 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; 44 break; 45 case MMC_VDD_29_30: 46 case MMC_VDD_30_31: 47 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; 48 break; 49 case MMC_VDD_32_33: 50 case MMC_VDD_33_34: 51 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; 52 break; 53 } 54 } 55 debug("%s: pwr = %X\n", __func__, pwr); 56 57 /* Set the bus voltage first (if any) */ 58 writeb(pwr, &priv->reg->pwrcon); 59 if (pwr == 0) 60 return; 61 62 /* Now enable bus power */ 63 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER; 64 writeb(pwr, &priv->reg->pwrcon); 65 } 66 67 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv, 68 struct mmc_data *data, 69 struct bounce_buffer *bbstate) 70 { 71 unsigned char ctrl; 72 73 74 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", 75 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, 76 data->blocksize); 77 78 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad); 79 /* 80 * DMASEL[4:3] 81 * 00 = Selects SDMA 82 * 01 = Reserved 83 * 10 = Selects 32-bit Address ADMA2 84 * 11 = Selects 64-bit Address ADMA2 85 */ 86 ctrl = readb(&priv->reg->hostctl); 87 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; 88 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; 89 writeb(ctrl, &priv->reg->hostctl); 90 91 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 92 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize); 93 writew(data->blocks, &priv->reg->blkcnt); 94 } 95 96 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv, 97 struct mmc_data *data) 98 { 99 unsigned short mode; 100 debug(" mmc_set_transfer_mode called\n"); 101 /* 102 * TRNMOD 103 * MUL1SIN0[5] : Multi/Single Block Select 104 * RD1WT0[4] : Data Transfer Direction Select 105 * 1 = read 106 * 0 = write 107 * ENACMD12[2] : Auto CMD12 Enable 108 * ENBLKCNT[1] : Block Count Enable 109 * ENDMA[0] : DMA Enable 110 */ 111 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | 112 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); 113 114 if (data->blocks > 1) 115 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; 116 117 if (data->flags & MMC_DATA_READ) 118 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; 119 120 writew(mode, &priv->reg->trnmod); 121 } 122 123 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv, 124 struct mmc_cmd *cmd, 125 struct mmc_data *data, 126 unsigned int timeout) 127 { 128 /* 129 * PRNSTS 130 * CMDINHDAT[1] : Command Inhibit (DAT) 131 * CMDINHCMD[0] : Command Inhibit (CMD) 132 */ 133 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; 134 135 /* 136 * We shouldn't wait for data inhibit for stop commands, even 137 * though they might use busy signaling 138 */ 139 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) 140 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; 141 142 while (readl(&priv->reg->prnsts) & mask) { 143 if (timeout == 0) { 144 printf("%s: timeout error\n", __func__); 145 return -1; 146 } 147 timeout--; 148 udelay(1000); 149 } 150 151 return 0; 152 } 153 154 static int tegra_mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, 155 struct mmc_data *data, 156 struct bounce_buffer *bbstate) 157 { 158 struct tegra_mmc_priv *priv = mmc->priv; 159 int flags, i; 160 int result; 161 unsigned int mask = 0; 162 unsigned int retry = 0x100000; 163 debug(" mmc_send_cmd called\n"); 164 165 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */); 166 167 if (result < 0) 168 return result; 169 170 if (data) 171 tegra_mmc_prepare_data(priv, data, bbstate); 172 173 debug("cmd->arg: %08x\n", cmd->cmdarg); 174 writel(cmd->cmdarg, &priv->reg->argument); 175 176 if (data) 177 tegra_mmc_set_transfer_mode(priv, data); 178 179 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 180 return -1; 181 182 /* 183 * CMDREG 184 * CMDIDX[13:8] : Command index 185 * DATAPRNT[5] : Data Present Select 186 * ENCMDIDX[4] : Command Index Check Enable 187 * ENCMDCRC[3] : Command CRC Check Enable 188 * RSPTYP[1:0] 189 * 00 = No Response 190 * 01 = Length 136 191 * 10 = Length 48 192 * 11 = Length 48 Check busy after response 193 */ 194 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 195 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; 196 else if (cmd->resp_type & MMC_RSP_136) 197 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; 198 else if (cmd->resp_type & MMC_RSP_BUSY) 199 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; 200 else 201 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; 202 203 if (cmd->resp_type & MMC_RSP_CRC) 204 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; 205 if (cmd->resp_type & MMC_RSP_OPCODE) 206 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; 207 if (data) 208 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; 209 210 debug("cmd: %d\n", cmd->cmdidx); 211 212 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg); 213 214 for (i = 0; i < retry; i++) { 215 mask = readl(&priv->reg->norintsts); 216 /* Command Complete */ 217 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { 218 if (!data) 219 writel(mask, &priv->reg->norintsts); 220 break; 221 } 222 } 223 224 if (i == retry) { 225 printf("%s: waiting for status update\n", __func__); 226 writel(mask, &priv->reg->norintsts); 227 return -ETIMEDOUT; 228 } 229 230 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { 231 /* Timeout Error */ 232 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); 233 writel(mask, &priv->reg->norintsts); 234 return -ETIMEDOUT; 235 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 236 /* Error Interrupt */ 237 debug("error: %08x cmd %d\n", mask, cmd->cmdidx); 238 writel(mask, &priv->reg->norintsts); 239 return -1; 240 } 241 242 if (cmd->resp_type & MMC_RSP_PRESENT) { 243 if (cmd->resp_type & MMC_RSP_136) { 244 /* CRC is stripped so we need to do some shifting. */ 245 for (i = 0; i < 4; i++) { 246 unsigned long offset = (unsigned long) 247 (&priv->reg->rspreg3 - i); 248 cmd->response[i] = readl(offset) << 8; 249 250 if (i != 3) { 251 cmd->response[i] |= 252 readb(offset - 1); 253 } 254 debug("cmd->resp[%d]: %08x\n", 255 i, cmd->response[i]); 256 } 257 } else if (cmd->resp_type & MMC_RSP_BUSY) { 258 for (i = 0; i < retry; i++) { 259 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ 260 if (readl(&priv->reg->prnsts) 261 & (1 << 20)) /* DAT[0] */ 262 break; 263 } 264 265 if (i == retry) { 266 printf("%s: card is still busy\n", __func__); 267 writel(mask, &priv->reg->norintsts); 268 return -ETIMEDOUT; 269 } 270 271 cmd->response[0] = readl(&priv->reg->rspreg0); 272 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 273 } else { 274 cmd->response[0] = readl(&priv->reg->rspreg0); 275 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 276 } 277 } 278 279 if (data) { 280 unsigned long start = get_timer(0); 281 282 while (1) { 283 mask = readl(&priv->reg->norintsts); 284 285 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 286 /* Error Interrupt */ 287 writel(mask, &priv->reg->norintsts); 288 printf("%s: error during transfer: 0x%08x\n", 289 __func__, mask); 290 return -1; 291 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { 292 /* 293 * DMA Interrupt, restart the transfer where 294 * it was interrupted. 295 */ 296 unsigned int address = readl(&priv->reg->sysad); 297 298 debug("DMA end\n"); 299 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, 300 &priv->reg->norintsts); 301 writel(address, &priv->reg->sysad); 302 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { 303 /* Transfer Complete */ 304 debug("r/w is done\n"); 305 break; 306 } else if (get_timer(start) > 8000UL) { 307 writel(mask, &priv->reg->norintsts); 308 printf("%s: MMC Timeout\n" 309 " Interrupt status 0x%08x\n" 310 " Interrupt status enable 0x%08x\n" 311 " Interrupt signal enable 0x%08x\n" 312 " Present status 0x%08x\n", 313 __func__, mask, 314 readl(&priv->reg->norintstsen), 315 readl(&priv->reg->norintsigen), 316 readl(&priv->reg->prnsts)); 317 return -1; 318 } 319 } 320 writel(mask, &priv->reg->norintsts); 321 } 322 323 udelay(1000); 324 return 0; 325 } 326 327 static int tegra_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 328 struct mmc_data *data) 329 { 330 void *buf; 331 unsigned int bbflags; 332 size_t len; 333 struct bounce_buffer bbstate; 334 int ret; 335 336 if (data) { 337 if (data->flags & MMC_DATA_READ) { 338 buf = data->dest; 339 bbflags = GEN_BB_WRITE; 340 } else { 341 buf = (void *)data->src; 342 bbflags = GEN_BB_READ; 343 } 344 len = data->blocks * data->blocksize; 345 346 bounce_buffer_start(&bbstate, buf, len, bbflags); 347 } 348 349 ret = tegra_mmc_send_cmd_bounced(mmc, cmd, data, &bbstate); 350 351 if (data) 352 bounce_buffer_stop(&bbstate); 353 354 return ret; 355 } 356 357 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock) 358 { 359 ulong rate; 360 int div; 361 unsigned short clk; 362 unsigned long timeout; 363 364 debug(" mmc_change_clock called\n"); 365 366 /* 367 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0 368 */ 369 if (clock == 0) 370 goto out; 371 372 rate = clk_set_rate(&priv->clk, clock); 373 div = (rate + clock - 1) / clock; 374 debug("div = %d\n", div); 375 376 writew(0, &priv->reg->clkcon); 377 378 /* 379 * CLKCON 380 * SELFREQ[15:8] : base clock divided by value 381 * ENSDCLK[2] : SD Clock Enable 382 * STBLINTCLK[1] : Internal Clock Stable 383 * ENINTCLK[0] : Internal Clock Enable 384 */ 385 div >>= 1; 386 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | 387 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); 388 writew(clk, &priv->reg->clkcon); 389 390 /* Wait max 10 ms */ 391 timeout = 10; 392 while (!(readw(&priv->reg->clkcon) & 393 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { 394 if (timeout == 0) { 395 printf("%s: timeout error\n", __func__); 396 return; 397 } 398 timeout--; 399 udelay(1000); 400 } 401 402 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 403 writew(clk, &priv->reg->clkcon); 404 405 debug("mmc_change_clock: clkcon = %08X\n", clk); 406 407 out: 408 priv->clock = clock; 409 } 410 411 static int tegra_mmc_set_ios(struct mmc *mmc) 412 { 413 struct tegra_mmc_priv *priv = mmc->priv; 414 unsigned char ctrl; 415 debug(" mmc_set_ios called\n"); 416 417 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); 418 419 /* Change clock first */ 420 tegra_mmc_change_clock(priv, mmc->clock); 421 422 ctrl = readb(&priv->reg->hostctl); 423 424 /* 425 * WIDE8[5] 426 * 0 = Depend on WIDE4 427 * 1 = 8-bit mode 428 * WIDE4[1] 429 * 1 = 4-bit mode 430 * 0 = 1-bit mode 431 */ 432 if (mmc->bus_width == 8) 433 ctrl |= (1 << 5); 434 else if (mmc->bus_width == 4) 435 ctrl |= (1 << 1); 436 else 437 ctrl &= ~(1 << 1); 438 439 writeb(ctrl, &priv->reg->hostctl); 440 debug("mmc_set_ios: hostctl = %08X\n", ctrl); 441 442 return 0; 443 } 444 445 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) 446 { 447 #if defined(CONFIG_TEGRA30) 448 u32 val; 449 450 debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg); 451 452 /* Set the pad drive strength for SDMMC1 or 3 only */ 453 if (priv->reg != (void *)0x78000000 && 454 priv->reg != (void *)0x78000400) { 455 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 456 __func__); 457 return; 458 } 459 460 val = readl(&priv->reg->sdmemcmppadctl); 461 val &= 0xFFFFFFF0; 462 val |= MEMCOMP_PADCTRL_VREF; 463 writel(val, &priv->reg->sdmemcmppadctl); 464 465 val = readl(&priv->reg->autocalcfg); 466 val &= 0xFFFF0000; 467 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; 468 writel(val, &priv->reg->autocalcfg); 469 #endif 470 } 471 472 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc) 473 { 474 unsigned int timeout; 475 debug(" mmc_reset called\n"); 476 477 /* 478 * RSTALL[0] : Software reset for all 479 * 1 = reset 480 * 0 = work 481 */ 482 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst); 483 484 priv->clock = 0; 485 486 /* Wait max 100 ms */ 487 timeout = 100; 488 489 /* hw clears the bit when it's done */ 490 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { 491 if (timeout == 0) { 492 printf("%s: timeout error\n", __func__); 493 return; 494 } 495 timeout--; 496 udelay(1000); 497 } 498 499 /* Set SD bus voltage & enable bus power */ 500 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1); 501 debug("%s: power control = %02X, host control = %02X\n", __func__, 502 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl)); 503 504 /* Make sure SDIO pads are set up */ 505 tegra_mmc_pad_init(priv); 506 } 507 508 static int tegra_mmc_init(struct mmc *mmc) 509 { 510 struct tegra_mmc_priv *priv = mmc->priv; 511 unsigned int mask; 512 debug(" tegra_mmc_init called\n"); 513 514 tegra_mmc_reset(priv, mmc); 515 516 priv->version = readw(&priv->reg->hcver); 517 debug("host version = %x\n", priv->version); 518 519 /* mask all */ 520 writel(0xffffffff, &priv->reg->norintstsen); 521 writel(0xffffffff, &priv->reg->norintsigen); 522 523 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */ 524 /* 525 * NORMAL Interrupt Status Enable Register init 526 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable 527 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable 528 * [3] ENSTADMAINT : DMA boundary interrupt 529 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable 530 * [0] ENSTACMDCMPLT : Command Complete Status Enable 531 */ 532 mask = readl(&priv->reg->norintstsen); 533 mask &= ~(0xffff); 534 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | 535 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | 536 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | 537 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | 538 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); 539 writel(mask, &priv->reg->norintstsen); 540 541 /* 542 * NORMAL Interrupt Signal Enable Register init 543 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable 544 */ 545 mask = readl(&priv->reg->norintsigen); 546 mask &= ~(0xffff); 547 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; 548 writel(mask, &priv->reg->norintsigen); 549 550 return 0; 551 } 552 553 static int tegra_mmc_getcd(struct mmc *mmc) 554 { 555 struct tegra_mmc_priv *priv = mmc->priv; 556 557 debug("tegra_mmc_getcd called\n"); 558 559 if (dm_gpio_is_valid(&priv->cd_gpio)) 560 return dm_gpio_get_value(&priv->cd_gpio); 561 562 return 1; 563 } 564 565 static const struct mmc_ops tegra_mmc_ops = { 566 .send_cmd = tegra_mmc_send_cmd, 567 .set_ios = tegra_mmc_set_ios, 568 .init = tegra_mmc_init, 569 .getcd = tegra_mmc_getcd, 570 }; 571 572 static int tegra_mmc_probe(struct udevice *dev) 573 { 574 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 575 struct tegra_mmc_priv *priv = dev_get_priv(dev); 576 int bus_width, ret; 577 578 priv->cfg.name = "Tegra SD/MMC"; 579 priv->cfg.ops = &tegra_mmc_ops; 580 581 bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 582 "bus-width", 1); 583 584 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 585 priv->cfg.host_caps = 0; 586 if (bus_width == 8) 587 priv->cfg.host_caps |= MMC_MODE_8BIT; 588 if (bus_width >= 4) 589 priv->cfg.host_caps |= MMC_MODE_4BIT; 590 priv->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 591 592 /* 593 * min freq is for card identification, and is the highest 594 * low-speed SDIO card frequency (actually 400KHz) 595 * max freq is highest HS eMMC clock as per the SD/MMC spec 596 * (actually 52MHz) 597 */ 598 priv->cfg.f_min = 375000; 599 priv->cfg.f_max = 48000000; 600 601 priv->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 602 603 priv->reg = (void *)dev_get_addr(dev); 604 605 ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl); 606 if (ret) { 607 debug("reset_get_by_name() failed: %d\n", ret); 608 return ret; 609 } 610 ret = clk_get_by_index(dev, 0, &priv->clk); 611 if (ret) { 612 debug("clk_get_by_index() failed: %d\n", ret); 613 return ret; 614 } 615 616 ret = reset_assert(&priv->reset_ctl); 617 if (ret) 618 return ret; 619 ret = clk_enable(&priv->clk); 620 if (ret) 621 return ret; 622 ret = clk_set_rate(&priv->clk, 20000000); 623 if (IS_ERR_VALUE(ret)) 624 return ret; 625 ret = reset_deassert(&priv->reset_ctl); 626 if (ret) 627 return ret; 628 629 /* These GPIOs are optional */ 630 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, 631 GPIOD_IS_IN); 632 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, 633 GPIOD_IS_IN); 634 gpio_request_by_name(dev, "power-gpios", 0, 635 &priv->pwr_gpio, GPIOD_IS_OUT); 636 if (dm_gpio_is_valid(&priv->pwr_gpio)) 637 dm_gpio_set_value(&priv->pwr_gpio, 1); 638 639 priv->mmc = mmc_create(&priv->cfg, priv); 640 if (priv->mmc == NULL) 641 return -1; 642 643 priv->mmc->dev = dev; 644 upriv->mmc = priv->mmc; 645 646 return 0; 647 } 648 649 static const struct udevice_id tegra_mmc_ids[] = { 650 { .compatible = "nvidia,tegra20-sdhci" }, 651 { .compatible = "nvidia,tegra30-sdhci" }, 652 { .compatible = "nvidia,tegra114-sdhci" }, 653 { .compatible = "nvidia,tegra124-sdhci" }, 654 { .compatible = "nvidia,tegra210-sdhci" }, 655 { .compatible = "nvidia,tegra186-sdhci" }, 656 { } 657 }; 658 659 U_BOOT_DRIVER(tegra_mmc_drv) = { 660 .name = "tegra_mmc", 661 .id = UCLASS_MMC, 662 .of_match = tegra_mmc_ids, 663 .probe = tegra_mmc_probe, 664 .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv), 665 }; 666