1 /* 2 * (C) Copyright 2007-2011 3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4 * Aaron <leafy.myeh@allwinnertech.com> 5 * 6 * MMC driver for allwinner sunxi platform. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <mmc.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/gpio.h> 19 #include <asm/arch/mmc.h> 20 #include <asm-generic/gpio.h> 21 22 struct sunxi_mmc_host { 23 unsigned mmc_no; 24 uint32_t *mclkreg; 25 unsigned fatal_err; 26 struct sunxi_mmc *reg; 27 struct mmc_config cfg; 28 }; 29 30 /* support 4 mmc hosts */ 31 struct sunxi_mmc_host mmc_host[4]; 32 33 static int sunxi_mmc_getcd_gpio(int sdc_no) 34 { 35 switch (sdc_no) { 36 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN); 37 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN); 38 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN); 39 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN); 40 } 41 return -EINVAL; 42 } 43 44 static int mmc_resource_init(int sdc_no) 45 { 46 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; 47 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 48 int cd_pin, ret = 0; 49 50 debug("init mmc %d resource\n", sdc_no); 51 52 switch (sdc_no) { 53 case 0: 54 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; 55 mmchost->mclkreg = &ccm->sd0_clk_cfg; 56 break; 57 case 1: 58 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; 59 mmchost->mclkreg = &ccm->sd1_clk_cfg; 60 break; 61 case 2: 62 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; 63 mmchost->mclkreg = &ccm->sd2_clk_cfg; 64 break; 65 case 3: 66 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; 67 mmchost->mclkreg = &ccm->sd3_clk_cfg; 68 break; 69 default: 70 printf("Wrong mmc number %d\n", sdc_no); 71 return -1; 72 } 73 mmchost->mmc_no = sdc_no; 74 75 cd_pin = sunxi_mmc_getcd_gpio(sdc_no); 76 if (cd_pin >= 0) { 77 ret = gpio_request(cd_pin, "mmc_cd"); 78 if (!ret) { 79 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP); 80 ret = gpio_direction_input(cd_pin); 81 } 82 } 83 84 return ret; 85 } 86 87 static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) 88 { 89 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; 90 91 if (hz <= 24000000) { 92 pll = CCM_MMC_CTRL_OSCM24; 93 pll_hz = 24000000; 94 } else { 95 #ifdef CONFIG_MACH_SUN9I 96 pll = CCM_MMC_CTRL_PLL_PERIPH0; 97 pll_hz = clock_get_pll4_periph0(); 98 #else 99 pll = CCM_MMC_CTRL_PLL6; 100 pll_hz = clock_get_pll6(); 101 #endif 102 } 103 104 div = pll_hz / hz; 105 if (pll_hz % hz) 106 div++; 107 108 n = 0; 109 while (div > 16) { 110 n++; 111 div = (div + 1) / 2; 112 } 113 114 if (n > 3) { 115 printf("mmc %u error cannot set clock to %u\n", 116 mmchost->mmc_no, hz); 117 return -1; 118 } 119 120 /* determine delays */ 121 if (hz <= 400000) { 122 oclk_dly = 0; 123 sclk_dly = 7; 124 } else if (hz <= 25000000) { 125 oclk_dly = 0; 126 sclk_dly = 5; 127 } else if (hz <= 50000000) { 128 oclk_dly = 3; 129 sclk_dly = 5; 130 } else { 131 /* hz > 50000000 */ 132 oclk_dly = 2; 133 sclk_dly = 4; 134 } 135 136 writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | 137 CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | 138 CCM_MMC_CTRL_M(div), mmchost->mclkreg); 139 140 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", 141 mmchost->mmc_no, hz, pll_hz, 1u << n, div, 142 pll_hz / (1u << n) / div); 143 144 return 0; 145 } 146 147 static int mmc_clk_io_on(int sdc_no) 148 { 149 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; 150 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 151 152 debug("init mmc %d clock and io\n", sdc_no); 153 154 /* config ahb clock */ 155 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); 156 157 #ifdef CONFIG_SUNXI_GEN_SUN6I 158 /* unassert reset */ 159 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); 160 #endif 161 #if defined(CONFIG_MACH_SUN9I) 162 /* sun9i has a mmc-common module, also set the gate and reset there */ 163 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET, 164 SUNXI_MMC_COMMON_BASE + 4 * sdc_no); 165 #endif 166 167 return mmc_set_mod_clk(mmchost, 24000000); 168 } 169 170 static int mmc_update_clk(struct mmc *mmc) 171 { 172 struct sunxi_mmc_host *mmchost = mmc->priv; 173 unsigned int cmd; 174 unsigned timeout_msecs = 2000; 175 176 cmd = SUNXI_MMC_CMD_START | 177 SUNXI_MMC_CMD_UPCLK_ONLY | 178 SUNXI_MMC_CMD_WAIT_PRE_OVER; 179 writel(cmd, &mmchost->reg->cmd); 180 while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) { 181 if (!timeout_msecs--) 182 return -1; 183 udelay(1000); 184 } 185 186 /* clock update sets various irq status bits, clear these */ 187 writel(readl(&mmchost->reg->rint), &mmchost->reg->rint); 188 189 return 0; 190 } 191 192 static int mmc_config_clock(struct mmc *mmc) 193 { 194 struct sunxi_mmc_host *mmchost = mmc->priv; 195 unsigned rval = readl(&mmchost->reg->clkcr); 196 197 /* Disable Clock */ 198 rval &= ~SUNXI_MMC_CLK_ENABLE; 199 writel(rval, &mmchost->reg->clkcr); 200 if (mmc_update_clk(mmc)) 201 return -1; 202 203 /* Set mod_clk to new rate */ 204 if (mmc_set_mod_clk(mmchost, mmc->clock)) 205 return -1; 206 207 /* Clear internal divider */ 208 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; 209 writel(rval, &mmchost->reg->clkcr); 210 211 /* Re-enable Clock */ 212 rval |= SUNXI_MMC_CLK_ENABLE; 213 writel(rval, &mmchost->reg->clkcr); 214 if (mmc_update_clk(mmc)) 215 return -1; 216 217 return 0; 218 } 219 220 static void sunxi_mmc_set_ios(struct mmc *mmc) 221 { 222 struct sunxi_mmc_host *mmchost = mmc->priv; 223 224 debug("set ios: bus_width: %x, clock: %d\n", 225 mmc->bus_width, mmc->clock); 226 227 /* Change clock first */ 228 if (mmc->clock && mmc_config_clock(mmc) != 0) { 229 mmchost->fatal_err = 1; 230 return; 231 } 232 233 /* Change bus width */ 234 if (mmc->bus_width == 8) 235 writel(0x2, &mmchost->reg->width); 236 else if (mmc->bus_width == 4) 237 writel(0x1, &mmchost->reg->width); 238 else 239 writel(0x0, &mmchost->reg->width); 240 } 241 242 static int sunxi_mmc_core_init(struct mmc *mmc) 243 { 244 struct sunxi_mmc_host *mmchost = mmc->priv; 245 246 /* Reset controller */ 247 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); 248 udelay(1000); 249 250 return 0; 251 } 252 253 static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) 254 { 255 struct sunxi_mmc_host *mmchost = mmc->priv; 256 const int reading = !!(data->flags & MMC_DATA_READ); 257 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : 258 SUNXI_MMC_STATUS_FIFO_FULL; 259 unsigned i; 260 unsigned byte_cnt = data->blocksize * data->blocks; 261 unsigned timeout_msecs = 2000; 262 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); 263 264 /* Always read / write data through the CPU */ 265 setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); 266 267 for (i = 0; i < (byte_cnt >> 2); i++) { 268 while (readl(&mmchost->reg->status) & status_bit) { 269 if (!timeout_msecs--) 270 return -1; 271 udelay(1000); 272 } 273 274 if (reading) 275 buff[i] = readl(&mmchost->reg->fifo); 276 else 277 writel(buff[i], &mmchost->reg->fifo); 278 } 279 280 return 0; 281 } 282 283 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs, 284 unsigned int done_bit, const char *what) 285 { 286 struct sunxi_mmc_host *mmchost = mmc->priv; 287 unsigned int status; 288 289 do { 290 status = readl(&mmchost->reg->rint); 291 if (!timeout_msecs-- || 292 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { 293 debug("%s timeout %x\n", what, 294 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); 295 return TIMEOUT; 296 } 297 udelay(1000); 298 } while (!(status & done_bit)); 299 300 return 0; 301 } 302 303 static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 304 struct mmc_data *data) 305 { 306 struct sunxi_mmc_host *mmchost = mmc->priv; 307 unsigned int cmdval = SUNXI_MMC_CMD_START; 308 unsigned int timeout_msecs; 309 int error = 0; 310 unsigned int status = 0; 311 unsigned int bytecnt = 0; 312 313 if (mmchost->fatal_err) 314 return -1; 315 if (cmd->resp_type & MMC_RSP_BUSY) 316 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); 317 if (cmd->cmdidx == 12) 318 return 0; 319 320 if (!cmd->cmdidx) 321 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 322 if (cmd->resp_type & MMC_RSP_PRESENT) 323 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; 324 if (cmd->resp_type & MMC_RSP_136) 325 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; 326 if (cmd->resp_type & MMC_RSP_CRC) 327 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; 328 329 if (data) { 330 if ((u32) data->dest & 0x3) { 331 error = -1; 332 goto out; 333 } 334 335 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; 336 if (data->flags & MMC_DATA_WRITE) 337 cmdval |= SUNXI_MMC_CMD_WRITE; 338 if (data->blocks > 1) 339 cmdval |= SUNXI_MMC_CMD_AUTO_STOP; 340 writel(data->blocksize, &mmchost->reg->blksz); 341 writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt); 342 } 343 344 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no, 345 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); 346 writel(cmd->cmdarg, &mmchost->reg->arg); 347 348 if (!data) 349 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); 350 351 /* 352 * transfer data and check status 353 * STATREG[2] : FIFO empty 354 * STATREG[3] : FIFO full 355 */ 356 if (data) { 357 int ret = 0; 358 359 bytecnt = data->blocksize * data->blocks; 360 debug("trans data %d bytes\n", bytecnt); 361 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); 362 ret = mmc_trans_data_by_cpu(mmc, data); 363 if (ret) { 364 error = readl(&mmchost->reg->rint) & \ 365 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; 366 error = TIMEOUT; 367 goto out; 368 } 369 } 370 371 error = mmc_rint_wait(mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE, "cmd"); 372 if (error) 373 goto out; 374 375 if (data) { 376 timeout_msecs = 120; 377 debug("cacl timeout %x msec\n", timeout_msecs); 378 error = mmc_rint_wait(mmc, timeout_msecs, 379 data->blocks > 1 ? 380 SUNXI_MMC_RINT_AUTO_COMMAND_DONE : 381 SUNXI_MMC_RINT_DATA_OVER, 382 "data"); 383 if (error) 384 goto out; 385 } 386 387 if (cmd->resp_type & MMC_RSP_BUSY) { 388 timeout_msecs = 2000; 389 do { 390 status = readl(&mmchost->reg->status); 391 if (!timeout_msecs--) { 392 debug("busy timeout\n"); 393 error = TIMEOUT; 394 goto out; 395 } 396 udelay(1000); 397 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); 398 } 399 400 if (cmd->resp_type & MMC_RSP_136) { 401 cmd->response[0] = readl(&mmchost->reg->resp3); 402 cmd->response[1] = readl(&mmchost->reg->resp2); 403 cmd->response[2] = readl(&mmchost->reg->resp1); 404 cmd->response[3] = readl(&mmchost->reg->resp0); 405 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", 406 cmd->response[3], cmd->response[2], 407 cmd->response[1], cmd->response[0]); 408 } else { 409 cmd->response[0] = readl(&mmchost->reg->resp0); 410 debug("mmc resp 0x%08x\n", cmd->response[0]); 411 } 412 out: 413 if (error < 0) { 414 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); 415 mmc_update_clk(mmc); 416 } 417 writel(0xffffffff, &mmchost->reg->rint); 418 writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, 419 &mmchost->reg->gctrl); 420 421 return error; 422 } 423 424 static int sunxi_mmc_getcd(struct mmc *mmc) 425 { 426 struct sunxi_mmc_host *mmchost = mmc->priv; 427 int cd_pin; 428 429 cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no); 430 if (cd_pin < 0) 431 return 1; 432 433 return !gpio_get_value(cd_pin); 434 } 435 436 int sunxi_mmc_has_egon_boot_signature(struct mmc *mmc) 437 { 438 char *buf = malloc(512); 439 int valid_signature = 0; 440 441 if (buf == NULL) 442 panic("Failed to allocate memory\n"); 443 444 if (mmc_getcd(mmc) && mmc_init(mmc) == 0 && 445 mmc->block_dev.block_read(mmc->block_dev.dev, 16, 1, buf) == 1 && 446 strncmp(&buf[4], "eGON.BT0", 8) == 0) 447 valid_signature = 1; 448 449 free(buf); 450 return valid_signature; 451 } 452 453 static const struct mmc_ops sunxi_mmc_ops = { 454 .send_cmd = sunxi_mmc_send_cmd, 455 .set_ios = sunxi_mmc_set_ios, 456 .init = sunxi_mmc_core_init, 457 .getcd = sunxi_mmc_getcd, 458 }; 459 460 struct mmc *sunxi_mmc_init(int sdc_no) 461 { 462 struct mmc_config *cfg = &mmc_host[sdc_no].cfg; 463 464 memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)); 465 466 cfg->name = "SUNXI SD/MMC"; 467 cfg->ops = &sunxi_mmc_ops; 468 469 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 470 cfg->host_caps = MMC_MODE_4BIT; 471 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 472 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 473 474 cfg->f_min = 400000; 475 cfg->f_max = 52000000; 476 477 if (mmc_resource_init(sdc_no) != 0) 478 return NULL; 479 480 mmc_clk_io_on(sdc_no); 481 482 return mmc_create(cfg, &mmc_host[sdc_no]); 483 } 484