1 /* 2 * (C) Copyright 2007-2011 3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4 * Aaron <leafy.myeh@allwinnertech.com> 5 * 6 * MMC driver for allwinner sunxi platform. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <mmc.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/gpio.h> 18 #include <asm/arch/mmc.h> 19 #include <asm-generic/gpio.h> 20 21 struct sunxi_mmc_host { 22 unsigned mmc_no; 23 uint32_t *mclkreg; 24 unsigned fatal_err; 25 struct sunxi_mmc *reg; 26 struct mmc_config cfg; 27 }; 28 29 /* support 4 mmc hosts */ 30 struct sunxi_mmc_host mmc_host[4]; 31 32 static int sunxi_mmc_getcd_gpio(int sdc_no) 33 { 34 switch (sdc_no) { 35 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN); 36 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN); 37 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN); 38 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN); 39 } 40 return -1; 41 } 42 43 static int mmc_resource_init(int sdc_no) 44 { 45 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; 46 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 47 int cd_pin, ret = 0; 48 49 debug("init mmc %d resource\n", sdc_no); 50 51 switch (sdc_no) { 52 case 0: 53 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; 54 mmchost->mclkreg = &ccm->sd0_clk_cfg; 55 break; 56 case 1: 57 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; 58 mmchost->mclkreg = &ccm->sd1_clk_cfg; 59 break; 60 case 2: 61 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; 62 mmchost->mclkreg = &ccm->sd2_clk_cfg; 63 break; 64 case 3: 65 mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; 66 mmchost->mclkreg = &ccm->sd3_clk_cfg; 67 break; 68 default: 69 printf("Wrong mmc number %d\n", sdc_no); 70 return -1; 71 } 72 mmchost->mmc_no = sdc_no; 73 74 cd_pin = sunxi_mmc_getcd_gpio(sdc_no); 75 if (cd_pin != -1) { 76 ret = gpio_request(cd_pin, "mmc_cd"); 77 if (!ret) 78 ret = gpio_direction_input(cd_pin); 79 } 80 81 return ret; 82 } 83 84 static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz) 85 { 86 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; 87 88 if (hz <= 24000000) { 89 pll = CCM_MMC_CTRL_OSCM24; 90 pll_hz = 24000000; 91 } else { 92 pll = CCM_MMC_CTRL_PLL6; 93 pll_hz = clock_get_pll6(); 94 } 95 96 div = pll_hz / hz; 97 if (pll_hz % hz) 98 div++; 99 100 n = 0; 101 while (div > 16) { 102 n++; 103 div = (div + 1) / 2; 104 } 105 106 if (n > 3) { 107 printf("mmc %u error cannot set clock to %u\n", 108 mmchost->mmc_no, hz); 109 return -1; 110 } 111 112 /* determine delays */ 113 if (hz <= 400000) { 114 oclk_dly = 0; 115 sclk_dly = 7; 116 } else if (hz <= 25000000) { 117 oclk_dly = 0; 118 sclk_dly = 5; 119 } else if (hz <= 50000000) { 120 oclk_dly = 3; 121 sclk_dly = 5; 122 } else { 123 /* hz > 50000000 */ 124 oclk_dly = 2; 125 sclk_dly = 4; 126 } 127 128 writel(CCM_MMC_CTRL_ENABLE | pll | CCM_MMC_CTRL_SCLK_DLY(sclk_dly) | 129 CCM_MMC_CTRL_N(n) | CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | 130 CCM_MMC_CTRL_M(div), mmchost->mclkreg); 131 132 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", 133 mmchost->mmc_no, hz, pll_hz, 1u << n, div, 134 pll_hz / (1u << n) / div); 135 136 return 0; 137 } 138 139 static int mmc_clk_io_on(int sdc_no) 140 { 141 struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; 142 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 143 144 debug("init mmc %d clock and io\n", sdc_no); 145 146 /* config ahb clock */ 147 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); 148 149 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) 150 /* unassert reset */ 151 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); 152 #endif 153 154 return mmc_set_mod_clk(mmchost, 24000000); 155 } 156 157 static int mmc_update_clk(struct mmc *mmc) 158 { 159 struct sunxi_mmc_host *mmchost = mmc->priv; 160 unsigned int cmd; 161 unsigned timeout_msecs = 2000; 162 163 cmd = SUNXI_MMC_CMD_START | 164 SUNXI_MMC_CMD_UPCLK_ONLY | 165 SUNXI_MMC_CMD_WAIT_PRE_OVER; 166 writel(cmd, &mmchost->reg->cmd); 167 while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) { 168 if (!timeout_msecs--) 169 return -1; 170 udelay(1000); 171 } 172 173 /* clock update sets various irq status bits, clear these */ 174 writel(readl(&mmchost->reg->rint), &mmchost->reg->rint); 175 176 return 0; 177 } 178 179 static int mmc_config_clock(struct mmc *mmc) 180 { 181 struct sunxi_mmc_host *mmchost = mmc->priv; 182 unsigned rval = readl(&mmchost->reg->clkcr); 183 184 /* Disable Clock */ 185 rval &= ~SUNXI_MMC_CLK_ENABLE; 186 writel(rval, &mmchost->reg->clkcr); 187 if (mmc_update_clk(mmc)) 188 return -1; 189 190 /* Set mod_clk to new rate */ 191 if (mmc_set_mod_clk(mmchost, mmc->clock)) 192 return -1; 193 194 /* Clear internal divider */ 195 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; 196 writel(rval, &mmchost->reg->clkcr); 197 198 /* Re-enable Clock */ 199 rval |= SUNXI_MMC_CLK_ENABLE; 200 writel(rval, &mmchost->reg->clkcr); 201 if (mmc_update_clk(mmc)) 202 return -1; 203 204 return 0; 205 } 206 207 static void mmc_set_ios(struct mmc *mmc) 208 { 209 struct sunxi_mmc_host *mmchost = mmc->priv; 210 211 debug("set ios: bus_width: %x, clock: %d\n", 212 mmc->bus_width, mmc->clock); 213 214 /* Change clock first */ 215 if (mmc->clock && mmc_config_clock(mmc) != 0) { 216 mmchost->fatal_err = 1; 217 return; 218 } 219 220 /* Change bus width */ 221 if (mmc->bus_width == 8) 222 writel(0x2, &mmchost->reg->width); 223 else if (mmc->bus_width == 4) 224 writel(0x1, &mmchost->reg->width); 225 else 226 writel(0x0, &mmchost->reg->width); 227 } 228 229 static int mmc_core_init(struct mmc *mmc) 230 { 231 struct sunxi_mmc_host *mmchost = mmc->priv; 232 233 /* Reset controller */ 234 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); 235 udelay(1000); 236 237 return 0; 238 } 239 240 static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) 241 { 242 struct sunxi_mmc_host *mmchost = mmc->priv; 243 const int reading = !!(data->flags & MMC_DATA_READ); 244 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY : 245 SUNXI_MMC_STATUS_FIFO_FULL; 246 unsigned i; 247 unsigned byte_cnt = data->blocksize * data->blocks; 248 unsigned timeout_msecs = 2000; 249 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); 250 251 /* Always read / write data through the CPU */ 252 setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); 253 254 for (i = 0; i < (byte_cnt >> 2); i++) { 255 while (readl(&mmchost->reg->status) & status_bit) { 256 if (!timeout_msecs--) 257 return -1; 258 udelay(1000); 259 } 260 261 if (reading) 262 buff[i] = readl(&mmchost->reg->fifo); 263 else 264 writel(buff[i], &mmchost->reg->fifo); 265 } 266 267 return 0; 268 } 269 270 static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs, 271 unsigned int done_bit, const char *what) 272 { 273 struct sunxi_mmc_host *mmchost = mmc->priv; 274 unsigned int status; 275 276 do { 277 status = readl(&mmchost->reg->rint); 278 if (!timeout_msecs-- || 279 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { 280 debug("%s timeout %x\n", what, 281 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); 282 return TIMEOUT; 283 } 284 udelay(1000); 285 } while (!(status & done_bit)); 286 287 return 0; 288 } 289 290 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 291 struct mmc_data *data) 292 { 293 struct sunxi_mmc_host *mmchost = mmc->priv; 294 unsigned int cmdval = SUNXI_MMC_CMD_START; 295 unsigned int timeout_msecs; 296 int error = 0; 297 unsigned int status = 0; 298 unsigned int bytecnt = 0; 299 300 if (mmchost->fatal_err) 301 return -1; 302 if (cmd->resp_type & MMC_RSP_BUSY) 303 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); 304 if (cmd->cmdidx == 12) 305 return 0; 306 307 if (!cmd->cmdidx) 308 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 309 if (cmd->resp_type & MMC_RSP_PRESENT) 310 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; 311 if (cmd->resp_type & MMC_RSP_136) 312 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; 313 if (cmd->resp_type & MMC_RSP_CRC) 314 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; 315 316 if (data) { 317 if ((u32) data->dest & 0x3) { 318 error = -1; 319 goto out; 320 } 321 322 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; 323 if (data->flags & MMC_DATA_WRITE) 324 cmdval |= SUNXI_MMC_CMD_WRITE; 325 if (data->blocks > 1) 326 cmdval |= SUNXI_MMC_CMD_AUTO_STOP; 327 writel(data->blocksize, &mmchost->reg->blksz); 328 writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt); 329 } 330 331 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no, 332 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); 333 writel(cmd->cmdarg, &mmchost->reg->arg); 334 335 if (!data) 336 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); 337 338 /* 339 * transfer data and check status 340 * STATREG[2] : FIFO empty 341 * STATREG[3] : FIFO full 342 */ 343 if (data) { 344 int ret = 0; 345 346 bytecnt = data->blocksize * data->blocks; 347 debug("trans data %d bytes\n", bytecnt); 348 writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); 349 ret = mmc_trans_data_by_cpu(mmc, data); 350 if (ret) { 351 error = readl(&mmchost->reg->rint) & \ 352 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; 353 error = TIMEOUT; 354 goto out; 355 } 356 } 357 358 error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd"); 359 if (error) 360 goto out; 361 362 if (data) { 363 timeout_msecs = 120; 364 debug("cacl timeout %x msec\n", timeout_msecs); 365 error = mmc_rint_wait(mmc, timeout_msecs, 366 data->blocks > 1 ? 367 SUNXI_MMC_RINT_AUTO_COMMAND_DONE : 368 SUNXI_MMC_RINT_DATA_OVER, 369 "data"); 370 if (error) 371 goto out; 372 } 373 374 if (cmd->resp_type & MMC_RSP_BUSY) { 375 timeout_msecs = 2000; 376 do { 377 status = readl(&mmchost->reg->status); 378 if (!timeout_msecs--) { 379 debug("busy timeout\n"); 380 error = TIMEOUT; 381 goto out; 382 } 383 udelay(1000); 384 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); 385 } 386 387 if (cmd->resp_type & MMC_RSP_136) { 388 cmd->response[0] = readl(&mmchost->reg->resp3); 389 cmd->response[1] = readl(&mmchost->reg->resp2); 390 cmd->response[2] = readl(&mmchost->reg->resp1); 391 cmd->response[3] = readl(&mmchost->reg->resp0); 392 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", 393 cmd->response[3], cmd->response[2], 394 cmd->response[1], cmd->response[0]); 395 } else { 396 cmd->response[0] = readl(&mmchost->reg->resp0); 397 debug("mmc resp 0x%08x\n", cmd->response[0]); 398 } 399 out: 400 if (error < 0) { 401 writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); 402 mmc_update_clk(mmc); 403 } 404 writel(0xffffffff, &mmchost->reg->rint); 405 writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, 406 &mmchost->reg->gctrl); 407 408 return error; 409 } 410 411 static int sunxi_mmc_getcd(struct mmc *mmc) 412 { 413 struct sunxi_mmc_host *mmchost = mmc->priv; 414 int cd_pin; 415 416 cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no); 417 if (cd_pin == -1) 418 return 1; 419 420 return !gpio_get_value(cd_pin); 421 } 422 423 static const struct mmc_ops sunxi_mmc_ops = { 424 .send_cmd = mmc_send_cmd, 425 .set_ios = mmc_set_ios, 426 .init = mmc_core_init, 427 .getcd = sunxi_mmc_getcd, 428 }; 429 430 struct mmc *sunxi_mmc_init(int sdc_no) 431 { 432 struct mmc_config *cfg = &mmc_host[sdc_no].cfg; 433 434 memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)); 435 436 cfg->name = "SUNXI SD/MMC"; 437 cfg->ops = &sunxi_mmc_ops; 438 439 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 440 cfg->host_caps = MMC_MODE_4BIT; 441 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 442 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I) 443 cfg->host_caps |= MMC_MODE_HC; 444 #endif 445 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 446 447 cfg->f_min = 400000; 448 cfg->f_max = 52000000; 449 450 if (mmc_resource_init(sdc_no) != 0) 451 return NULL; 452 453 mmc_clk_io_on(sdc_no); 454 455 return mmc_create(cfg, &mmc_host[sdc_no]); 456 } 457