1 /* 2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <fdtdec.h> 12 #include <libfdt.h> 13 #include <mmc.h> 14 #include <reset.h> 15 #include <asm/io.h> 16 #include <asm/gpio.h> 17 #include <linux/iopoll.h> 18 19 struct stm32_sdmmc2_plat { 20 struct mmc_config cfg; 21 struct mmc mmc; 22 }; 23 24 struct stm32_sdmmc2_priv { 25 fdt_addr_t base; 26 struct clk clk; 27 struct reset_ctl reset_ctl; 28 struct gpio_desc cd_gpio; 29 u32 clk_reg_msk; 30 u32 pwr_reg_msk; 31 }; 32 33 struct stm32_sdmmc2_ctx { 34 u32 cache_start; 35 u32 cache_end; 36 u32 data_length; 37 bool dpsm_abort; 38 }; 39 40 /* SDMMC REGISTERS OFFSET */ 41 #define SDMMC_POWER 0x00 /* SDMMC power control */ 42 #define SDMMC_CLKCR 0x04 /* SDMMC clock control */ 43 #define SDMMC_ARG 0x08 /* SDMMC argument */ 44 #define SDMMC_CMD 0x0C /* SDMMC command */ 45 #define SDMMC_RESP1 0x14 /* SDMMC response 1 */ 46 #define SDMMC_RESP2 0x18 /* SDMMC response 2 */ 47 #define SDMMC_RESP3 0x1C /* SDMMC response 3 */ 48 #define SDMMC_RESP4 0x20 /* SDMMC response 4 */ 49 #define SDMMC_DTIMER 0x24 /* SDMMC data timer */ 50 #define SDMMC_DLEN 0x28 /* SDMMC data length */ 51 #define SDMMC_DCTRL 0x2C /* SDMMC data control */ 52 #define SDMMC_DCOUNT 0x30 /* SDMMC data counter */ 53 #define SDMMC_STA 0x34 /* SDMMC status */ 54 #define SDMMC_ICR 0x38 /* SDMMC interrupt clear */ 55 #define SDMMC_MASK 0x3C /* SDMMC mask */ 56 #define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */ 57 #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */ 58 59 /* SDMMC_POWER register */ 60 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 61 #define SDMMC_POWER_VSWITCH BIT(2) 62 #define SDMMC_POWER_VSWITCHEN BIT(3) 63 #define SDMMC_POWER_DIRPOL BIT(4) 64 65 /* SDMMC_CLKCR register */ 66 #define SDMMC_CLKCR_CLKDIV GENMASK(9, 0) 67 #define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV 68 #define SDMMC_CLKCR_PWRSAV BIT(12) 69 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 70 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 71 #define SDMMC_CLKCR_NEGEDGE BIT(16) 72 #define SDMMC_CLKCR_HWFC_EN BIT(17) 73 #define SDMMC_CLKCR_DDR BIT(18) 74 #define SDMMC_CLKCR_BUSSPEED BIT(19) 75 #define SDMMC_CLKCR_SELCLKRX GENMASK(21, 20) 76 77 /* SDMMC_CMD register */ 78 #define SDMMC_CMD_CMDINDEX GENMASK(5, 0) 79 #define SDMMC_CMD_CMDTRANS BIT(6) 80 #define SDMMC_CMD_CMDSTOP BIT(7) 81 #define SDMMC_CMD_WAITRESP GENMASK(9, 8) 82 #define SDMMC_CMD_WAITRESP_0 BIT(8) 83 #define SDMMC_CMD_WAITRESP_1 BIT(9) 84 #define SDMMC_CMD_WAITINT BIT(10) 85 #define SDMMC_CMD_WAITPEND BIT(11) 86 #define SDMMC_CMD_CPSMEN BIT(12) 87 #define SDMMC_CMD_DTHOLD BIT(13) 88 #define SDMMC_CMD_BOOTMODE BIT(14) 89 #define SDMMC_CMD_BOOTEN BIT(15) 90 #define SDMMC_CMD_CMDSUSPEND BIT(16) 91 92 /* SDMMC_DCTRL register */ 93 #define SDMMC_DCTRL_DTEN BIT(0) 94 #define SDMMC_DCTRL_DTDIR BIT(1) 95 #define SDMMC_DCTRL_DTMODE GENMASK(3, 2) 96 #define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4) 97 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4 98 #define SDMMC_DCTRL_RWSTART BIT(8) 99 #define SDMMC_DCTRL_RWSTOP BIT(9) 100 #define SDMMC_DCTRL_RWMOD BIT(10) 101 #define SDMMC_DCTRL_SDMMCEN BIT(11) 102 #define SDMMC_DCTRL_BOOTACKEN BIT(12) 103 #define SDMMC_DCTRL_FIFORST BIT(13) 104 105 /* SDMMC_STA register */ 106 #define SDMMC_STA_CCRCFAIL BIT(0) 107 #define SDMMC_STA_DCRCFAIL BIT(1) 108 #define SDMMC_STA_CTIMEOUT BIT(2) 109 #define SDMMC_STA_DTIMEOUT BIT(3) 110 #define SDMMC_STA_TXUNDERR BIT(4) 111 #define SDMMC_STA_RXOVERR BIT(5) 112 #define SDMMC_STA_CMDREND BIT(6) 113 #define SDMMC_STA_CMDSENT BIT(7) 114 #define SDMMC_STA_DATAEND BIT(8) 115 #define SDMMC_STA_DHOLD BIT(9) 116 #define SDMMC_STA_DBCKEND BIT(10) 117 #define SDMMC_STA_DABORT BIT(11) 118 #define SDMMC_STA_DPSMACT BIT(12) 119 #define SDMMC_STA_CPSMACT BIT(13) 120 #define SDMMC_STA_TXFIFOHE BIT(14) 121 #define SDMMC_STA_RXFIFOHF BIT(15) 122 #define SDMMC_STA_TXFIFOF BIT(16) 123 #define SDMMC_STA_RXFIFOF BIT(17) 124 #define SDMMC_STA_TXFIFOE BIT(18) 125 #define SDMMC_STA_RXFIFOE BIT(19) 126 #define SDMMC_STA_BUSYD0 BIT(20) 127 #define SDMMC_STA_BUSYD0END BIT(21) 128 #define SDMMC_STA_SDMMCIT BIT(22) 129 #define SDMMC_STA_ACKFAIL BIT(23) 130 #define SDMMC_STA_ACKTIMEOUT BIT(24) 131 #define SDMMC_STA_VSWEND BIT(25) 132 #define SDMMC_STA_CKSTOP BIT(26) 133 #define SDMMC_STA_IDMATE BIT(27) 134 #define SDMMC_STA_IDMABTC BIT(28) 135 136 /* SDMMC_ICR register */ 137 #define SDMMC_ICR_CCRCFAILC BIT(0) 138 #define SDMMC_ICR_DCRCFAILC BIT(1) 139 #define SDMMC_ICR_CTIMEOUTC BIT(2) 140 #define SDMMC_ICR_DTIMEOUTC BIT(3) 141 #define SDMMC_ICR_TXUNDERRC BIT(4) 142 #define SDMMC_ICR_RXOVERRC BIT(5) 143 #define SDMMC_ICR_CMDRENDC BIT(6) 144 #define SDMMC_ICR_CMDSENTC BIT(7) 145 #define SDMMC_ICR_DATAENDC BIT(8) 146 #define SDMMC_ICR_DHOLDC BIT(9) 147 #define SDMMC_ICR_DBCKENDC BIT(10) 148 #define SDMMC_ICR_DABORTC BIT(11) 149 #define SDMMC_ICR_BUSYD0ENDC BIT(21) 150 #define SDMMC_ICR_SDMMCITC BIT(22) 151 #define SDMMC_ICR_ACKFAILC BIT(23) 152 #define SDMMC_ICR_ACKTIMEOUTC BIT(24) 153 #define SDMMC_ICR_VSWENDC BIT(25) 154 #define SDMMC_ICR_CKSTOPC BIT(26) 155 #define SDMMC_ICR_IDMATEC BIT(27) 156 #define SDMMC_ICR_IDMABTCC BIT(28) 157 #define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0))) 158 159 /* SDMMC_MASK register */ 160 #define SDMMC_MASK_CCRCFAILIE BIT(0) 161 #define SDMMC_MASK_DCRCFAILIE BIT(1) 162 #define SDMMC_MASK_CTIMEOUTIE BIT(2) 163 #define SDMMC_MASK_DTIMEOUTIE BIT(3) 164 #define SDMMC_MASK_TXUNDERRIE BIT(4) 165 #define SDMMC_MASK_RXOVERRIE BIT(5) 166 #define SDMMC_MASK_CMDRENDIE BIT(6) 167 #define SDMMC_MASK_CMDSENTIE BIT(7) 168 #define SDMMC_MASK_DATAENDIE BIT(8) 169 #define SDMMC_MASK_DHOLDIE BIT(9) 170 #define SDMMC_MASK_DBCKENDIE BIT(10) 171 #define SDMMC_MASK_DABORTIE BIT(11) 172 #define SDMMC_MASK_TXFIFOHEIE BIT(14) 173 #define SDMMC_MASK_RXFIFOHFIE BIT(15) 174 #define SDMMC_MASK_RXFIFOFIE BIT(17) 175 #define SDMMC_MASK_TXFIFOEIE BIT(18) 176 #define SDMMC_MASK_BUSYD0ENDIE BIT(21) 177 #define SDMMC_MASK_SDMMCITIE BIT(22) 178 #define SDMMC_MASK_ACKFAILIE BIT(23) 179 #define SDMMC_MASK_ACKTIMEOUTIE BIT(24) 180 #define SDMMC_MASK_VSWENDIE BIT(25) 181 #define SDMMC_MASK_CKSTOPIE BIT(26) 182 #define SDMMC_MASK_IDMABTCIE BIT(28) 183 184 /* SDMMC_IDMACTRL register */ 185 #define SDMMC_IDMACTRL_IDMAEN BIT(0) 186 187 #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF 188 189 DECLARE_GLOBAL_DATA_PTR; 190 191 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv, 192 struct mmc_data *data, 193 struct stm32_sdmmc2_ctx *ctx) 194 { 195 u32 data_ctrl, idmabase0; 196 197 /* Configure the SDMMC DPSM (Data Path State Machine) */ 198 data_ctrl = (__ilog2(data->blocksize) << 199 SDMMC_DCTRL_DBLOCKSIZE_SHIFT) & 200 SDMMC_DCTRL_DBLOCKSIZE; 201 202 if (data->flags & MMC_DATA_READ) { 203 data_ctrl |= SDMMC_DCTRL_DTDIR; 204 idmabase0 = (u32)data->dest; 205 } else { 206 idmabase0 = (u32)data->src; 207 } 208 209 /* Set the SDMMC Data TimeOut value */ 210 writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER); 211 212 /* Set the SDMMC DataLength value */ 213 writel(ctx->data_length, priv->base + SDMMC_DLEN); 214 215 /* Write to SDMMC DCTRL */ 216 writel(data_ctrl, priv->base + SDMMC_DCTRL); 217 218 /* Cache align */ 219 ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN); 220 ctx->cache_end = roundup(idmabase0 + ctx->data_length, 221 ARCH_DMA_MINALIGN); 222 223 /* 224 * Flush data cache before DMA start (clean and invalidate) 225 * Clean also needed for read 226 * Avoid issue on buffer not cached-aligned 227 */ 228 flush_dcache_range(ctx->cache_start, ctx->cache_end); 229 230 /* Enable internal DMA */ 231 writel(idmabase0, priv->base + SDMMC_IDMABASE0); 232 writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL); 233 } 234 235 static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv, 236 struct mmc_cmd *cmd, u32 cmd_param) 237 { 238 if (readl(priv->base + SDMMC_ARG) & SDMMC_CMD_CPSMEN) 239 writel(0, priv->base + SDMMC_ARG); 240 241 cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN; 242 if (cmd->resp_type & MMC_RSP_PRESENT) { 243 if (cmd->resp_type & MMC_RSP_136) 244 cmd_param |= SDMMC_CMD_WAITRESP; 245 else if (cmd->resp_type & MMC_RSP_CRC) 246 cmd_param |= SDMMC_CMD_WAITRESP_0; 247 else 248 cmd_param |= SDMMC_CMD_WAITRESP_1; 249 } 250 251 /* Clear flags */ 252 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); 253 254 /* Set SDMMC argument value */ 255 writel(cmd->cmdarg, priv->base + SDMMC_ARG); 256 257 /* Set SDMMC command parameters */ 258 writel(cmd_param, priv->base + SDMMC_CMD); 259 } 260 261 static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv, 262 struct mmc_cmd *cmd, 263 struct stm32_sdmmc2_ctx *ctx) 264 { 265 u32 mask = SDMMC_STA_CTIMEOUT; 266 u32 status; 267 int ret; 268 269 if (cmd->resp_type & MMC_RSP_PRESENT) { 270 mask |= SDMMC_STA_CMDREND; 271 if (cmd->resp_type & MMC_RSP_CRC) 272 mask |= SDMMC_STA_CCRCFAIL; 273 } else { 274 mask |= SDMMC_STA_CMDSENT; 275 } 276 277 /* Polling status register */ 278 ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask, 279 10000); 280 281 if (ret < 0) { 282 debug("%s: timeout reading SDMMC_STA register\n", __func__); 283 ctx->dpsm_abort = true; 284 return ret; 285 } 286 287 /* Check status */ 288 if (status & SDMMC_STA_CTIMEOUT) { 289 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n", 290 __func__, status, cmd->cmdidx); 291 ctx->dpsm_abort = true; 292 return -ETIMEDOUT; 293 } 294 295 if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) { 296 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n", 297 __func__, status, cmd->cmdidx); 298 ctx->dpsm_abort = true; 299 return -EILSEQ; 300 } 301 302 if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) { 303 cmd->response[0] = readl(priv->base + SDMMC_RESP1); 304 if (cmd->resp_type & MMC_RSP_136) { 305 cmd->response[1] = readl(priv->base + SDMMC_RESP2); 306 cmd->response[2] = readl(priv->base + SDMMC_RESP3); 307 cmd->response[3] = readl(priv->base + SDMMC_RESP4); 308 } 309 } 310 311 return 0; 312 } 313 314 static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv, 315 struct mmc_cmd *cmd, 316 struct mmc_data *data, 317 struct stm32_sdmmc2_ctx *ctx) 318 { 319 u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT | 320 SDMMC_STA_IDMATE | SDMMC_STA_DATAEND; 321 u32 status; 322 323 if (data->flags & MMC_DATA_READ) 324 mask |= SDMMC_STA_RXOVERR; 325 else 326 mask |= SDMMC_STA_TXUNDERR; 327 328 status = readl(priv->base + SDMMC_STA); 329 while (!(status & mask)) 330 status = readl(priv->base + SDMMC_STA); 331 332 /* 333 * Need invalidate the dcache again to avoid any 334 * cache-refill during the DMA operations (pre-fetching) 335 */ 336 if (data->flags & MMC_DATA_READ) 337 invalidate_dcache_range(ctx->cache_start, ctx->cache_end); 338 339 if (status & SDMMC_STA_DCRCFAIL) { 340 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n", 341 __func__, status, cmd->cmdidx); 342 if (readl(priv->base + SDMMC_DCOUNT)) 343 ctx->dpsm_abort = true; 344 return -EILSEQ; 345 } 346 347 if (status & SDMMC_STA_DTIMEOUT) { 348 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n", 349 __func__, status, cmd->cmdidx); 350 ctx->dpsm_abort = true; 351 return -ETIMEDOUT; 352 } 353 354 if (status & SDMMC_STA_TXUNDERR) { 355 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n", 356 __func__, status, cmd->cmdidx); 357 ctx->dpsm_abort = true; 358 return -EIO; 359 } 360 361 if (status & SDMMC_STA_RXOVERR) { 362 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n", 363 __func__, status, cmd->cmdidx); 364 ctx->dpsm_abort = true; 365 return -EIO; 366 } 367 368 if (status & SDMMC_STA_IDMATE) { 369 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n", 370 __func__, status, cmd->cmdidx); 371 ctx->dpsm_abort = true; 372 return -EIO; 373 } 374 375 return 0; 376 } 377 378 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 379 struct mmc_data *data) 380 { 381 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); 382 struct stm32_sdmmc2_ctx ctx; 383 u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0; 384 int ret, retry = 3; 385 386 retry_cmd: 387 ctx.data_length = 0; 388 ctx.dpsm_abort = false; 389 390 if (data) { 391 ctx.data_length = data->blocks * data->blocksize; 392 stm32_sdmmc2_start_data(priv, data, &ctx); 393 } 394 395 stm32_sdmmc2_start_cmd(priv, cmd, cmdat); 396 397 debug("%s: send cmd %d data: 0x%x @ 0x%x\n", 398 __func__, cmd->cmdidx, 399 data ? ctx.data_length : 0, (unsigned int)data); 400 401 ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx); 402 403 if (data && !ret) 404 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx); 405 406 /* Clear flags */ 407 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); 408 if (data) 409 writel(0x0, priv->base + SDMMC_IDMACTRL); 410 411 /* 412 * To stop Data Path State Machine, a stop_transmission command 413 * shall be send on cmd or data errors. 414 */ 415 if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) { 416 struct mmc_cmd stop_cmd; 417 418 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 419 stop_cmd.cmdarg = 0; 420 stop_cmd.resp_type = MMC_RSP_R1b; 421 422 debug("%s: send STOP command to abort dpsm treatments\n", 423 __func__); 424 425 stm32_sdmmc2_start_cmd(priv, &stop_cmd, SDMMC_CMD_CMDSTOP); 426 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx); 427 428 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); 429 } 430 431 if ((ret != -ETIMEDOUT) && (ret != 0) && retry) { 432 printf("%s: cmd %d failed, retrying ...\n", 433 __func__, cmd->cmdidx); 434 retry--; 435 goto retry_cmd; 436 } 437 438 debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret); 439 440 return ret; 441 } 442 443 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv) 444 { 445 /* Reset */ 446 reset_assert(&priv->reset_ctl); 447 udelay(2); 448 reset_deassert(&priv->reset_ctl); 449 450 udelay(1000); 451 452 /* Set Power State to ON */ 453 writel(SDMMC_POWER_PWRCTRL | priv->pwr_reg_msk, priv->base + SDMMC_POWER); 454 455 /* 456 * 1ms: required power up waiting time before starting the 457 * SD initialization sequence 458 */ 459 udelay(1000); 460 } 461 462 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1) 463 static int stm32_sdmmc2_set_ios(struct udevice *dev) 464 { 465 struct mmc *mmc = mmc_get_mmc_dev(dev); 466 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); 467 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev); 468 struct mmc_config *cfg = &plat->cfg; 469 u32 desired = mmc->clock; 470 u32 sys_clock = clk_get_rate(&priv->clk); 471 u32 clk = 0; 472 473 debug("%s: bus_with = %d, clock = %d\n", __func__, 474 mmc->bus_width, mmc->clock); 475 476 if ((mmc->bus_width == 1) && (desired == cfg->f_min)) 477 stm32_sdmmc2_pwron(priv); 478 479 /* 480 * clk_div = 0 => command and data generated on SDMMCCLK falling edge 481 * clk_div > 0 and NEGEDGE = 0 => command and data generated on 482 * SDMMCCLK rising edge 483 * clk_div > 0 and NEGEDGE = 1 => command and data generated on 484 * SDMMCCLK falling edge 485 */ 486 if (desired && ((sys_clock > desired) || 487 IS_RISING_EDGE(priv->clk_reg_msk))) { 488 clk = DIV_ROUND_UP(sys_clock, 2 * desired); 489 if (clk > SDMMC_CLKCR_CLKDIV_MAX) 490 clk = SDMMC_CLKCR_CLKDIV_MAX; 491 } 492 493 if (mmc->bus_width == 4) 494 clk |= SDMMC_CLKCR_WIDBUS_4; 495 if (mmc->bus_width == 8) 496 clk |= SDMMC_CLKCR_WIDBUS_8; 497 498 writel(clk | priv->clk_reg_msk, priv->base + SDMMC_CLKCR); 499 500 return 0; 501 } 502 503 static int stm32_sdmmc2_getcd(struct udevice *dev) 504 { 505 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); 506 507 debug("stm32_sdmmc2_getcd called\n"); 508 509 if (dm_gpio_is_valid(&priv->cd_gpio)) 510 return dm_gpio_get_value(&priv->cd_gpio); 511 512 return 1; 513 } 514 515 static const struct dm_mmc_ops stm32_sdmmc2_ops = { 516 .send_cmd = stm32_sdmmc2_send_cmd, 517 .set_ios = stm32_sdmmc2_set_ios, 518 .get_cd = stm32_sdmmc2_getcd, 519 }; 520 521 static int stm32_sdmmc2_probe(struct udevice *dev) 522 { 523 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 524 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev); 525 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); 526 struct mmc_config *cfg = &plat->cfg; 527 int ret; 528 529 priv->base = dev_read_addr(dev); 530 if (priv->base == FDT_ADDR_T_NONE) 531 return -EINVAL; 532 533 if (dev_read_bool(dev, "st,negedge")) 534 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE; 535 if (dev_read_bool(dev, "st,dirpol")) 536 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL; 537 538 ret = clk_get_by_index(dev, 0, &priv->clk); 539 if (ret) 540 return ret; 541 542 ret = clk_enable(&priv->clk); 543 if (ret) 544 goto clk_free; 545 546 ret = reset_get_by_index(dev, 0, &priv->reset_ctl); 547 if (ret) 548 goto clk_disable; 549 550 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, 551 GPIOD_IS_IN); 552 553 cfg->f_min = 400000; 554 cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000); 555 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 556 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 557 cfg->name = "STM32 SDMMC2"; 558 559 cfg->host_caps = 0; 560 if (cfg->f_max > 25000000) 561 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 562 563 switch (dev_read_u32_default(dev, "bus-width", 1)) { 564 case 8: 565 cfg->host_caps |= MMC_MODE_8BIT; 566 case 4: 567 cfg->host_caps |= MMC_MODE_4BIT; 568 break; 569 case 1: 570 break; 571 default: 572 pr_err("invalid \"bus-width\" property, force to 1\n"); 573 } 574 575 upriv->mmc = &plat->mmc; 576 577 return 0; 578 579 clk_disable: 580 clk_disable(&priv->clk); 581 clk_free: 582 clk_free(&priv->clk); 583 584 return ret; 585 } 586 587 int stm32_sdmmc_bind(struct udevice *dev) 588 { 589 struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev); 590 591 return mmc_bind(dev, &plat->mmc, &plat->cfg); 592 } 593 594 static const struct udevice_id stm32_sdmmc2_ids[] = { 595 { .compatible = "st,stm32-sdmmc2" }, 596 { } 597 }; 598 599 U_BOOT_DRIVER(stm32_sdmmc2) = { 600 .name = "stm32_sdmmc2", 601 .id = UCLASS_MMC, 602 .of_match = stm32_sdmmc2_ids, 603 .ops = &stm32_sdmmc2_ops, 604 .probe = stm32_sdmmc2_probe, 605 .bind = stm32_sdmmc_bind, 606 .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv), 607 .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat), 608 }; 609