1 /* 2 * Copyright (c) 2017 3 * Patrice Chotard <patrice.chotard@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <mmc.h> 11 #include <sdhci.h> 12 #include <asm/arch/sdhci.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 struct sti_sdhci_plat { 17 struct mmc_config cfg; 18 struct mmc mmc; 19 }; 20 21 /* 22 * used to get access to MMC1 reset, 23 * will be removed when STi reset driver will be available 24 */ 25 #define STIH410_SYSCONF5_BASE 0x092b0000 26 27 /** 28 * sti_mmc_core_config: configure the Arasan HC 29 * @regbase: base address 30 * @mmc_instance: mmc instance id 31 * Description: this function is to configure the Arasan MMC HC. 32 * This should be called when the system starts in case of, on the SoC, 33 * it is needed to configure the host controller. 34 * This happens on some SoCs, i.e. StiH410, where the MMC0 inside the flashSS 35 * needs to be configured as MMC 4.5 to have full capabilities. 36 * W/o these settings the SDHCI could configure and use the embedded controller 37 * with limited features. 38 */ 39 static void sti_mmc_core_config(const u32 regbase, int mmc_instance) 40 { 41 unsigned long *sysconf; 42 43 /* only MMC1 has a reset line */ 44 if (mmc_instance) { 45 sysconf = (unsigned long *)(STIH410_SYSCONF5_BASE + 46 ST_MMC_CCONFIG_REG_5); 47 generic_set_bit(SYSCONF_MMC1_ENABLE_BIT, sysconf); 48 } 49 50 writel(STI_FLASHSS_MMC_CORE_CONFIG_1, 51 regbase + FLASHSS_MMC_CORE_CONFIG_1); 52 53 if (mmc_instance) { 54 writel(STI_FLASHSS_MMC_CORE_CONFIG2, 55 regbase + FLASHSS_MMC_CORE_CONFIG_2); 56 writel(STI_FLASHSS_MMC_CORE_CONFIG3, 57 regbase + FLASHSS_MMC_CORE_CONFIG_3); 58 } else { 59 writel(STI_FLASHSS_SDCARD_CORE_CONFIG2, 60 regbase + FLASHSS_MMC_CORE_CONFIG_2); 61 writel(STI_FLASHSS_SDCARD_CORE_CONFIG3, 62 regbase + FLASHSS_MMC_CORE_CONFIG_3); 63 } 64 writel(STI_FLASHSS_MMC_CORE_CONFIG4, 65 regbase + FLASHSS_MMC_CORE_CONFIG_4); 66 } 67 68 static int sti_sdhci_probe(struct udevice *dev) 69 { 70 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 71 struct sti_sdhci_plat *plat = dev_get_platdata(dev); 72 struct sdhci_host *host = dev_get_priv(dev); 73 int ret, mmc_instance; 74 75 /* 76 * identify current mmc instance, mmc1 has a reset, not mmc0 77 * MMC0 is wired to the SD slot, 78 * MMC1 is wired on the high speed connector 79 */ 80 81 if (fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "resets", NULL)) 82 mmc_instance = 1; 83 else 84 mmc_instance = 0; 85 86 sti_mmc_core_config((const u32) host->ioaddr, mmc_instance); 87 88 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | 89 SDHCI_QUIRK_32BIT_DMA_ADDR | 90 SDHCI_QUIRK_NO_HISPD_BIT; 91 92 host->host_caps = MMC_MODE_DDR_52MHz; 93 94 ret = sdhci_setup_cfg(&plat->cfg, host, 50000000, 400000); 95 if (ret) 96 return ret; 97 98 host->mmc = &plat->mmc; 99 host->mmc->priv = host; 100 host->mmc->dev = dev; 101 upriv->mmc = host->mmc; 102 103 return sdhci_probe(dev); 104 } 105 106 static int sti_sdhci_ofdata_to_platdata(struct udevice *dev) 107 { 108 struct sdhci_host *host = dev_get_priv(dev); 109 110 host->name = strdup(dev->name); 111 host->ioaddr = (void *)dev_get_addr(dev); 112 113 host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 114 "bus-width", 4); 115 116 return 0; 117 } 118 119 static int sti_sdhci_bind(struct udevice *dev) 120 { 121 struct sti_sdhci_plat *plat = dev_get_platdata(dev); 122 123 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 124 } 125 126 static const struct udevice_id sti_sdhci_ids[] = { 127 { .compatible = "st,sdhci" }, 128 { } 129 }; 130 131 U_BOOT_DRIVER(sti_mmc) = { 132 .name = "sti_sdhci", 133 .id = UCLASS_MMC, 134 .of_match = sti_sdhci_ids, 135 .bind = sti_sdhci_bind, 136 .ops = &sdhci_ops, 137 .ofdata_to_platdata = sti_sdhci_ofdata_to_platdata, 138 .probe = sti_sdhci_probe, 139 .priv_auto_alloc_size = sizeof(struct sdhci_host), 140 .platdata_auto_alloc_size = sizeof(struct sti_sdhci_plat), 141 }; 142